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Tsirkin" , Alejandro Jimenez , Ani Sinha , "Eduardo Habkost" , Igor Mammedov , "Marcel Apfelbaum" , Paolo Bonzini , Richard Henderson , Sairaj Kodilkar , CC: , Subject: [PATCH 2/8] amd_iommu: update PA, GVA and VA size macros Date: Mon, 11 May 2026 18:09:31 +0530 Message-ID: <20260511123937.32743-3-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511123937.32743-1-sarunkod@amd.com> References: <20260511123937.32743-1-sarunkod@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B0:EE_|SN7PR12MB7346:EE_ X-MS-Office365-Filtering-Correlation-Id: 827db31f-3784-4e90-d933-08deaf5a9776 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700016|1800799024|82310400026|921020|11063799003|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: OK57r2m225Ec/olBBmP5c2+8g0uSUWlSsXyVOeTtHpaPZO1bEP15sgEI5y7RxV3Ta/Zmnrk66ZjEveglPjK5pYPy5Hh1Sr8sJoDJfrXVu03n+OX9z02XJhRqvkYh8c6LBO+3m0+OS4Sk9PqYgvxAmTUtP5o38bBlu6MWmRaoFhwLzhjOnvBl6oOCqGRP/7gf0KtlVeoItPGJEwsoTO4HMoqGAcII4oQjaqNQ5gXvnDxaeF1v9qK0mH9PATjRyJ4CAXK/ignHAV2m9UwhXEfD1tNQTk29FzCXmh3Y8/nn440rY6K+K/76QrXHdYFip3AviF9YhDKBBUwUehHyj/StOBEqkxuHU7F2BEcQXaidyHuaRYVOiN7295cZslyFsZ+CdzuO/UKzFuzjdKDctNvGcFKDhfAdSbwA0Ti9bGvFN/NrIr8+N1OgJO9M6htKnpNoFmk4zFyH+FgldzaV4ncUmgLiN4rYAkayPI1kUsKYizXa4YMS1dLEWvVgOhIiZLjmeVIWuZHIPv8OeMQysi+5mwLoSWQZne0c8+hU0DlhdEhiLs8R+lFUKBKdAmlrDr4CSgsygyhYL/B4TpoF3Si0DvE2MR2ecdFcFRhYKn9+vaKbVpG/GX618wXerIxO2H27cQ0v6HkTwGuMoQNhMWfbXX6yv4Hx6rB1C8DA0ibg0FZ+VQL/bEwKk++diPQd0BnealuyyrjZF/0FuJQl/Jf5zHVGc8OO2k7MyUj6JmP51w1PnMikBjRlgULasIhpn5j+qxO8Sg8PybKesjaUp+0NLQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(36860700016)(1800799024)(82310400026)(921020)(11063799003)(56012099003)(22082099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: O805dEtN/aW77VO6V2ICj2ntvpdr+jQKZBg9R3cmKZHjjyyw763SGlbRZfp9XINBjeTaSv/pPl6+cYeYW17nLnDdB4gKA9x70iKYMLoC4baTlM3rn4qOJXosH/v3X4JIRvUnnOlsxD3xBwx4BWXxdHPtYDSEqDLEp7FcD4vac6kODv0Njmy2MLqJ4XFTplV4z42phxmz1c5gNDldvK7CfymvcpRGrf7p1JS7k1uMQaFGBqXMwNclBciv+PdGQBadjvdFZXKZvmyaZs4sDZLNSTboOwYNd8G0NX0RzzxFpB0YJoRTf0Dg4eMJmDtF92TT/9qIbH58RLpkS1im8VOdluRC16fPn5VBPGgWrpxb8IxEa4rZq1kJgyv2w6iUjRwufKj8yBrscZCAX2h11m4zBgiJzRCpudgG//iDL+GDqt1AfcNc/S7K5q1aV7C9fQfc X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 12:41:15.5654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 827db31f-3784-4e90-d933-08deaf5a9776 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7346 Received-SPF: permerror client-ip=2a01:111:f403:c105::5; envelope-from=Sairaj.K@amd.com; helo=CH5PR02CU005.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1778506881677154100 Content-Type: text/plain; charset="utf-8" Current implemenation supports upto 64 bit IOVA and upto 52 bit PA. Modify related macros so that guest can see right size. Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde --- hw/i386/acpi-build.c | 2 +- hw/i386/amd_iommu.c | 2 +- hw/i386/amd_iommu.h | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 9446a9f862ca..e4ad01eec037 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1763,7 +1763,7 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linke= r, const char *oem_id, */ build_append_int_noprefix(table_data, (1UL << 0) | /* EFRSup */ - (40UL << 8), /* PASize */ + AMDVI_PA_SIZE_52, 4); /* reserved */ build_append_int_noprefix(table_data, 0, 8); diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 789e09d6f2bc..7c52f9ade6e6 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -2450,7 +2450,7 @@ static void amdvi_pci_realize(PCIDevice *pdev, Error = **errp) 0xff000000); pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, 0); pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, - AMDVI_MAX_PH_ADDR | AMDVI_MAX_GVA_ADDR | AMDVI_MAX_VA_ADDR); + AMDVI_PA_SIZE_52 | AMDVI_GVA_SIZE_48 | AMDVI_VA_SIZE_64); } =20 static void amdvi_sysbus_reset(DeviceState *dev) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 302ccca5121f..fe8f4a6cdc74 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -245,9 +245,9 @@ #define AMDVI_PAGE_SHIFT_4K 12 #define AMDVI_PAGE_MASK_4K GENMASK64(63, 12) =20 -#define AMDVI_MAX_GVA_ADDR (2UL << 5) -#define AMDVI_MAX_PH_ADDR (40UL << 8) -#define AMDVI_MAX_VA_ADDR (48UL << 15) +#define AMDVI_GVA_SIZE_48 (2UL << 5) +#define AMDVI_PA_SIZE_52 (52UL << 8) +#define AMDVI_VA_SIZE_64 (64UL << 15) =20 /* Completion Wait data size */ #define AMDVI_COMPLETION_DATA_SIZE 8 --=20 2.34.1 From nobody Sat May 30 17:44:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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Tsirkin" , Alejandro Jimenez , Ani Sinha , "Eduardo Habkost" , Igor Mammedov , "Marcel Apfelbaum" , Paolo Bonzini , Richard Henderson , Sairaj Kodilkar , CC: , Subject: [PATCH 3/8] amd_iommu: Return empty efr for stub call Date: Mon, 11 May 2026 18:09:32 +0530 Message-ID: <20260511123937.32743-4-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511123937.32743-1-sarunkod@amd.com> References: <20260511123937.32743-1-sarunkod@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B4:EE_|LV8PR12MB9269:EE_ X-MS-Office365-Filtering-Correlation-Id: a3724ad5-2624-4f5c-9503-08deaf5aa196 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700016|376014|82310400026|11063799003|56012099003|921020|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: DLWHDDx/YbIxq0t2SFlvbwBGim3MyOhTIMBvJ82MaWJcFo056ygzVkksOyaAZC5raoAtVAiobzhYpbiCol08G6MlpF1PSkr/HX9VcfSf91Jd0xS3HmtBVH6gxsGIc9QY+pfYvSMH8Iif06MHT/j2z5k6uQuOfL3wrb7GishrcgIRt05Exjbur4+mYwObLAGi1EC2GAupZtqzYMGZms4VBJdfvHssY4vaYe5XvXYcQjMDx5a9evF+IH9CJHa2ytCdzZV9Wn2ch8j8fgzpT+m4MN/1cDvTugDtQHtlxTF8E6xuuHZe9UrYQtU3ywIWX+4/GEXdie7PArj1KQ8m713pTo9JS9/aLUPLvPcBKHt3sa+ZSlqMu1gjV8JiaE48MvcKB1lKxhrLva5VANexho2HfsXIc3R9ykk8HD0+F3KK8scMiGnNME+znimSVqB4L+e3V8jcEMBb0rvfvHS1YW4GA6UookiY0rQlPDUX+c9AKjeWZUkcXonO5W3jHh7/AKf33fvjNIcSXUMJcrxR13EWLwvuzZZ+/9tPADHYBM8BXEMRUAStyoYrfaurl0ilNWuJreE6/359L6VBX3rmqIQJnOYpOvaF0QNeDZx4JCzg5CEf6C1nRQEtjcrBmUxtRPStachgY51azFa3rFAc/vQ01K7cCsvpy5O/bTNzo/MQrNPChLw2YAn6C9vaB6OiM9qZfVruQDfR0noLRCA9cq2M+029Rf65pB/wDMljH0meU4BndSgv8ICiy0gvJzaYAELIaEbIKtmp8mvb8lvVvnKZQw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(11063799003)(56012099003)(921020)(18002099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PB7aOaeabw69cBOrQqhl+kRpu/TSSoYsStNR7kFh8xub18pWmvN07b5p850bS3AwfdRTgcEdqNzkPZjrf6iKh3wwk4jmQ+q3TS/aaU8TlKb7Krbfw6ztwNCWAjLzId4mmOWkykyrR4fJyrocrVbZequ5vBQ3sJtpc1jTLru6+1eXNOACHWLVWwYTDruvgEfK+pPHNm8OY99sFEKfgmmNun2sDNQYEmhpoYaUBWkV/t68ri2UYHTeF04pRl/RsJIAtQScNJV1+rtV9T+jEZjmR9rEe259NmuenIxEgedGBx1EN9Q+283Cyay5/sQv044z8WJRVc3xSoPXZQRDr2BQwtVHM2rwH/nsM8QiQ6dADBhvh34BW475QCchQHROhvSK+6c3uJv/m27FdIVUCtX/QJtM+3LoScHDKT19wpBt1gdE3Ppd0OQDpm/mi8FKXYOW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 12:41:32.5452 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3724ad5-2624-4f5c-9503-08deaf5aa196 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9269 Received-SPF: permerror client-ip=2a01:111:f403:c10d::3; envelope-from=Sairaj.K@amd.com; helo=SN4PR0501CU005.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1778504390343154100 Content-Type: text/plain; charset="utf-8" The stub call should not return normal EFR as it is used as place holder when actual AMD IOMMU calls are not available. Hence return 0. Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde --- hw/i386/amd_iommu-stub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/amd_iommu-stub.c b/hw/i386/amd_iommu-stub.c index d62a3732e60f..fb36dee903ee 100644 --- a/hw/i386/amd_iommu-stub.c +++ b/hw/i386/amd_iommu-stub.c @@ -22,5 +22,5 @@ =20 uint64_t amdvi_extended_feature_register(AMDVIState *s) { - return AMDVI_DEFAULT_EXT_FEATURES; + return 0; } --=20 2.34.1 From nobody Sat May 30 17:44:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1778506724; cv=pass; d=zohomail.com; s=zohoarc; b=PP4/5bJAcc3e8jIwsAU/Pqrzh1Od2ZuyZ9ZUiwwVHtyJrbdheh64Qo1RPWGNjcVIAGuD0zkelVMniu2Sm/UbnFtJgtkby9HrPL2EyF5uPX4Sg1WuUem/VJVsIi4EVBAq1ccnqpdxvxdzw32dFcTX5CwbFsjhK1wV3eu0e94FWOc= ARC-Message-Signature: i=2; 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Tsirkin" , Alejandro Jimenez , Ani Sinha , "Eduardo Habkost" , Igor Mammedov , "Marcel Apfelbaum" , Paolo Bonzini , Richard Henderson , Sairaj Kodilkar , CC: , Subject: [PATCH 4/8] acpi_build: Use IOMMU pci device to build IOMMU device ID Date: Mon, 11 May 2026 18:09:33 +0530 Message-ID: <20260511123937.32743-5-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511123937.32743-1-sarunkod@amd.com> References: <20260511123937.32743-1-sarunkod@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AE:EE_|BL4PR12MB9480:EE_ X-MS-Office365-Filtering-Correlation-Id: 18869513-3a80-481d-3288-08deaf5aabbf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700016|82310400026|18002099003|11063799003|921020|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: R05PB1yDu5QyQ5eXCoDHPiFa6juNtNKNLFqOULOM0NYipeQp7z23ma+/zUhcynbGA0oyTXjFI/9OZUwGdGaLT6i9etMGs/3JZxRMswdfF5OQD71DXAG+oFGXt0ft4FKYTIiUahRnpp1gfX+hUU222G1flBHK7cI2cRor/z7l2hWCy3Aa0n5jobV9eOX4uHIh8b31rYbYm/phhaIIfwYJttHkE+gDpzf4i4ywtiJeWDv+kI2gJ5rG1KyZTWIvR5LAlB5zl3yz6MUeFzkZfe4wxMn4UMNDXP6gBVUmcA6Bnn4HR6ZEwF3B1UySCstdpha5dAWCRA0UsJTnVZS1catUys5NSStxlTpqoxJ74qc3VPG+XxfmnQ6qtHXsI8I+taiE4NXT/rcpWgjeKhgPRKPWyGXDrZI26N6pNAIVZZJBSshLEa16H1UmY1JFUwqvWmRRRuYs2tbBPzltSD2i7dVp8I75YM1J9OCajmxUxRw0Hld/TJfYLYBRXNihGS2YH0Q6qC0fjF3sfiLDfWYwcsM4lwG4GWWegIx6i+z4oLMZR1N3N0U4w4Uk0x35t6BmcVfqjXMEnElpiQrLPZwRR7QUpXE0TsZnQQMeao8Jt5kszqeNEgqmYDquVR33W7Jl7x6frzsI+UQWbX5haRigxdPOo0r9Fvr3eYF/0M+2wIMNYsnp4dv7CCzbAfCXklBLNzN6ygCHoxJDTfLLxhFWfpg+tvxZartNoQlHzluLjwgky37tDICcFMbHBVixuftZsvnw8WfXgrQTqGNr2nj0GOK45Q== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700016)(82310400026)(18002099003)(11063799003)(921020)(56012099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: X3U2EWP009itnsDDXYq4LJYSo5iuyGQ3nnBLs0urktRWW28VA1fcz3xk8LK4/H791kl+t7aE5daM2c01p34sYmxlEiG4/GWOA7a0cwug7V73i6Ns/yfpDQfVhtWUdFEpUyCXyl1LjOAaa/aEAkmCa0/X1T/IezWIw3txix/+MomBJkjXBQe7gamI1NLyur5pRHctHcNyldC6KY4tpZtiNhWPTPVJGOtmmQCkf5W1tI6wYUW38Frak+KRs2+eiwUFujPQxqbMWcGnuUHGc6A/ru0vzlESZ4uyKh5Qr/qnt3/Wjun1ShEb3L/k75S0Y5RAxqu8fjQgbuPe9mrOF9ikWEbpd4P8MXLpgqGFooXFxQu2XJCLUjHCfU7MGluCrKbT4TmXpyFAHdO/jOeJjX1MDK8GnqvPHQ/9OoDZy8w8T/FWPqBgcotC3/aPAUR43aZb X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 12:41:49.5895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18869513-3a80-481d-3288-08deaf5aabbf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9480 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=Sairaj.K@amd.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1778506726015158500 Content-Type: text/plain; charset="utf-8" Currently, build_amd_iommu() uses "addr" property to build the device ID for IOMMU device and advertise it throught IVRS. But this property does not enc= ode IOMMU bus. This will be a problem if IOMMU is attached to different bus. Hence use iommu pci device which provides bus, to build the IOMMU device ID. Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde --- hw/i386/acpi-build.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index e4ad01eec037..718e3f546b18 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1752,10 +1752,13 @@ build_amd_iommu(GArray *table_data, BIOSLinker *lin= ker, const char *oem_id, const char *oem_table_id) { AMDVIState *s =3D AMD_IOMMU_DEVICE(x86_iommu_get_default()); + PCIDevice *iommu_dev =3D &(s->pci->dev); GArray *ivhd_blob =3D g_array_new(false, true, 1); AcpiTable table =3D { .sig =3D "IVRS", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id }; uint64_t feature_report; + int iommu_bus =3D pci_bus_num(pci_get_bus(iommu_dev)); + uint16_t iommu_devid =3D PCI_BUILD_BDF(iommu_bus, iommu_dev->devfn); =20 acpi_table_begin(&table, table_data); /* IVinfo - IO virtualization information common to all @@ -1816,9 +1819,7 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linke= r, const char *oem_id, /* IVHD length */ build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); /* DeviceID */ - build_append_int_noprefix(table_data, - object_property_get_int(OBJECT(s->pci), "add= r", - &error_abort), 2); + build_append_int_noprefix(table_data, iommu_devid, 2); /* Capability offset */ build_append_int_noprefix(table_data, s->pci->capab_offset, 2); /* IOMMU base address */ @@ -1850,10 +1851,9 @@ build_amd_iommu(GArray *table_data, BIOSLinker *link= er, const char *oem_id, =20 /* IVHD length */ build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); + /* DeviceID */ - build_append_int_noprefix(table_data, - object_property_get_int(OBJECT(s->pci), "add= r", - &error_abort), 2); + build_append_int_noprefix(table_data, iommu_devid, 2); /* Capability offset */ build_append_int_noprefix(table_data, s->pci->capab_offset, 2); /* IOMMU base address */ --=20 2.34.1 From nobody Sat May 30 17:44:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Alejandro Jimenez , Ani Sinha , "Eduardo Habkost" , Igor Mammedov , "Marcel Apfelbaum" , Paolo Bonzini , Richard Henderson , Sairaj Kodilkar , CC: , Subject: [PATCH 5/8] acpi_build: Introduce necessary macros and structs for AMD IOMMU IVRS Date: Mon, 11 May 2026 18:09:34 +0530 Message-ID: <20260511123937.32743-6-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511123937.32743-1-sarunkod@amd.com> References: <20260511123937.32743-1-sarunkod@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|DM6PR12MB4155:EE_ X-MS-Office365-Filtering-Correlation-Id: 2454fcaa-3800-4fb2-9806-08deaf5ab915 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700016|376014|82310400026|11063799003|56012099003|921020|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: tp2xb1eOjFh1+ogVMLSqh7kLnQf7Dm5Ai9FmzD1FUX1DCI/rgkiVyH7i6q+tXNhZ642S+3OtTvcksukmShVoaAGIKcNDjkd3OLn05iRlwaVs9JR6DUJCsenRezJrfyXps8wj+VzB0grTLlmBEDmK5uCC+GnYbFxfpkyDVcwiDy7aOTOLkxiu07kQDiOrBNcu6LZVUPL4Q6X1S9KOyP9LavOds0Ac79kGkZGrPbTWMBv0o+0J37lIElw81TmjjlNz5vndinS7jfJN9Bkv9Dpb6wPzYCCECHNGZ4F7KkwI1BZGUrRFVjbxfNbpSBqmgIAXotZHK6No4LTXoM9hSMW3DOEYTMGlaIH/yvEphb6HYBCQgNnvuFfZiezIxOm/4Xsc7gSu2VhB3Vb1LtEbFBitRLB0lgaJDQRQNJWWsh3SxfrizdJfVaHbXcgZRy65o9fuxGH6XUcKdsL6lAlAHBh2LgDlDW2W81RvVneP/20EsCwYnexoa6exL6wAFSchlAcIwmXorOUiFr2cHbTCZSFrXeLZKex9a6Vl5L0kSRPC7LKpiV+k6Q43k0jTYlZU+kjsqp3VovHe4reds5gSKk+DPcch3HdYWkYUOJ7S/akVIZAjB0PICjq9TNIuf2/gcNY/xWLHqGXNG1FRaXwDDOL7NiaLqnGB3/xe6a6PDXXGuP/CcxV9J7jzf3aDMpQiE+eTiAtw34DOiNeuh7ThZ1d1kzLVzCMb3Zxjj6g6ojdELhwrkjghidznuOlk3kBCRDUxlyZ5N9f1Iw+0aVY7kbLhJQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(11063799003)(56012099003)(921020)(18002099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: R1PRwh9pGhUPJ9HbrU101zoBlu0HNKaNnKFas61End62X/tq10ZAtFsnpJzu4rQHh1PqRWsPV58rVveVsF8kg8JZmmgZjG37tYigVN2s+WSX8QlNtv7+z5ZdVmLr5z2aDLXWHOu/Skka1Vk5MfJlCPOKXFbbR+jRP2Mz78a5AoL2N5XgzTv1ohXqLYeSjsRZcNkA6hjNn5VIiybTlFWLNzzRV2BhMqm3LyNMpF/7Tkr/UpQKD9KqqhM7ay9uajSbY4ub2lX7zOHZpysH8wamo2O8YtiT0/bChQNYKa0dLrwRJLcxR6sS4Wk6DWs4o4qz/KOyW7Wrp14lV8B91Id3+HVLOVmO8Qbrepa2TAA0iC0YSP7xqL+16rdeM2JA2Jaq/+J2tbzlrZ9D9MMAdAL07whnsM+uX7ZRI9Tbmu+7RK7xH1Y5rU8ALMsXbL4K+sPb X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 12:42:11.9651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2454fcaa-3800-4fb2-9806-08deaf5ab915 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4155 Received-SPF: permerror client-ip=2a01:111:f403:c111::9; envelope-from=Sairaj.K@amd.com; helo=DM5PR21CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1778507034717154100 Content-Type: text/plain; charset="utf-8" Introduce necessary macros, along with packed structs which represents the AMD IVRS data structure, to hold the necessary information. This will improve readability of the current code. Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde --- hw/i386/acpi-build.h | 92 ++++++++++++++++++++++++++++++++++++++++++++ hw/i386/amd_iommu.h | 6 +++ 2 files changed, 98 insertions(+) diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h index 8ba3c33e4831..9fd60a186db1 100644 --- a/hw/i386/acpi-build.h +++ b/hw/i386/acpi-build.h @@ -2,10 +2,102 @@ #ifndef HW_I386_ACPI_BUILD_H #define HW_I386_ACPI_BUILD_H #include "hw/acpi/acpi-defs.h" +#include "qemu/bitops.h" =20 extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; =20 void acpi_setup(void); Object *acpi_get_i386_pci_host(void); =20 +#define AMD_IVINFO_EFR_SUP BIT(0) + +#define AMD_IVHD_FLAG_HT_TUN_EN BIT(0) +#define AMD_IVHD_FLAG_IOTLB_SUP BIT(4) +#define AMD_IVHD_FLAG_PREF_SUP BIT(6) +#define AMD_IVHD_FLAG_PPR_SUP BIT(7) + +#define AMD_IVHD_FEATURE_REPORT_XT_SUP_SHIFT (0) +#define AMD_IVHD_FEATURE_REPORT_GT_SUP_SHIFT (2) +#define AMD_IVHD_FEATURE_REPORT_GLX_SUP_SHIFT (3) +#define AMD_IVHD_FEATURE_REPORT_GA_SUP_SHIFT (6) +#define AMD_IVHD_FEATURE_REPORT_GATS_SHIFT (28) +#define AMD_IVHD_FEATURE_REPORT_HATS_SHIFT (30) + +#define AMD_IVHD_ATTRIBUTES_HATDIS_SHIFT (0) + +#define AMD_IVHD_DEVICE_ENTRY_TYPE_RESERVED (0) +#define AMD_IVHD_DEVICE_ENTRY_TYPE_ALL (1) +#define AMD_IVHD_DEVICE_ENTRY_TYPE_SELECT (2) +#define AMD_IVHD_DEVICE_ENTRY_TYPE_START_RANGE (3) +#define AMD_IVHD_DEVICE_ENTRY_TYPE_END_RANGE (4) +#define AMD_IVHD_DEVICE_ENTRY_TYPE_ALIAS_START_RANGE (0x43) +#define AMD_IVHD_DEVICE_ENTRY_TYPE_SPECIAL_DEVICE (0x48) + +#define IVHD_VARIETY_IOAPIC (1) +#define IVHD_VARIETY_HPET (2) + +/* + * Vendor(AMD) specific fields in the IVRS header + * Excludes fields in ACPI table header + */ +typedef +struct AmdIvrsVendorHdr { + uint32_t ivinfo; + uint64_t reserved; +} __attribute__((packed)) AmdIvrsVendorHdr; + +/* IVHD type 10h */ +typedef +struct AmdIvhdHdr10 { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t devid; + uint16_t capab_offset; + uint64_t base_addr; + uint16_t pci_seg; + uint16_t iommu_info; + uint32_t iommu_feature_report; +} __attribute__((packed)) AmdIvhdHdr10; + +/* IVHD type 11h */ +typedef +struct AmdIvhdHdr11 { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t devid; + uint16_t capab_offset; + uint64_t base_addr; + uint16_t pci_seg; + uint16_t iommu_info; + uint32_t iommu_attributes; + uint64_t efr; + uint64_t efr2; +} __attribute__((packed)) AmdIvhdHdr11; + +typedef +struct AmdIvhdDeviceEntry { + uint8_t type; + uint16_t devid; + uint8_t dte_setting; +} __attribute__((packed)) AmdIvhdDeviceEntry; + +typedef +struct AmdIvhdDeviceEntryExt { + uint8_t type; + uint16_t devid_a; + uint8_t dte_setting; + union { + struct { + uint8_t handle; + uint16_t devid_b; + uint8_t variety; + } __attribute__((packed)); + struct { + uint32_t ext_dte_setting; + } __attribute__((packed)); + }; +} __attribute__((packed)) AmdIvhdDeviceEntryExt; + #endif diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index fe8f4a6cdc74..d97ddbd612dc 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -175,9 +175,15 @@ #define AMDVI_DTE_QUAD3_RESERVED (GENMASK64(14, 0) | GENMASK64(53, = 48)) =20 /* AMDVI paging mode */ +#define AMDVI_GATS_MODE_SHIFT (12) +#define AMDVI_GATS_MODE_MASK (3ULL << 12) #define AMDVI_GATS_MODE (2ULL << 12) +#define AMDVI_HATS_MODE_SHIFT (10) +#define AMDVI_HATS_MODE_MASK (3ULL << 10) #define AMDVI_HATS_MODE (2ULL << 10) #define AMDVI_HATS_MODE_RESERVED (3ULL << 10) +#define AMDVI_GLX_SUP_SHIFT (14) +#define AMDVI_GLX_SUP_MASK (3ULL << 14) =20 /* Page Table format */ =20 --=20 2.34.1 From nobody Sat May 30 17:44:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tsirkin" , Alejandro Jimenez , Ani Sinha , "Eduardo Habkost" , Igor Mammedov , "Marcel Apfelbaum" , Paolo Bonzini , Richard Henderson , Sairaj Kodilkar , CC: , Subject: [PATCH 6/8] acpi_build: Build IVRS feature report using extended feature register Date: Mon, 11 May 2026 18:09:35 +0530 Message-ID: <20260511123937.32743-7-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260511123937.32743-1-sarunkod@amd.com> References: <20260511123937.32743-1-sarunkod@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231C:EE_|LV8PR12MB9716:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a9bd0ed-3bbc-4f37-92ca-08deaf5ac384 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|376014|82310400026|22082099003|18002099003|921020|56012099003|11063799003; X-Microsoft-Antispam-Message-Info: EMbrvrToEyQTpkn6N5ho4Q7mK2xBMu6TI0fgBCQESrHzNSZalngJQG2aGLDcoOuiEDjjUnjnO3uRmeK3Uyk77EHFJIlH+S05Ly6GtdupQzaGwtRoyzP3VfnT5MiXpPuo+AAWQ48gjtepkKYMk7W+fCsdxzhuSvDSYv4g1rgSbZDg1jWIXuVKXiewlVuTW5DMC0pEvV8dX7wns4Rsd4cO6wQJi6DkYzeb2rY+k2Tn2b7lb+tidvc1xwsRc0hXDDKeZshXUAhJi3pBqOsVXS+L7bPByrhWlUBK8Rc5RtnaTtCOzkiz//Q0eqdBpxl4X/6VsIJDzLW/CabG9SdeCcQk0t0Yml0sH2rDZu7m48ExUe5Ky/TN0WFKwV9gtHg3LdHfRr4GYRMZjB+wePKTnarDrGxKvt/ZLDrBsDF7NrT67I2fGUSzamZ7IkpTrf2b9CJAFbtLu3JUtcTt15EaUbjB94wfPw5qVAY+i3z3W33JJLDXbWSijjK6DhvQ42sHIpXGf5C1Y0pJlTeJ/cIz90rG+6VGSTPV0t6OwPVaxnAl07uJI5WTtNMyj7WcY+VYNbltNOSumWd1LG8XmtIILzP8eACtQcZFffl2jtU0rTRUAsH+q+M7bTHwBf6F7FmdSZWo0b5ZVAt7z5flnXlkDxL3UDOzw9TYM75ban65RIMOnG0LSs17x1EQxymFRrv5wr4PXxyUiG+HLGeoOQm2rdiZMY7N4aeMrApEaYv1CvUkxQOsOFhs0i9O/NXtJ2zm0dl29NmJjsY84FzDdhA+nB2oWQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700016)(1800799024)(376014)(82310400026)(22082099003)(18002099003)(921020)(56012099003)(11063799003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Th0M5yNFbNbajQx4uniErlV3BU/mZ2hSEQm4ZSAAwQtcNOd+GNEzoym7DUL8U51t8lfydHELlxIRcAgQ/GZRwOice5naRXYCFtiFLsJkiQRfVlSQZydu8W33akAtOeKsyFCW49ndZe6iXLynCtkTWXpgY8dj36LrLlO+Opo+cn092Q5y1gbo2eChl9DExVLClBcUBemxTR9HzgxEA6dxEaqtSYfpA1NPc1GybetNkmy2PtJcpe4uos9hHZHxs+LSMvuJKMBN57J6iAgvCqbS4OYIVYRh97OpjOl9fOqtwXCNi9rnnO70PQusAxlaSb3ZR+g2kInPjuuTh7916mcDHtGJuoI/OB+YTXwoQy08V1SEXBBMp8mkhamcE+G6aJvfOthMVinOrEKvZbt/6iUOFcI/5sMXo9ufMTEhT30aI83ww1x/2BXkzOk6OJi/eTB/ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2026 12:42:29.4005 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a9bd0ed-3bbc-4f37-92ca-08deaf5ac384 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9716 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=Sairaj.K@amd.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1778507109957154100 Content-Type: text/plain; charset="utf-8" Currently IVRS feature report values are hardcoded, this is difficult to maintain as any updates to extended feature must be synced. Along with it current feature report does not have GATS and HATS set. Hence use the extended feature registers to build the IVRS feature report. Signed-off-by: Sairaj Kodilkar --- hw/i386/acpi-build.c | 38 +++++++++++++++++++++++++++++++------- hw/i386/acpi-build.h | 1 - 2 files changed, 31 insertions(+), 8 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 718e3f546b18..82208e06e155 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1747,6 +1747,36 @@ ivrs_host_bridges(Object *obj, void *opaque) return 0; } =20 +/* + * IVHD type 0x10 reports features using Feature Reporting field, which has + * different format than extended feature register (EFR) in the IOMMU MMIO + * space. + * + * Convert the EFR format to feature reporting format. + */ +static uint32_t +get_amd_ivhd_feature_report(AMDVIState *s) +{ + uint64_t feature =3D amdvi_extended_feature_register(s); + uint32_t is_gt =3D !!(feature & AMDVI_FEATURE_GT); + uint32_t is_ga =3D !!(feature & AMDVI_FEATURE_GA); + uint64_t glx_sup =3D (feature & AMDVI_GLX_SUP_MASK) >> AMDVI_GLX_SUP_S= HIFT; + uint64_t hats_mode =3D (feature & AMDVI_HATS_MODE_MASK) >> + AMDVI_HATS_MODE_SHIFT; + uint64_t gats_mode =3D (feature & AMDVI_GATS_MODE_MASK) >> + AMDVI_GATS_MODE_SHIFT; + uint32_t feature_report; + + feature_report =3D s->xtsup << AMD_IVHD_FEATURE_REPORT_XT_SUP_SHIFT | + is_gt << AMD_IVHD_FEATURE_REPORT_GT_SUP_SHIFT | + glx_sup << AMD_IVHD_FEATURE_REPORT_GLX_SUP_SHIFT | + is_ga << AMD_IVHD_FEATURE_REPORT_GA_SUP_SHIFT | + hats_mode << AMD_IVHD_FEATURE_REPORT_HATS_SHIFT | + gats_mode << AMD_IVHD_FEATURE_REPORT_GATS_SHIFT; + + return feature_report; +} + static void build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id, const char *oem_table_id) @@ -1829,13 +1859,7 @@ build_amd_iommu(GArray *table_data, BIOSLinker *link= er, const char *oem_id, /* IOMMU info */ build_append_int_noprefix(table_data, 0, 2); /* IOMMU Feature Reporting */ - feature_report =3D (48UL << 30) | /* HATS */ - (48UL << 28) | /* GATS */ - (1UL << 2) | /* GTSup */ - (1UL << 6); /* GASup */ - if (s->xtsup) { - feature_report |=3D (1UL << 0); /* XTSup */ - } + feature_report =3D get_amd_ivhd_feature_report(s); build_append_int_noprefix(table_data, feature_report, 4); =20 /* IVHD entries as found above */ diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h index 9fd60a186db1..d81b7890e6e2 100644 --- a/hw/i386/acpi-build.h +++ b/hw/i386/acpi-build.h @@ -1,4 +1,3 @@ - #ifndef HW_I386_ACPI_BUILD_H #define HW_I386_ACPI_BUILD_H #include "hw/acpi/acpi-defs.h" --=20 2.34.1 From nobody Sat May 30 17:44:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1778505067; cv=pass; d=zohomail.com; s=zohoarc; b=S35Qq56lGEboCx+4e3MroNYmfNIpacP8nz583wyLAX9yNRlMSqJnPfUqQZ84Etgnnx24iR/M4ydxdyUQwoEUX7SeMrvNW1aXL1yVc1lmlLTrSqlmk+2kZ7LIPpHDjq9eYtwcVOHgRl+PVr9pqgD+dd5YCFvt/qdvBI6cO1Yxcco= ARC-Message-Signature: i=2; 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envelope-from=Sairaj.K@amd.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1778505069662158500 Content-Type: text/plain; charset="utf-8" Use structs and macros to improve the readability and maintainability of the the code.=20 Signed-off-by: Sairaj Kodilkar --- hw/i386/acpi-build.c | 149 +++++++++++++++++-------------------------- 1 file changed, 59 insertions(+), 90 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 82208e06e155..e18c9be801a2 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1663,11 +1663,13 @@ static void insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque) { GArray *table_data =3D opaque; - uint32_t entry; + AmdIvhdDeviceEntry entry =3D {}; =20 /* "Select" IVHD entry, type 0x2 */ - entry =3D PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2; - build_append_int_noprefix(table_data, entry, 4); + entry.type =3D AMD_IVHD_DEVICE_ENTRY_TYPE_SELECT; + entry.devid =3D PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); + + g_array_append_vals(table_data, &entry, sizeof(entry)); =20 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { PCIBus *sec_bus =3D pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); @@ -1691,11 +1693,14 @@ insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaq= ue) */ if (sec =3D=3D sub) { /* leaf bus */ /* "Start of Range" IVHD entry, type 0x3 */ - entry =3D PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3; - build_append_int_noprefix(table_data, entry, 4); + entry.type =3D AMD_IVHD_DEVICE_ENTRY_TYPE_START_RANGE; + entry.devid =3D PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); + g_array_append_vals(table_data, &entry, sizeof(entry)); + /* "End of Range" IVHD entry, type 0x4 */ - entry =3D PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; - build_append_int_noprefix(table_data, entry, 4); + entry.type =3D AMD_IVHD_DEVICE_ENTRY_TYPE_END_RANGE; + entry.devid =3D PCI_BUILD_BDF(sub, PCI_DEVFN_MAX - 1); + g_array_append_vals(table_data, &entry, sizeof(entry)); } else { pci_for_each_device(sec_bus, sec, insert_ivhd, table_data); } @@ -1708,24 +1713,26 @@ insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaq= ue) * express bridges, just as in pci_device_iommu_address_space(= ). * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec. */ - uint16_t dev_id_a, dev_id_b; + AmdIvhdDeviceEntryExt entry_ext =3D {}; =20 - dev_id_a =3D PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); + entry_ext.type =3D AMD_IVHD_DEVICE_ENTRY_TYPE_ALIAS_START_RANG= E; + entry_ext.devid_a =3D PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)); =20 if (pci_is_express(dev) && pcie_cap_get_type(dev) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE) { - dev_id_b =3D dev_id_a; + entry_ext.devid_b =3D entry_ext.devid_a; } else { - dev_id_b =3D PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn); + entry_ext.devid_b =3D PCI_BUILD_BDF(pci_bus_num(bus), + dev->devfn); } =20 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */ - build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4); - build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4); + g_array_append_vals(table_data, &entry_ext, sizeof(entry_ext)); =20 /* "End of Range" IVHD entry, type 0x4 */ - entry =3D PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4; - build_append_int_noprefix(table_data, entry, 4); + entry.type =3D AMD_IVHD_DEVICE_ENTRY_TYPE_END_RANGE; + entry.devid =3D PCI_BUILD_BDF(sub, PCI_DEVFN_MAX - 1); + g_array_append_vals(table_data, &entry, sizeof(entry)); } } } @@ -1786,20 +1793,20 @@ build_amd_iommu(GArray *table_data, BIOSLinker *lin= ker, const char *oem_id, GArray *ivhd_blob =3D g_array_new(false, true, 1); AcpiTable table =3D { .sig =3D "IVRS", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id }; - uint64_t feature_report; int iommu_bus =3D pci_bus_num(pci_get_bus(iommu_dev)); uint16_t iommu_devid =3D PCI_BUILD_BDF(iommu_bus, iommu_dev->devfn); + AmdIvrsVendorHdr ivrs_hdr =3D {}; + AmdIvhdHdr10 ivhd10 =3D {}; + AmdIvhdHdr11 ivhd11 =3D {}; =20 acpi_table_begin(&table, table_data); /* IVinfo - IO virtualization information common to all * IOMMU units in a system */ - build_append_int_noprefix(table_data, - (1UL << 0) | /* EFRSup */ - AMDVI_PA_SIZE_52, - 4); - /* reserved */ - build_append_int_noprefix(table_data, 0, 8); + ivrs_hdr.ivinfo =3D AMD_IVINFO_EFR_SUP | AMDVI_GVA_SIZE_48 | + AMDVI_PA_SIZE_52 | AMDVI_VA_SIZE_64; + + g_array_append_vals(table_data, &ivrs_hdr, sizeof(ivrs_hdr)); =20 /* * A PCI bus walk, for each PCI host bridge, is necessary to create a @@ -1817,7 +1824,8 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linke= r, const char *oem_id, * These are 4-byte device entries currently reporting the range= of * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte) */ - build_append_int_noprefix(ivhd_blob, 0x0000001, 4); + AmdIvhdDeviceEntry entry =3D { .type =3D AMD_IVHD_DEVICE_ENTRY_TYP= E_ALL }; + g_array_append_vals(ivhd_blob, &entry, sizeof(entry)); } =20 /* @@ -1829,76 +1837,37 @@ build_amd_iommu(GArray *table_data, BIOSLinker *lin= ker, const char *oem_id, * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059' */ if (x86_iommu_ir_supported(x86_iommu_get_default())) { - build_append_int_noprefix(ivhd_blob, - (0x1ull << 56) | /* type IOAPIC= */ - (IOAPIC_SB_DEVID << 40) | /* IOAPIC devi= d */ - 0x48, /* special dev= ice */ - 8); - } - - /* IVHD definition - type 10h */ - build_append_int_noprefix(table_data, 0x10, 1); - /* virtualization flags */ - build_append_int_noprefix(table_data, - (1UL << 0) | /* HtTunEn */ - (1UL << 4) | /* iotblSup */ - (1UL << 6) | /* PrefSup */ - (1UL << 7), /* PPRSup */ - 1); - - /* IVHD length */ - build_append_int_noprefix(table_data, ivhd_blob->len + 24, 2); - /* DeviceID */ - build_append_int_noprefix(table_data, iommu_devid, 2); - /* Capability offset */ - build_append_int_noprefix(table_data, s->pci->capab_offset, 2); - /* IOMMU base address */ - build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); - /* PCI Segment Group */ - build_append_int_noprefix(table_data, 0, 2); - /* IOMMU info */ - build_append_int_noprefix(table_data, 0, 2); - /* IOMMU Feature Reporting */ - feature_report =3D get_amd_ivhd_feature_report(s); - build_append_int_noprefix(table_data, feature_report, 4); - + AmdIvhdDeviceEntryExt entry_ext =3D { + .type =3D AMD_IVHD_DEVICE_ENTRY_TYPE_SPECIAL_DEVICE, + .devid_b =3D IOAPIC_SB_DEVID, + .variety =3D IVHD_VARIETY_IOAPIC + }; + + g_array_append_vals(ivhd_blob, &entry_ext, sizeof(entry_ext)); + } + + ivhd10.type =3D 0x10; + ivhd10.flags =3D AMD_IVHD_FLAG_HT_TUN_EN | AMD_IVHD_FLAG_IOTLB_SUP | + AMD_IVHD_FLAG_PREF_SUP | AMD_IVHD_FLAG_PPR_SUP; + ivhd10.length =3D ivhd_blob->len + sizeof(ivhd10); + ivhd10.devid =3D iommu_devid; + ivhd10.capab_offset =3D s->pci->capab_offset; + ivhd10.base_addr =3D s->mr_mmio.addr; + ivhd10.iommu_feature_report =3D get_amd_ivhd_feature_report(s); + g_array_append_vals(table_data, &ivhd10, sizeof(ivhd10)); /* IVHD entries as found above */ g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); =20 - /* IVHD definition - type 11h */ - build_append_int_noprefix(table_data, 0x11, 1); - /* virtualization flags */ - build_append_int_noprefix(table_data, - (1UL << 0) | /* HtTunEn */ - (1UL << 4), /* iotblSup */ - 1); - - /* IVHD length */ - build_append_int_noprefix(table_data, ivhd_blob->len + 40, 2); - - /* DeviceID */ - build_append_int_noprefix(table_data, iommu_devid, 2); - /* Capability offset */ - build_append_int_noprefix(table_data, s->pci->capab_offset, 2); - /* IOMMU base address */ - build_append_int_noprefix(table_data, s->mr_mmio.addr, 8); - /* PCI Segment Group */ - build_append_int_noprefix(table_data, 0, 2); - /* IOMMU info */ - build_append_int_noprefix(table_data, 0, 2); - /* IOMMU Attributes */ - if (!s->iommu.dma_translation) { - build_append_int_noprefix(table_data, (1UL << 0) /* HATDis */, 4); - } else { - build_append_int_noprefix(table_data, 0, 4); - } - /* EFR Register Image */ - build_append_int_noprefix(table_data, - amdvi_extended_feature_register(s), - 8); - /* EFR Register Image 2 */ - build_append_int_noprefix(table_data, 0, 8); - + ivhd11.type =3D 0x11; + ivhd11.flags =3D AMD_IVHD_FLAG_HT_TUN_EN | AMD_IVHD_FLAG_IOTLB_SUP; + ivhd11.length =3D ivhd_blob->len + sizeof(ivhd11); + ivhd11.devid =3D iommu_devid; + ivhd11.capab_offset =3D s->pci->capab_offset; + ivhd11.base_addr =3D s->mr_mmio.addr; + ivhd11.iommu_attributes =3D !s->iommu.dma_translation << + AMD_IVHD_ATTRIBUTES_HATDIS_SHIFT; + ivhd11.efr =3D amdvi_extended_feature_register(s); + g_array_append_vals(table_data, &ivhd11, sizeof(ivhd11)); /* IVHD entries as found above */ g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len); =20 --=20 2.34.1 From nobody Sat May 30 17:44:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; 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envelope-from=Sairaj.K@amd.com; helo=SJ2PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1778505792111154100 Content-Type: text/plain; charset="utf-8" Differences between disassembled ASL files for IVRS: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/x86/q35/IVRS.ivrs, Mon May 11 11:21:47 2= 026 + * Disassembly of /tmp/aml-NGQ9O3, Mon May 11 11:21:47 2026 * * ACPI Data Table [IVRS] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "IVRS" [I/O Virtualizati= on Reporting Structure] [004h 0004 4] Table Length : 000000B0 [008h 0008 1] Revision : 01 -[009h 0009 1] Checksum : 74 +[009h 0009 1] Checksum : 68 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 -[024h 0036 4] Virtualization Info : 00002801 +[024h 0036 4] Virtualization Info : 00203441 [028h 0040 8] Reserved : 0000000000000000 [030h 0048 1] Subtable Type : 10 [Hardware Definition Blo= ck] [031h 0049 1] Flags : D1 [032h 0050 2] Length : 0038 [034h 0052 2] DeviceId : 0010 [036h 0054 2] Capability Offset : 0040 [038h 0056 8] Base Address : 00000000FED80000 [040h 0064 2] PCI Segment Group : 0000 [042h 0066 2] Virtualization Info : 0000 -[044h 0068 4] Feature Reporting : 00000044 +[044h 0068 4] Feature Reporting : A0000044 [048h 0072 1] Entry Type : 02 [049h 0073 2] Device ID : 0000 [04Bh 0075 1] Data Setting : 00 [04Ch 0076 1] Entry Type : 02 [04Dh 0077 2] Device ID : 0008 [04Fh 0079 1] Data Setting : 00 [050h 0080 1] Entry Type : 02 [051h 0081 2] Device ID : 0010 [053h 0083 1] Data Setting : 00 [054h 0084 1] Entry Type : 02 [055h 0085 2] Device ID : 00F8 [057h 0087 1] Data Setting : 00 @@ -98,27 +98,27 @@ [0A1h 0161 2] Device ID : 00FA [0A3h 0163 1] Data Setting : 00 [0A4h 0164 1] Entry Type : 02 [0A5h 0165 2] Device ID : 00FB [0A7h 0167 1] Data Setting : 00 [0A8h 0168 1] Entry Type : 48 [0A9h 0169 2] Device ID : 0000 [0ABh 0171 1] Data Setting : 00 [0ACh 0172 1] Handle : 00 [0ADh 0173 2] Source Used Device ID : 00A0 [0AFh 0175 1] Variety : 01 Signed-off-by: Sairaj Kodilkar --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 33e998165591..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -tests/data/acpi/x86/q35/IVRS.ivrs --=20 2.34.1