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Fri, 08 May 2026 10:20:15 -0700 (PDT) From: Jim MacArthur Date: Fri, 08 May 2026 18:20:12 +0100 Subject: [PATCH 1/3] boot.S: Allocate minimal space for granule protection tables MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-jmac-gpctest-v1-1-e57e42c87e1e@linaro.org> References: <20260508-jmac-gpctest-v1-0-e57e42c87e1e@linaro.org> In-Reply-To: <20260508-jmac-gpctest-v1-0-e57e42c87e1e@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1778260896313158500 Allocates the minimum required space for granule protection tables, 8 bytes for stage 0 and 512KB for stage 1. Signed-off-by: Jim MacArthur --- tests/tcg/aarch64/system/boot.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boo= t.S index 8bfa4e4efc..ffcb9a2140 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -404,6 +404,16 @@ ttb_stage2: .space 4096, 0 =20 .align 12 + .global realms_gpt0 + /* GPT stage 0 table */ +realms_gpt0: + .space 4096, 0 + .align 17 + .global realms_gpt1 + /* GPT stage 1 table, initialised to all 0xFF (full access) */ +realms_gpt1: + .space 524288, 0xFF + .align 12 system_stack: .space 4096, 0 system_stack_end: --=20 2.43.0 From nobody Mon May 25 20:32:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Fri, 08 May 2026 10:20:16 -0700 (PDT) From: Jim MacArthur Date: Fri, 08 May 2026 18:20:13 +0100 Subject: [PATCH 2/3] altvec.S: Alternative vector table for aarch64 testing MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-jmac-gpctest-v1-2-e57e42c87e1e@linaro.org> References: <20260508-jmac-gpctest-v1-0-e57e42c87e1e@linaro.org> In-Reply-To: <20260508-jmac-gpctest-v1-0-e57e42c87e1e@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1778260858766154100 Sets up a potential replacement vector table which will record and ignore certain types of exception. Indicative values are recorded in 'exception_log'. Most exception types are handled in the same way as the table in boot.S. Signed-off-by: Jim MacArthur --- tests/tcg/aarch64/Makefile.softmmu-target | 2 +- tests/tcg/aarch64/system/altvec.S | 129 ++++++++++++++++++++++++++= ++++ 2 files changed, 130 insertions(+), 1 deletion(-) diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index f7a7d2b800..60c65f4969 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -8,7 +8,7 @@ AARCH64_SYSTEM_SRC=3D$(AARCH64_SRC)/system VPATH+=3D$(AARCH64_SYSTEM_SRC) =20 # These objects provide the basic boot code and helper functions for all t= ests -CRT_OBJS=3Dboot.o +CRT_OBJS=3Dboot.o altvec.o =20 AARCH64_TEST_C_SRCS=3D$(wildcard $(AARCH64_SYSTEM_SRC)/*.c) AARCH64_TEST_S_SRCS=3D$(AARCH64_SYSTEM_SRC)/mte.S diff --git a/tests/tcg/aarch64/system/altvec.S b/tests/tcg/aarch64/system/a= ltvec.S new file mode 100644 index 0000000000..079846b639 --- /dev/null +++ b/tests/tcg/aarch64/system/altvec.S @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Alternative AArch64 vector table. Can replace the vector table + * in boot.S and record & ignore some exceptions in exception_log. + * Maintains the semihosting error print and exit for most + * exceptions. + * + * Copyright Linaro Ltd 2026 + * + */ + +#define semihosting_call hlt 0xf000 +#define SYS_WRITE0 0x04 /* string to debug channel */ +#define SYS_EXIT 0x18 + .align 12 + + .macro ventry label + .align 7 + b \label + .endm + + .global alt_vector_table +alt_vector_table: + /* Current EL with SP0. */ + ventry curr_sp0_sync /* Synchronous */ + ventry curr_sp0_irq /* Irq/vIRQ */ + ventry curr_sp0_fiq /* Fiq/vFIQ */ + ventry curr_sp0_serror /* SError/VSError */ + + /* Current EL with SPx. */ + ventry curr_spx_sync /* Synchronous */ + ventry curr_spx_irq /* IRQ/vIRQ */ + ventry curr_spx_fiq /* FIQ/vFIQ */ + ventry curr_spx_serror /* SError/VSError */ + + /* Lower EL using AArch64. */ + ventry lower_a64_sync /* Synchronous */ + ventry lower_a64_irq /* IRQ/vIRQ */ + ventry lower_a64_fiq /* FIQ/vFIQ */ + ventry lower_a64_serror /* SError/VSError */ + + /* Lower EL using AArch32. */ + ventry lower_a32_sync /* Synchronous */ + ventry lower_a32_irq /* IRQ/vIRQ */ + ventry lower_a32_fiq /* FIQ/vFIQ */ + ventry lower_a32_serror /* SError/VSError */ + + .text + .align 4 + +curr_spx_sync: + sub sp, sp, #16 + stp x0, x1, [sp, #0] + mrs x0, ESR_EL3 + lsr x0, x0, #26 + and x0, x0, #0x3f + cmp x0, #37 + beq data_fault + cmp x0, #30 + beq gpc_fault + b generic_exception + +data_fault: + mrs x0, FAR_EL3 + adrp x1, exception_log + str x0, [x1] + ldr x0, =3D0x1001 + str x0, [x1, #8] + b skip_return +gpc_fault: + mrs x0, FAR_EL3 + adrp x1, exception_log + str x0, [x1] + ldr x0, =3D0x1002 + str x0, [x1, #8] + /* Fall through */ +skip_return: + mrs x0, ELR_EL3 + add x0, x0, #4 /* Skip faulting instruction */ + msr ELR_EL3, x0 + ldp x0, x1, [sp, #0] + add sp, sp, #16 + eret +curr_sp0_sync: +curr_sp0_irq: +curr_sp0_fiq: +curr_sp0_serror: +curr_spx_irq: +curr_spx_fiq: +curr_spx_serror: +lower_a64_sync: +lower_a64_irq: +lower_a64_fiq: +lower_a64_serror: +lower_a32_sync: +lower_a32_irq: +lower_a32_fiq: +lower_a32_serror: +generic_exception: + adr x1, .unexp_excp +exit_msg: + mov x0, SYS_WRITE0 + semihosting_call + mov x0, 1 /* EXIT_FAILURE */ + bl _exit + /* never returns */ +print_debug_msg: + mov x0, SYS_WRITE0 + semihosting_call + ret +_exit: + mov x1, x0 + ldr x0, =3D0x20026 /* ADP_Stopped_ApplicationExit */ + stp x0, x1, [sp, #-16]! + mov x1, sp + mov x0, SYS_EXIT + semihosting_call + + + .section .rodata +.unexp_excp: + .string "Unexpected exception (via alternative handler).\n" + + .data + .align 8 + .global exception_log +exception_log: + .space 128, 0 + --=20 2.43.0 From nobody Mon May 25 20:32:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 08 May 2026 10:20:16 -0700 (PDT) From: Jim MacArthur Date: Fri, 08 May 2026 18:20:14 +0100 Subject: [PATCH 3/3] gpc-test.c: Basic test for granule protection check. MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260508-jmac-gpctest-v1-3-e57e42c87e1e@linaro.org> References: <20260508-jmac-gpctest-v1-0-e57e42c87e1e@linaro.org> In-Reply-To: <20260508-jmac-gpctest-v1-0-e57e42c87e1e@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Jim MacArthur X-Mailer: b4 0.13.0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1778260860381154100 * Sets up granule protection tablers * Installs the alternative vector table * Enables GPC * Performs memory accesses in the protected region to check for allowed and disallowed reads. Signed-off-by: Jim MacArthur --- tests/tcg/aarch64/Makefile.softmmu-target | 5 ++ tests/tcg/aarch64/system/gpc-test.c | 125 ++++++++++++++++++++++++++= ++++ 2 files changed, 130 insertions(+) diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index 60c65f4969..90630e95dc 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -71,6 +71,11 @@ QEMU_EL2_MACHINE=3D-machine virt,virtualization=3Don,gic= -version=3D2 -cpu cortex-a57 - QEMU_EL2_BASE_ARGS=3D-semihosting-config enable=3Don,target=3Dnative,chard= ev=3Doutput,arg=3D"2" run-vtimer: QEMU_OPTS=3D$(QEMU_EL2_MACHINE) $(QEMU_EL2_BASE_ARGS) -kernel =20 +# gpc-test needs EL3 and RME +QEMU_EL3_MACHINE=3D-machine virt,virtualization=3Don,secure=3Don,gic-versi= on=3D3 -cpu max,x-rme=3Don +QEMU_EL3_BASE_ARGS=3D-semihosting-config enable=3Don,target=3Dnative,chard= ev=3Doutput,arg=3D"3" +run-gpc-test: QEMU_OPTS=3D$(QEMU_EL3_MACHINE) $(QEMU_EL3_BASE_ARGS) -kernel + # Simple Record/Replay Test .PHONY: memory-record run-memory-record: memory-record memory diff --git a/tests/tcg/aarch64/system/gpc-test.c b/tests/tcg/aarch64/system= /gpc-test.c new file mode 100644 index 0000000000..fae754a56c --- /dev/null +++ b/tests/tcg/aarch64/system/gpc-test.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * + * + * Copyright (c) 2026 Linaro Ltd + * + */ + +#include +#include +#include + +#define ID_AA64PFR0_EL1 "S3_0_C0_C4_0" + +#define GPCCR_EL3 "S3_6_C2_C1_6" +#define GPTBR_EL3 "S3_6_C2_C1_4" + +#define VBAR_EL3 "S3_6_C12_C0_0" + +#define get_sys_reg(register_name, dest) \ + asm("mrs %[reg], " register_name "\n\t" : [reg] "=3Dr" (dest)) +#define set_sys_reg(register_name, value) \ + asm("msr " register_name ", %[reg]\n\r" : : [reg] "r" (value)) + +extern void alt_vector_table(void); /* From altvec.S */ +extern volatile uint64_t exception_log[]; /* From altvec.S */ +extern uint64_t realms_gpt0[]; /* From boot.S */ +extern uint64_t realms_gpt1[]; /* From boot.s */ + +const uint32_t gpc_granule_size =3D 4096; +const uint32_t gpis_per_64_bits =3D 16; + +int main(uint64_t sp) +{ + uint64_t out; + uint64_t pfr0; + uint64_t gpt_base; + uint64_t rme_status; + uint64_t currentel_raw; + uint64_t currentel; + uint64_t gpt_table0_addr =3D (uint64_t) realms_gpt0; + uint64_t gpt_table1_addr =3D (uint64_t) realms_gpt1; + + /* Mask is FNG1, FNG0, and A2 */ + const uint64_t feature_mask =3D (1ULL << 18 | 1ULL << 17 | 1ULL << 16); + const uint64_t in =3D feature_mask; + + get_sys_reg("CurrentEL", currentel_raw); + currentel =3D (currentel_raw >> 2) & 0x3; + + if (currentel < 3) { + ml_printf("FAIL: Test must be run at EL3 (it is %d)\n", currentel); + return 1; + } + + get_sys_reg(ID_AA64PFR0_EL1, pfr0); + + /* rme_status is 1 for RME, 2 for RME + GPC2, 3 for RME+GPC3 */ + rme_status =3D (pfr0 >> 52) & 0xF; + ml_printf("RME is %ld\n", rme_status); + if (rme_status < 1) { + ml_printf("SKIP: System does not support GPC (RME=3D%ld)\n", rme_s= tatus); + return 0; + } + + /* Configure the level 0 table for the first 4GB of memory */ + realms_gpt0[0] =3D gpt_table1_addr | 0x3; /* Covers GB 0; table descri= ptor */ + realms_gpt0[1] =3D 0xf1; /* Covers GB 1; full access */ + realms_gpt0[2] =3D 0xf1; /* Covers GB 2; full access */ + realms_gpt0[3] =3D 0xf1; /* Covers GB 3; full access */ + + /* Install new vector table */ + set_sys_reg(VBAR_EL3, alt_vector_table); + + /* Pick a random location to read inside the first 1GB. */ + uint64_t fault_location =3D 0x10202008; + uint32_t gpi_index =3D fault_location / gpc_granule_size; + realms_gpt1[gpi_index / gpis_per_64_bits] =3D 0; + + gpt_base =3D gpt_table0_addr >> 12; + set_sys_reg(GPTBR_EL3, gpt_base); + + /* + * Default values: + * PPS=3D0: GPC table 0 protects 4GB. + * RLPAD=3D0: Realm physical address spaces are normal + * NSPAD=3D0: Non-secure physical address spaces are normal + * SPAD=3D0: Secure physical address spaces are normal + * IRGN=3D0: Inner non-cacheable + * ORGN=3D0: Outer non-cacheable + * PGS=3D0: Physical granule size is 4KB. + * GPCP=3D0: All GPC faults reported + * TBGPCP=3D0: Trace buffer rejects trace + * L0GPTSZ=3D0: Each entry in table 0 protects 1GB. + * APPSAA=3D0: Accesses above 4GB must be to Non-secure PAs + * GPCBW=3D0: Bypass windows disabled. + * NA6, NA7, NSP, SA, NSO are all reserved values for GPI. + */ + uint64_t gpccr =3D 0; + + /* Switch on granule protection check */ + gpccr |=3D 1 << 16; /* GPC enabled. */ + gpccr |=3D 0b10 << 12; /* SH =3D Outer shareable */ + set_sys_reg(GPCCR_EL3, gpccr); + + /* Access some memory outside the GPC forbidden region */ + uint64_t x =3D *(unsigned int *) (fault_location + 4096 * 16); + ml_printf("Fault address: %lx\n", exception_log[0]); + if (exception_log[0] !=3D 0) { + ml_printf("FAIL: Memory access was blocked by GPC, " + "and should not have been\n"); + return 1; + } + + /* Access the GPC forbidden region */ + x =3D *(unsigned int *) fault_location; + + ml_printf("Fault address: %lx\n", exception_log[0]); + if (exception_log[0] !=3D fault_location) { + ml_printf("FAIL: Memory access was not blocked by GPC, " + "and should have been\n"); + return 1; + } + return 0; +} --=20 2.43.0