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Rename few more emphasizing Aarch64 specific features. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/internals.h | 8 ++++---- target/arm/cpu.c | 8 ++++---- target/arm/cpu32-stubs.c | 8 ++++---- target/arm/cpu64.c | 12 ++++++------ 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a632584a4e0..27b284f17b9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1746,10 +1746,10 @@ int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByte= Array *buf, int reg); int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg); -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10feb639c4d..d670ffe4de0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1682,25 +1682,25 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error *= *errp) Error *local_err =3D NULL; =20 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - arm_cpu_sve_finalize(cpu, &local_err); + aarch64_cpu_sve_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - arm_cpu_sme_finalize(cpu, &local_err); + aarch64_cpu_sme_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - arm_cpu_pauth_finalize(cpu, &local_err); + aarch64_cpu_pauth_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - arm_cpu_lpa2_finalize(cpu, &local_err); + aarch64_cpu_lpa2_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; diff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c index 9e50bb1b0b5..d42b1a5d6a6 100644 --- a/target/arm/cpu32-stubs.c +++ b/target/arm/cpu32-stubs.c @@ -4,22 +4,22 @@ #include "target/arm/cpu.h" #include "target/arm/internals.h" =20 -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } =20 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } =20 -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } =20 -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a93ad2da5ad..b38a78aac3f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -60,7 +60,7 @@ int get_sysreg_idx(ARMSysRegs sysreg) =20 #undef DEF =20 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* * If any vector lengths are explicitly enabled with sve properties, @@ -121,7 +121,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * Disable all SVE extensions as well. Note that some ZFR0 * fields are used also by SME so must not be wiped in * an SME-no-SVE config. We will clear the rest in - * arm_cpu_sme_finalize() if necessary. + * aarch_cpu_sme_finalize() if necessary. */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0); FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0); @@ -336,7 +336,7 @@ static void cpu_arm_set_sve(Object *obj, bool value, Er= ror **errp) FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value); } =20 -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp) { uint32_t vq_map =3D cpu->sme_vq.map; uint32_t vq_init =3D cpu->sme_vq.init; @@ -408,7 +408,7 @@ static void cpu_arm_set_sme(Object *obj, bool value, Er= ror **errp) /* * For now, write 0 for "off" and 1 for "on" into the PFR1 field. * We will correct this value to report the right SME - * level (SME vs SME2) in arm_cpu_sme_finalize() later. + * level (SME vs SME2) in aarch_cpu_sme_finalize() later. */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); } @@ -548,7 +548,7 @@ void aarch64_add_sme_properties(Object *obj) #endif } =20 -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { ARMPauthFeature features =3D cpu_isar_feature(pauth_feature, cpu); ARMISARegisters *isar =3D &cpu->isar; @@ -666,7 +666,7 @@ void aarch64_add_pauth_properties(Object *obj) } } =20 -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { uint64_t t; =20 --=20 2.53.0