From nobody Sat May 30 16:41:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778161670; cv=none; d=zohomail.com; s=zohoarc; b=jDZCVTe1F3XIpzWcoAunn1F5G6OWrvAVcLeaBBAXPKCzxf9mW5BKMpVykuvcwfHx/uTU7+FeF2Y/jJvLn16f7Xavyz0gjLHsi3dI+zZxi4lnlLuA0SaQAYLLI0VFiOi62Yh8kqIkeLBUkAEleY7dZaqgH7SNSsD1mOSg2CLvJk8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778161670; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0vnX1tchTMN4f4eTabnG6jZSrIEMOA2BX2sx6GfZ0fk=; b=byjGlFUZ6M99PlKrCI1v1PEwwo1Yz8YswqqDt1gZdnSvcpeC0k0EvVtNw7q1J0kwuOUBX60ZpMVNJXdQyfppjkX/O88um+mxNVw14HL3v95aiUQ8FQRwsgespYbHdNzKRI0wf/2c2/LRpCUZltAWZsloO3D9yPMJFBke4WWRnMM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778161670954919.7062340775276; Thu, 7 May 2026 06:47:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wKz4g-0007rU-HS; Thu, 07 May 2026 09:47:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wKz4T-0007os-UJ for qemu-devel@nongnu.org; Thu, 07 May 2026 09:47:23 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wKz4S-0004Ry-7L for qemu-devel@nongnu.org; Thu, 07 May 2026 09:47:21 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so13010935e9.2 for ; Thu, 07 May 2026 06:47:19 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e538fb1a7sm220467085e9.9.2026.05.07.06.47.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 07 May 2026 06:47:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1778161638; x=1778766438; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0vnX1tchTMN4f4eTabnG6jZSrIEMOA2BX2sx6GfZ0fk=; b=yC7eqW3lBlXUbqjpnKora1bXQozTvxhh5fRApyiRsGJkFm45SdVf5V25C0pMudF2JJ R76Ai/tse8h87AlwYe5a1V/s1Vl8vQIfqeJBBYz23Qytb1yyjA2OK0fAObcAzOxlEhEW 7pVQrhjvZ0ib9Ntf/4VrNKuGLfQpqPYjypY6ni64O9jPZzxJZlTMmE3CyhQzu0uGY4r5 3No2outpX0vXPN2dAJL3R3ZaSB+xdVLjSF3P5jzK3i3vpKNz/ANhugW/d6K3xJlvzDXp 8hQU8e0luz+N1bS+WkMl3sH6zKM0U1Q34oT3FdkRQ/H4+noWkyIa5q9aNjPXZYpNH94b CMQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778161638; x=1778766438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0vnX1tchTMN4f4eTabnG6jZSrIEMOA2BX2sx6GfZ0fk=; b=SbEBO3wTK5yMlcQFEO/vb0uIqs49XPHfbKTaUAZCANxEnmHgQ3+8CeJDub3GmbgaXh vAKWSdRHWzwLcm+bn5JOi45OqWFKbzhacFStVtWPWPmqQeRAxiF1on4Zl79VwXjV4MeY rXJFKn29N+jLXPGzYn/cHqbojAQFcMxklkrzuwfkWDQBRRwArDthzlhHG5cHQOkIhwip DpLkSgB+RIniUWsBqIziS/vFLPqxRxjBA3QDgqTgbAUeto5Vmx+7PixF0Y8RKHGTEndk Lt+sHM8OJsnr/6tSIIk/oD54uM7NbPDVLHZYkpoUUeRu3FpXvn5z6Tl6PHuU4veIL/gy 3evQ== X-Gm-Message-State: AOJu0Yy6ogjV8qlzjm+F2gaIMlOR3MPxTrpiG2PDnmT5xsyoomW6t6Kc +zB5RURc59KaavgRyNmkaCQeUnLmwMTtsGbT+nF7kPQWuMlUlBTKOIlTLs5KF1vjehiqiiUFd1u 7T2a22wM= X-Gm-Gg: AeBDies0icfrr8bewwY/ey10B4cJQ3sODuAPgq9xWxMjc1//EanAC5KyZ/ui2WOXIYZ JxBYfpX2ka1/BxC3vtSXetGXHeA/gQKiRbfSAIauhLgBOTMr7IwRXxNzDYCgevSUUACgFJ60B4D eTAVBLLjU2NOh+RyJRFcO77E4+sPP1lH6EU194TewBv/DwowhHVdytUPQzIu/mSLnOvm8FN40Mx yR/6X+F/Iw9rxyRyWSqgJAxf56mSdfp0bSrNW5PIVuQu0CJ3YKjt74zVjfCO05vehHjZxjv2Q37 posxesHAIAVQzppunahrQF3W7SGT10tnOA+ULTwBs4BKDKcZYIIazPurWxO7YLhphY5XvZciZQT W2pbzUTW9P/iHvOe8y/WwUOGfOhvT3Ya7XPf3dDdo/TEfNmjvrprqhc9jIY7cpTGF5Th51wpW+y UC+0PbPdAxTdkOLvDV85mTWUsJcp8HBd5AUZd9Rt+dRKYG37Zfst2avT8uflfhDaKPRS/WppL+b +Azj1IW6os= X-Received: by 2002:a05:600c:8b08:b0:48a:5501:7995 with SMTP id 5b1f17b1804b1-48e51f32ca9mr140288565e9.18.1778161638183; Thu, 07 May 2026 06:47:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/2] target/arm: Rename Aarch64-specific methods Date: Thu, 7 May 2026 15:47:08 +0200 Message-ID: <20260507134709.70507-2-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260507134709.70507-1-philmd@linaro.org> References: <20260507134709.70507-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1778161673840158501 Various Aarch64 specific methods start with the 'aarch64_' prefix. Rename few more emphasizing Aarch64 specific features. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- target/arm/internals.h | 8 ++++---- target/arm/cpu.c | 8 ++++---- target/arm/cpu32-stubs.c | 8 ++++---- target/arm/cpu64.c | 12 ++++++------ 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a632584a4e0..27b284f17b9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1746,10 +1746,10 @@ int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByte= Array *buf, int reg); int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg); -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); void aarch64_max_tcg_initfn(Object *obj); void aarch64_add_pauth_properties(Object *obj); void aarch64_add_sve_properties(Object *obj); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10feb639c4d..d670ffe4de0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1682,25 +1682,25 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error *= *errp) Error *local_err =3D NULL; =20 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - arm_cpu_sve_finalize(cpu, &local_err); + aarch64_cpu_sve_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - arm_cpu_sme_finalize(cpu, &local_err); + aarch64_cpu_sme_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - arm_cpu_pauth_finalize(cpu, &local_err); + aarch64_cpu_pauth_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - arm_cpu_lpa2_finalize(cpu, &local_err); + aarch64_cpu_lpa2_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; diff --git a/target/arm/cpu32-stubs.c b/target/arm/cpu32-stubs.c index 9e50bb1b0b5..d42b1a5d6a6 100644 --- a/target/arm/cpu32-stubs.c +++ b/target/arm/cpu32-stubs.c @@ -4,22 +4,22 @@ #include "target/arm/cpu.h" #include "target/arm/internals.h" =20 -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } =20 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } =20 -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } =20 -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a93ad2da5ad..b38a78aac3f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -60,7 +60,7 @@ int get_sysreg_idx(ARMSysRegs sysreg) =20 #undef DEF =20 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* * If any vector lengths are explicitly enabled with sve properties, @@ -121,7 +121,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * Disable all SVE extensions as well. Note that some ZFR0 * fields are used also by SME so must not be wiped in * an SME-no-SVE config. We will clear the rest in - * arm_cpu_sme_finalize() if necessary. + * aarch_cpu_sme_finalize() if necessary. */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0); FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0); @@ -336,7 +336,7 @@ static void cpu_arm_set_sve(Object *obj, bool value, Er= ror **errp) FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value); } =20 -void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_sme_finalize(ARMCPU *cpu, Error **errp) { uint32_t vq_map =3D cpu->sme_vq.map; uint32_t vq_init =3D cpu->sme_vq.init; @@ -408,7 +408,7 @@ static void cpu_arm_set_sme(Object *obj, bool value, Er= ror **errp) /* * For now, write 0 for "off" and 1 for "on" into the PFR1 field. * We will correct this value to report the right SME - * level (SME vs SME2) in arm_cpu_sme_finalize() later. + * level (SME vs SME2) in aarch_cpu_sme_finalize() later. */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); } @@ -548,7 +548,7 @@ void aarch64_add_sme_properties(Object *obj) #endif } =20 -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { ARMPauthFeature features =3D cpu_isar_feature(pauth_feature, cpu); ARMISARegisters *isar =3D &cpu->isar; @@ -666,7 +666,7 @@ void aarch64_add_pauth_properties(Object *obj) } } =20 -void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) +void aarch64_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { uint64_t t; =20 --=20 2.53.0 From nobody Sat May 30 16:41:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1778161672; cv=none; d=zohomail.com; s=zohoarc; b=UtE39pZGrLFeYBksWMO94OMWaAc1NWAdzz3QFIQj4HBPeRFN6PdL2cRnyl147InT2EjsP7aotjBTgqMswNljK22LgApW579/+jUutLEyjg5KpWdnF49sgq17eoXEJpilqCP7nvZjw9ieiSzovMqmBvefmcT4y0wb+ml5b1wMpcU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778161672; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=q9chL/SLwUMeu/2j+R75W2A1pHuRpO6RtXQfsY6XREY=; b=k19fTsMs0bcIt8xkCwKZpMV3W2fJMXBbwCO0GyMrKAMK3AAXWMu4uE3zfbVIlcazwFqpsJ3U8vf4xj/cTDZojx9p0U+TrUCSIq/Gg4DfgJ326W089R7c76N6XiR2v+wnq+WLg0NlYAm5EtK6Al+oVuDR8e2IM6UYLzv+5E0UNok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778161672948184.1792070303643; Thu, 7 May 2026 06:47:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wKz4m-0007to-1Q; Thu, 07 May 2026 09:47:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wKz4b-0007rR-9b for qemu-devel@nongnu.org; Thu, 07 May 2026 09:47:31 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wKz4Z-0004T6-9K for qemu-devel@nongnu.org; Thu, 07 May 2026 09:47:28 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-488a8ca4aadso8390295e9.3 for ; Thu, 07 May 2026 06:47:26 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e53891d62sm200348655e9.1.2026.05.07.06.47.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 07 May 2026 06:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1778161645; x=1778766445; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q9chL/SLwUMeu/2j+R75W2A1pHuRpO6RtXQfsY6XREY=; b=Xyl6YXSz1Q+5iVz9eLoTbjSrRzZ2qayN7VAq10jx5pFh7gYiEpxj5iWt9oGETJSFrK qiCardtFl+dV8GrkNCdsLe08N4Bjr17cQmJxE2JJEBBvVusJkUFjk+/paOacr65MbhHa vy7HF5nGFY7LgPPB4CKgbuAMY5CbKbNswBh5wLNPvwOWdq9TjVqjyBSycXOFudu7qjb6 7NmzxIdbTIq8iXwOraP+55zDIAqpZ5vlQehgzthjWPNpp5DcwsXdEu8MKpO8yIYAbA7z vO89JuCSMI/X1hN6uQTJUXNwPXQ7BAdK5b7mvBFDyQVQB3wynHcaTtOxvPrNk28WlWhQ ulQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778161645; x=1778766445; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=q9chL/SLwUMeu/2j+R75W2A1pHuRpO6RtXQfsY6XREY=; b=FgkHXAKLosWVHBkXCaPKvqVkM/ZRSq9C3JhbFX0ARZ+QP17UpfI5XL3M7oXGmb8ztX aa1UUOrSKIgjqZWwLflNw0tugVEv6duh3jSxoPD7t7BSxo4RzWY9k+7OSc4CzUyUbmTD UX7CkDshrT95bGrOKc+6pqWE/rnu1JxQRfFvMUzvoJ7RTLAQahyEHqt2NsE+nn7B+SMw rZZ3iABPjTqgb9J640Pm/afcpM//6hWTQ4xpHDn6cB7Ybg1P7qMsDInkOU6zE0J7vbn2 F7tEZr9NTpK2+Qe15M9FIm8PvDg+4vMTJQQRZQXawhXR0jJJTPbbjGZGbT+X9pPFKDHC oOgg== X-Gm-Message-State: AOJu0YzFUg+zIa1olM/0SlNT8TW0lSQdpwhYEtxeMHtZvESJacU+WZAB zvURBi9YFGM/OVzH2HocEqVRdr5TW8gn3agMM1u5p09umeS7Us7A15Nb09iWC9S50wzqYPMQxn2 eEdYzNt4= X-Gm-Gg: AeBDieurFlL64FA6kDaBDI0nclY4pZ4LXLV4f09a7TxTp00TUmrBG02vO6RVSAJzI2A aPlN5dAzP+Xhqz6kyQg0aLt4zzuxiL55J7n6LNrADD5CD1yRg6sHSQASF4r3L3gTeGJci7aWKoO cmQGJrYTN+smMSIQDVKxqRuv6ASh9IQNKXvEYH8akUR0zb81regkhpkyswG+3JOIhcW6nsQLu+c LsdnUebdtspXbQv3Jam7l6aVhBbXyFjNi6scjZWQyDkpaCOyxamgaYstINJxUr3wYMmHWQaQ9j/ ZuhncVuYN0R/anTMp0zLC+PZkuYE7D8dFwTdzdKaYG38VtrLOB6LKh6v86fGcd2oQEEd2gVvRxG Xt0N06WlxMFwUUc32hhnNJqCXLdPnRKby2bNfOQkDYCbwQZOWxd+ODu5CrTmFHZVWb+hEKKuJJY iLD7QGFtupGlB7e2Uj7l42WaE2osRNXyd5sFypvzP6f8bmUytlxteC1b7zqCvWZS/rVy13sDbo3 S7V86ew34w= X-Received: by 2002:a05:600c:354b:b0:488:ab26:8fe0 with SMTP id 5b1f17b1804b1-48e51f32bdemr132794885e9.15.1778161645105; Thu, 07 May 2026 06:47:25 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/2] target/arm: Extract IDAU interface to its own unit Date: Thu, 7 May 2026 15:47:09 +0200 Message-ID: <20260507134709.70507-3-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260507134709.70507-1-philmd@linaro.org> References: <20260507134709.70507-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1778161674908154100 Move IDAU TypeInfo structure to its own source file and build it once as common ARM object. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/hw/arm/armv7m.h | 2 +- include/hw/misc/tz-msc.h | 2 +- target/arm/{ =3D> tcg}/idau.h | 0 hw/arm/armv7m.c | 2 +- target/arm/cpu.c | 2 +- target/arm/ptw.c | 2 +- target/arm/tcg/cpu32.c | 8 -------- target/arm/tcg/idau.c | 20 ++++++++++++++++++++ target/arm/tcg/meson.build | 1 + 9 files changed, 26 insertions(+), 13 deletions(-) rename target/arm/{ =3D> tcg}/idau.h (100%) create mode 100644 target/arm/tcg/idau.c diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index 98ad08db036..70555962bb9 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -13,7 +13,7 @@ #include "hw/core/sysbus.h" #include "hw/intc/armv7m_nvic.h" #include "hw/misc/armv7m_ras.h" -#include "target/arm/idau.h" +#include "target/arm/tcg/idau.h" #include "qom/object.h" #include "hw/core/clock.h" =20 diff --git a/include/hw/misc/tz-msc.h b/include/hw/misc/tz-msc.h index 07112d8caa3..6cf4c6b09eb 100644 --- a/include/hw/misc/tz-msc.h +++ b/include/hw/misc/tz-msc.h @@ -51,7 +51,7 @@ #define TZ_MSC_H =20 #include "hw/core/sysbus.h" -#include "target/arm/idau.h" +#include "target/arm/tcg/idau.h" #include "qom/object.h" =20 #define TYPE_TZ_MSC "tz-msc" diff --git a/target/arm/idau.h b/target/arm/tcg/idau.h similarity index 100% rename from target/arm/idau.h rename to target/arm/tcg/idau.h diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index a29eab6c915..68a1cbd6316 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -20,7 +20,7 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/log.h" -#include "target/arm/idau.h" +#include "target/arm/tcg/idau.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" #include "target/arm/cpu-qom.h" diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d670ffe4de0..7b29532e6ee 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -24,7 +24,7 @@ #include "qemu/log.h" #include "exec/page-vary.h" #include "system/whpx.h" -#include "target/arm/idau.h" +#include "target/arm/tcg/idau.h" #include "qemu/module.h" #include "qapi/error.h" #include "cpu.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 316e201cfe0..ff7b7a4d0c8 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -17,7 +17,7 @@ #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "idau.h" +#include "target/arm/tcg/idau.h" =20 typedef struct S1Translate { /* diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 2127d456ad6..73d21c6cf7d 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -12,7 +12,6 @@ #include "cpu.h" #include "accel/tcg/cpu-ops.h" #include "internals.h" -#include "target/arm/idau.h" #if !defined(CONFIG_USER_ONLY) #include "hw/core/boards.h" #endif @@ -899,17 +898,10 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { #endif }; =20 -static const TypeInfo idau_interface_type_info =3D { - .name =3D TYPE_IDAU_INTERFACE, - .parent =3D TYPE_INTERFACE, - .class_size =3D sizeof(IDAUInterfaceClass), -}; - static void arm_tcg_cpu_register_types(void) { size_t i; =20 - type_register_static(&idau_interface_type_info); for (i =3D 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { arm_cpu_register(&arm_tcg_cpus[i]); } diff --git a/target/arm/tcg/idau.c b/target/arm/tcg/idau.c new file mode 100644 index 00000000000..57e5c658e9d --- /dev/null +++ b/target/arm/tcg/idau.c @@ -0,0 +1,20 @@ +/* + * QEMU ARM CPU -- interface for the Arm v8M IDAU + * + * Copyright (c) 2018 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "target/arm/tcg/idau.h" + +static const TypeInfo idau_types[] =3D { + { + .name =3D TYPE_IDAU_INTERFACE, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(IDAUInterfaceClass), + } +}; + +DEFINE_TYPES(idau_types) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index d2364aa39c4..fa1e3d6640c 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -56,6 +56,7 @@ arm_common_ss.add(zlib) arm_common_ss.add(files( 'arith_helper.c', 'crypto_helper.c', + 'idau.c', )) =20 arm_common_system_ss.add( --=20 2.53.0