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Tue, 05 May 2026 20:37:00 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Xu , Michael Rolnik , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Pierrick Bouvier , Mark Burton , Peter Maydell , Jim Shu Subject: [PATCH v3 1/5] accel/tcg: Pass access_type as an argument of tlb_set_page*() Date: Wed, 6 May 2026 11:36:38 +0800 Message-ID: <20260506033642.3641390-2-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260506033642.3641390-1-jim.shu@sifive.com> References: <20260506033642.3641390-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=jim.shu@sifive.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1778038692277158500 Content-Type: text/plain; charset="utf-8" Pass the access_type so that we could know CPU will do the read or write access. Then, CPU can fill the CPUTLBEntry[Full] of the specific permission (@prot). It is fine for address_space_translate*() to return different section of read and write access. tlb_set_page*() only sets 'CPUTLBEntry.addr_*' for specific @prot, so access from another @prot will only get TLB miss and start to overwrite 'CPUTLBEntry[Full]' with new @prot. It is the preliminary patch of next commit to pass the iommu_flags to IOMMUMemoryRegion from access_type. Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 14 ++++++++------ include/exec/cputlb.h | 11 +++++++---- target/alpha/helper.c | 2 +- target/avr/helper.c | 3 ++- target/i386/tcg/system/excp_helper.c | 3 ++- target/loongarch/tcg/tlb_helper.c | 2 +- target/m68k/helper.c | 10 +++++++--- target/microblaze/helper.c | 8 ++++---- target/mips/tcg/system/tlb_helper.c | 4 ++-- target/or1k/mmu.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/riscv/cpu_helper.c | 2 +- target/rx/cpu.c | 3 ++- target/s390x/tcg/excp_helper.c | 2 +- target/sh4/helper.c | 3 ++- target/sparc/mmu_helper.c | 6 +++--- target/tricore/helper.c | 2 +- target/xtensa/helper.c | 3 ++- 18 files changed, 48 insertions(+), 34 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d6115bbb0a4..3bc951603dc 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1022,7 +1022,8 @@ static inline void tlb_set_compare(CPUTLBEntryFull *f= ull, CPUTLBEntry *ent, * critical section. */ void tlb_set_page_full(CPUState *cpu, int mmu_idx, - vaddr addr, CPUTLBEntryFull *full) + vaddr addr, MMUAccessType access_type, + CPUTLBEntryFull *full) { CPUTLB *tlb =3D &cpu->neg.tlb; CPUTLBDesc *desc =3D &tlb->d[mmu_idx]; @@ -1185,7 +1186,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, =20 void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, vaddr size) + MMUAccessType access_type, int mmu_idx, + vaddr size) { CPUTLBEntryFull full =3D { .phys_addr =3D paddr, @@ -1195,15 +1197,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr a= ddr, }; =20 assert(is_power_of_2(size)); - tlb_set_page_full(cpu, mmu_idx, addr, &full); + tlb_set_page_full(cpu, mmu_idx, addr, access_type, &full); } =20 void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, + hwaddr paddr, int prot, MMUAccessType access_type, int mmu_idx, vaddr size) { tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED, - prot, mmu_idx, size); + prot, access_type, mmu_idx, size); } =20 /** @@ -1245,7 +1247,7 @@ static bool tlb_fill_align(CPUState *cpu, vaddr addr,= MMUAccessType type, if (ops->tlb_fill_align) { if (ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, memop, size, probe, ra)) { - tlb_set_page_full(cpu, mmu_idx, addr, &full); + tlb_set_page_full(cpu, mmu_idx, addr, type, &full); return true; } } else { diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3a9603a6965..47fa4302a9a 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -41,6 +41,7 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr= _t length); * @cpu: CPU context * @mmu_idx: mmu index of the tlb to modify * @addr: virtual address of the entry to add + * @access_type: access was read/write/execute * @full: the details of the tlb entry * * Add an entry to @cpu tlb index @mmu_idx. All of the fields of @@ -56,6 +57,7 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr= _t length); * used by tlb_flush_page. */ void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, + MMUAccessType access_type, CPUTLBEntryFull *full); =20 /** @@ -65,6 +67,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr = addr, * @paddr: physical address of the page * @attrs: memory transaction attributes * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @access_type: access was read/write/execute * @mmu_idx: MMU index to insert TLB entry for * @size: size of the page in bytes * @@ -81,9 +84,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr = addr, * used by tlb_flush_page. */ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); - + hwaddr paddr, MemTxAttrs attrs, int prot, + MMUAccessType access_type, int mmu_idx, + vaddr size); /** * tlb_set_page: * @@ -92,7 +95,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, * as a convenience for CPUs which don't use memory transaction attributes. */ void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, + hwaddr paddr, int prot, MMUAccessType access_type, int mmu_idx, vaddr size); =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 179dc2dc7ae..7645ff27e20 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -328,7 +328,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, } =20 tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); + prot, access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } =20 diff --git a/target/avr/helper.c b/target/avr/helper.c index 365c8c60e19..4f536f08676 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -143,7 +143,8 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, prot =3D PAGE_READ | PAGE_WRITE; } =20 - tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, paddr, prot, access_type, mmu_idx, + TARGET_PAGE_SIZE); return true; } =20 diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index d7ea77c8558..0fdae83f0a2 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -628,7 +628,8 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int siz= e, tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK, out.paddr & TARGET_PAGE_MASK, cpu_get_mem_attrs(env), - out.prot, mmu_idx, out.page_size); + out.prot, access_type, mmu_idx, + out.page_size); return true; } =20 diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index c0fd8527fe9..f84a62e2861 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -669,7 +669,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address= , int size, prot =3D context.prot; tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); qemu_log_mask(CPU_LOG_MMU, "%s address=3D%" VADDR_PRIx " physical " HWADDR_FMT_= plx " prot %d\n", __func__, address, physical, prot); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bab1843892..61048892adf 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -969,7 +969,7 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, tlb_set_page(cs, address & TARGET_PAGE_MASK, address & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); + qemu_access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } =20 @@ -989,7 +989,8 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, address, access_type, &page_size); if (likely(ret =3D=3D 0)) { tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, mmu_idx, page_size= ); + physical & TARGET_PAGE_MASK, prot, qemu_access_type, + mmu_idx, page_size); return true; } =20 @@ -1461,6 +1462,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, = uint32_t is_read) int prot; int ret; target_ulong page_size; + MMUAccessType qemu_access_type =3D MMU_DATA_LOAD; =20 access_type =3D ACCESS_PTEST; if (env->dfc & 4) { @@ -1468,9 +1470,11 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr,= uint32_t is_read) } if ((env->dfc & 3) =3D=3D 2) { access_type |=3D ACCESS_CODE; + qemu_access_type =3D MMU_INST_FETCH; } if (!is_read) { access_type |=3D ACCESS_STORE; + qemu_access_type =3D MMU_DATA_STORE; } =20 env->mmu.mmusr =3D 0; @@ -1480,7 +1484,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, = uint32_t is_read) if (ret =3D=3D 0) { tlb_set_page(env_cpu(env), addr & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, - prot, access_type & ACCESS_SUPER ? + prot, qemu_access_type, access_type & ACCESS_SUPER ? MMU_KERNEL_IDX : MMU_USER_IDX, page_size); } } diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a1857b72172..2bdf8c3ea03 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -101,8 +101,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, /* MMU disabled or not available. */ address &=3D TARGET_PAGE_MASK; prot =3D PAGE_RWX; - tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, - TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, address, address, attrs, prot, access_= type, + mmu_idx, TARGET_PAGE_SIZE); return true; } =20 @@ -113,8 +113,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, =20 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x prot=3D= %x\n", mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, - TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, access_t= ype, + mmu_idx, TARGET_PAGE_SIZE); return true; } =20 diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index 566924b079e..bf08ba29d02 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -934,7 +934,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } #if !defined(TARGET_MIPS64) @@ -952,7 +952,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } } diff --git a/target/or1k/mmu.c b/target/or1k/mmu.c index 315debaf3e5..c14f03081e1 100644 --- a/target/or1k/mmu.c +++ b/target/or1k/mmu.c @@ -127,7 +127,7 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, in= t size, if (likely(excp =3D=3D 0)) { tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys_addr & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } if (probe) { diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ac607054027..8b55a9e4ddf 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1369,7 +1369,7 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int = size, if (ppc_xlate(cpu, eaddr, access_type, &raddr, &page_size, &prot, mmu_idx, !probe)) { tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - prot, mmu_idx, 1UL << page_size); + prot, access_type, mmu_idx, 1UL << page_size); return true; } if (probe) { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 39c3486ae0f..6ff7b499711 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1927,7 +1927,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 if (ret =3D=3D TRANSLATE_SUCCESS) { tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), - prot, mmu_idx, tlb_size); + prot, access_type, mmu_idx, tlb_size); return true; } else if (probe) { return false; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index b5284199e6d..6114e345e65 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -194,7 +194,8 @@ static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, i= nt size, /* Linear mapping */ address =3D physical =3D addr & TARGET_PAGE_MASK; prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, physical, prot, access_type, + mmu_idx, TARGET_PAGE_SIZE); return true; } =20 diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 05e448d3f20..3363e2818d5 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -184,7 +184,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } if (probe) { diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5d6295618f5..2542d3d88f5 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -812,7 +812,8 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (ret =3D=3D MMU_OK) { address &=3D TARGET_PAGE_MASK; physical &=3D TARGET_PAGE_MASK; - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZ= E); + tlb_set_page(cs, address, physical, prot, access_type, mmu_idx, + TARGET_PAGE_SIZE); return true; } if (probe) { diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a6f76a1ab76..316f4182848 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -236,7 +236,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, "Translate at %" VADDR_PRIx " -> " HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n", address, full.phys_addr, vaddr); - tlb_set_page_full(cs, mmu_idx, vaddr, &full); + tlb_set_page_full(cs, mmu_idx, vaddr, access_type, &full); return true; } =20 @@ -252,7 +252,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ full.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page_full(cs, mmu_idx, vaddr, &full); + tlb_set_page_full(cs, mmu_idx, vaddr, access_type, &full); return true; } else { if (access_type =3D=3D MMU_INST_FETCH) { @@ -777,7 +777,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->= tl, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page_full(cs, mmu_idx, address, &full); + tlb_set_page_full(cs, mmu_idx, address, access_type, &full); return true; } if (probe) { diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7ee8c7fd699..a7173dc73f0 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -86,7 +86,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); + rw, mmu_idx, TARGET_PAGE_SIZE); return true; } else { assert(ret < 0); diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 2d93b45036d..2cd51ba0cb7 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -282,7 +282,8 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, tlb_set_page(cs, address & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); + access, access_type, mmu_idx, + page_size); return true; } else if (probe) { return false; --=20 2.43.0 From nobody Sat May 30 16:48:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1778038668; cv=none; d=zohomail.com; s=zohoarc; b=Rali2uS/xdpu4T1JX1suS71Vle2fETmEEKy+6ToNqPl45l56oQ2DIjraP897J4AK7xNHuQ88dY1qerkFbRG/phwK/rrXsVfEqsnsY5RtUJA/pbYAX4ZmgAUuC3P38jqFAqR1Lhu05mcl6C9zAFCVqwaeTfmzbvObyQKDR1+LLG8= ARC-Message-Signature: i=1; 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Tue, 05 May 2026 20:37:08 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Xu , Michael Rolnik , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Pierrick Bouvier , Mark Burton , Peter Maydell , Jim Shu Subject: [PATCH v3 2/5] accel/tcg: address_space_translate*() will pass the correct iommu_flags Date: Wed, 6 May 2026 11:36:39 +0800 Message-ID: <20260506033642.3641390-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260506033642.3641390-1-jim.shu@sifive.com> References: <20260506033642.3641390-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1778038670266158500 Content-Type: text/plain; charset="utf-8" Instead of IOMMU_NONE, address_space_translate_for_iotlb() now can pass the correct iommu_flags to the IOMMU translate function from the access_type. Since RISC-V wgChecker [1] could permit access in RO or WO permission only, the IOMMUMemoryRegion could return different section for read and write access. To support this kind of IOMMUMemoryRegion in the path of CPU access, we should pass correct iommu_flags here. [1] RISC-V WG: https://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/ Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 3 ++- include/accel/tcg/iommu.h | 12 +++++------- system/physmem.c | 16 +++++++++++----- 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3bc951603dc..4ca4152579b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1050,7 +1050,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, full->attrs, &= prot); + &xlat, &sz, full->attrs, &= prot, + access_type); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx diff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h index 547f8ea0ef0..30655aab4ba 100644 --- a/include/accel/tcg/iommu.h +++ b/include/accel/tcg/iommu.h @@ -14,13 +14,11 @@ #include "exec/hwaddr.h" #include "exec/memattrs.h" =20 -MemoryRegionSection *address_space_translate_for_iotlb(CPUState *cpu, - int asidx, - hwaddr addr, - hwaddr *xlat, - hwaddr *plen, - MemTxAttrs attrs, - int *prot); +MemoryRegionSection * +address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot, + MMUAccessType access_type); =20 #endif =20 diff --git a/system/physmem.c b/system/physmem.c index c58d940e807..564d2c6a648 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -685,12 +685,14 @@ void tcg_iommu_init_notifier_list(CPUState *cpu) MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_ad= dr, hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, int *prot) + MemTxAttrs attrs, int *prot, + MMUAccessType access_type) { MemoryRegionSection *section; IOMMUMemoryRegion *iommu_mr; IOMMUMemoryRegionClass *imrc; IOMMUTLBEntry iotlb; + IOMMUAccessFlags iommu_flags; int iommu_idx; hwaddr addr =3D orig_addr; AddressSpaceDispatch *d =3D address_space_to_dispatch(cpu->cpu_ases[as= idx].as); @@ -707,10 +709,14 @@ address_space_translate_for_iotlb(CPUState *cpu, int = asidx, hwaddr orig_addr, =20 iommu_idx =3D imrc->attrs_to_index(iommu_mr, attrs); tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); - /* We need all the permissions, so pass IOMMU_NONE so the IOMMU - * doesn't short-cut its translation table walk. - */ - iotlb =3D imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); + + if (access_type =3D=3D MMU_DATA_STORE) { + iommu_flags =3D IOMMU_WO; + } else { + iommu_flags =3D IOMMU_RO; + } + + iotlb =3D imrc->translate(iommu_mr, addr, iommu_flags, iommu_idx); addr =3D ((iotlb.translated_addr & ~iotlb.addr_mask) | (addr & iotlb.addr_mask)); /* Update the caller's prot bits to remove permissions the IOMMU --=20 2.43.0 From nobody Sat May 30 16:48:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1778038702; cv=none; d=zohomail.com; s=zohoarc; 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Tue, 05 May 2026 20:37:15 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Xu , Michael Rolnik , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Pierrick Bouvier , Mark Burton , Peter Maydell , Jim Shu Subject: [PATCH v3 3/5] accel/tcg: Provide early AS translate function Date: Wed, 6 May 2026 11:36:40 +0800 Message-ID: <20260506033642.3641390-4-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260506033642.3641390-1-jim.shu@sifive.com> References: <20260506033642.3641390-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1778038704499154100 Content-Type: text/plain; charset="utf-8" New early AS translate function will skip IOMMU translation. It will return IOMMU region if finding it. Original function is renamed to the late translate function. It is preparation commit of IOMMU lazy translation. Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 6 ++--- include/accel/tcg/iommu.h | 13 +++++++---- system/physmem.c | 46 ++++++++++++++++++++++++++++++++++++--- 3 files changed, 55 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4ca4152579b..f0c049e1551 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1049,9 +1049,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, =20 prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); - section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, full->attrs, &= prot, - access_type); + section =3D address_space_translate_for_iotlb_late(cpu, asidx, paddr_p= age, + &xlat, &sz, full->att= rs, + &prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx diff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h index 30655aab4ba..11e3d63d798 100644 --- a/include/accel/tcg/iommu.h +++ b/include/accel/tcg/iommu.h @@ -15,10 +15,15 @@ #include "exec/memattrs.h" =20 MemoryRegionSection * -address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, - hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, int *prot, - MMUAccessType access_type); +address_space_translate_for_iotlb_early(CPUState *cpu, int asidx, hwaddr a= ddr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot); + +MemoryRegionSection * +address_space_translate_for_iotlb_late(CPUState *cpu, int asidx, hwaddr ad= dr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot, + MMUAccessType access_type); =20 #endif =20 diff --git a/system/physmem.c b/system/physmem.c index 564d2c6a648..6e2d43e850f 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -682,11 +682,11 @@ void tcg_iommu_init_notifier_list(CPUState *cpu) } =20 /* Called from RCU critical section */ -MemoryRegionSection * +static MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_ad= dr, hwaddr *xlat, hwaddr *plen, MemTxAttrs attrs, int *prot, - MMUAccessType access_type) + MMUAccessType access_type, bool early_tr= ans) { MemoryRegionSection *section; IOMMUMemoryRegion *iommu_mr; @@ -710,6 +710,11 @@ address_space_translate_for_iotlb(CPUState *cpu, int a= sidx, hwaddr orig_addr, iommu_idx =3D imrc->attrs_to_index(iommu_mr, attrs); tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); =20 + /* Defer the iommu translation */ + if (early_trans) { + break; + } + if (access_type =3D=3D MMU_DATA_STORE) { iommu_flags =3D IOMMU_WO; } else { @@ -737,7 +742,8 @@ address_space_translate_for_iotlb(CPUState *cpu, int as= idx, hwaddr orig_addr, d =3D flatview_to_dispatch(address_space_to_flatview(iotlb.target_= as)); } =20 - assert(!memory_region_is_iommu(section->mr)); + /* For late translation, IOMMU region translation should be finished */ + assert(early_trans || !memory_region_is_iommu(section->mr)); *xlat =3D addr; return section; =20 @@ -755,6 +761,40 @@ translate_fail: return &d->map.sections[PHYS_SECTION_UNASSIGNED]; } =20 +/* + * address_space_translate_for_iotlb_early: translate address without + * performing IOMMU translation. This is used for CPU TLB setup. + * + * Called from RCU critical section. + */ +MemoryRegionSection * +address_space_translate_for_iotlb_early(CPUState *cpu, int asidx, + hwaddr orig_addr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot) +{ + /* access_type doesn't matter for early translation */ + return address_space_translate_for_iotlb(cpu, asidx, orig_addr, xlat, = plen, + attrs, prot, MMU_DATA_LOAD, t= rue); +} + +/* + * address_space_translate_for_iotlb_late: translate address with + * performing IOMMU translation. This is used for lazy IOMMU translation. + * + * Called from RCU critical section. + */ +MemoryRegionSection * +address_space_translate_for_iotlb_late(CPUState *cpu, int asidx, + hwaddr orig_addr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot, + MMUAccessType access_type) +{ + return address_space_translate_for_iotlb(cpu, asidx, orig_addr, xlat, = plen, + attrs, prot, access_type, fal= se); +} + #endif /* CONFIG_TCG */ =20 void cpu_address_space_init(CPUState *cpu, int asidx, --=20 2.43.0 From nobody Sat May 30 16:48:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1778038685; cv=none; d=zohomail.com; s=zohoarc; b=elUyQuR4J8PZ8lqLYJs/ELaLsePmCh04Xyrk4wVSYIDJc6VxFHvvAsAdN4gsNzDKVbTLvurhmZwr2mJSjE8JdfSJQvnArAu49U9IWG5cZRr6nDiQv/RzMUT1dJWpAGl5bonR9m7ziZeeZJ2AW8DaTtSU3IHBoPCBAL+MyPO4hnE= ARC-Message-Signature: i=1; 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Tue, 05 May 2026 20:37:22 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Xu , Michael Rolnik , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Pierrick Bouvier , Mark Burton , Peter Maydell , Jim Shu Subject: [PATCH v3 4/5] accel/tcg: Add IOMMU lazy translation function Date: Wed, 6 May 2026 11:36:41 +0800 Message-ID: <20260506033642.3641390-5-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260506033642.3641390-1-jim.shu@sifive.com> References: <20260506033642.3641390-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1778038686116158500 Content-Type: text/plain; charset="utf-8" The lazy translation will translate IOMMU regions of the specific access_type and store the result into the CPUTLBEntryFull. For CPUTLBEntry, lazy translation may update 'addend' and 'addr_idx' array. We restrict IOMMU region to have a single non-zero 'addend' across all permissions. Also, lazy translation only updates the 'addr_idx' for the permissions specified in @prot. Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 168 ++++++++++++++++++++++++++++++++++++++++++ include/hw/core/cpu.h | 15 ++++ 2 files changed, 183 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f0c049e1551..5735f632896 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1272,6 +1272,174 @@ static inline void cpu_unaligned_access(CPUState *c= pu, vaddr addr, mmu_idx, retaddr); } =20 +/* + * Perform lazy IOMMU translation for a CPUTLBEntry/CPUTLBEntryFull. + * This is called when CPU utilize the TLB entry in the slow path. + * Updates both entry and full entry to IOMMU translated data for the + * specific access type. + */ +static void +tlb_translate_iommu(CPUState *cpu, int mmu_idx, + vaddr addr, MMUAccessType access_type, + CPUTLBEntryFull *full) +{ + CPUTLB *tlb =3D &cpu->neg.tlb; + MemoryRegionSection *section; + unsigned int read_flags, write_flags; + uintptr_t addend; + CPUTLBEntry *te; + hwaddr iotlb, xlat, sz, paddr_page; + vaddr addr_page; + int asidx, wp_flags, prot; + bool is_ram, is_romd; + + if (!full->is_iommu || (full->iommu_last_at =3D=3D access_type)) { + return; + } + + assert_cpu_is_self(cpu); + + if (full->lg_page_size <=3D TARGET_PAGE_BITS) { + sz =3D TARGET_PAGE_SIZE; + } else { + sz =3D (hwaddr)1 << full->lg_page_size; + tlb_add_large_page(cpu, mmu_idx, addr, sz); + } + addr_page =3D addr & TARGET_PAGE_MASK; + paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; + + prot =3D full->prot; + asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); + + section =3D address_space_translate_for_iotlb_late(cpu, asidx, paddr_p= age, + &xlat, &sz, full->att= rs, + &prot, access_type); + + assert(sz >=3D TARGET_PAGE_SIZE); + + tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx + " prot=3D%x idx=3D%d\n", + addr, full->phys_addr, prot, mmu_idx); + + is_ram =3D memory_region_is_ram(section->mr); + is_romd =3D memory_region_is_romd(section->mr); + + read_flags =3D full->tlb_fill_flags; + if (full->lg_page_size < TARGET_PAGE_BITS) { + /* Repeat the MMU check and TLB fill on every access. */ + read_flags |=3D TLB_INVALID_MASK; + } + + if (is_ram || is_romd) { + /* RAM and ROMD both have associated host memory. */ + addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + xla= t; + } else { + /* I/O and IOMMU does not; force the host address to NULL. */ + addend =3D 0; + } + + write_flags =3D read_flags; + + if (is_ram) { + iotlb =3D memory_region_get_ram_addr(section->mr) + xlat; + assert(!(iotlb & ~TARGET_PAGE_MASK)); + /* + * Computing is_clean is expensive; avoid all that unless + * the page is actually writable. + */ + if (prot & PAGE_WRITE) { + if (section->readonly) { + write_flags |=3D TLB_DISCARD_WRITE; + } else if (physical_memory_is_clean(iotlb)) { + write_flags |=3D TLB_NOTDIRTY; + } + } + } else { + /* I/O or ROMD */ + iotlb =3D xlat; + /* + * Writes to romd devices must go through MMIO to enable write. + * Reads to romd devices go through the ram_ptr found above, + * but of course reads to I/O must go through MMIO. + */ + write_flags |=3D TLB_MMIO; + if (!is_romd) { + read_flags =3D write_flags; + } + } + + wp_flags =3D cpu_watchpoint_address_matches(cpu, addr_page, + TARGET_PAGE_SIZE); + + /* Update the CPUTLBEntryFull for this access type. */ + full->iommu_last_at =3D access_type; + full->xlat_offset =3D iotlb - addr_page; + full->section =3D section; + full->phys_addr =3D paddr_page; + + /* Update the CPUTLBEntry: addend and addr_idx */ + tlb =3D &cpu->neg.tlb; + te =3D tlb_entry(cpu, mmu_idx, addr_page); + + qemu_spin_lock(&tlb->c.lock); + + /* + * If IOMMU region is translated to the memories (has associated + * host memory), it will update the 'addend' to access memories in the + * fast path. Otherwise, IO region do not update the 'addend' because + * it might be already used by memory region from the other permission= s. + * It is fine since IO region do not use addend. + */ + if (is_ram || is_romd) { + if (te->addend + addr_page) { + /* addend of untranslated IOMMU region is 0 - addr_page. */ + + /* + * CPUTLBEntry only has 1 addend across all permissions. + * We don't support the IOMMUMemoryRegion to be translated to + * 2 different host memories from the different permissions. + * QEMU will trigger an assertion for such case. + */ + g_assert(addend =3D=3D te->addend + addr_page); + } else { + te->addend =3D addend - addr_page; + } + } + + /* + * In the IOMMU lazy translation, we only update TLB flags for the + * permissions specified in @prot. For other permissions, we still + * keep the original TLB flags (e.g. TLB_IOMMU if not translated). + */ + if (prot & PAGE_EXEC) { + tlb_set_compare(full, te, addr_page, read_flags, + MMU_INST_FETCH, prot & PAGE_EXEC); + } + + if (wp_flags & BP_MEM_READ) { + read_flags |=3D TLB_WATCHPOINT; + } + if (prot & PAGE_READ) { + tlb_set_compare(full, te, addr_page, read_flags, + MMU_DATA_LOAD, prot & PAGE_READ); + } + + if (prot & PAGE_WRITE_INV) { + write_flags |=3D TLB_INVALID_MASK; + } + if (wp_flags & BP_MEM_WRITE) { + write_flags |=3D TLB_WATCHPOINT; + } + if (prot & PAGE_WRITE) { + tlb_set_compare(full, te, addr_page, write_flags, + MMU_DATA_STORE, prot & PAGE_WRITE); + } + + qemu_spin_unlock(&tlb->c.lock); + + return; +} + static MemoryRegionSection * io_prepare(hwaddr *out_offset, CPUState *cpu, CPUTLBEntryFull *full, vaddr addr, uintptr_t retaddr) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 207a7a1becb..cfbce50d1c5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -254,6 +254,21 @@ struct CPUTLBEntryFull { */ uint8_t slow_flags[MMU_ACCESS_COUNT]; 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Tue, 05 May 2026 20:37:29 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Peter Xu , Michael Rolnik , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Pierrick Bouvier , Mark Burton , Peter Maydell , Jim Shu Subject: [PATCH v3 5/5] accel/tcg: Support IOMMU lazy translation in CPU TLB Date: Wed, 6 May 2026 11:36:42 +0800 Message-ID: <20260506033642.3641390-6-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260506033642.3641390-1-jim.shu@sifive.com> References: <20260506033642.3641390-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1778038694564154100 Content-Type: text/plain; charset="utf-8" tlb_set_page_full() no longer translates IOMMU region, but only stores untranslated IOMMU region in the CPUTLBEntryFull. Then, when CPU uses CPUTLBEntryFull in the slow path. it should perform the lazy translation via tlb_translate_iommu(). The untranslated IOMMU region in TLB always requires to run in the slow path to trigger the lazy translation, so the IOMMU region will contain a new TLB flag, TLB_IOMMU, to force the slow path. Lazy translation will overwrite the TLB flags to the flags of the translated region. The host memory region from IOMMU region can still run in the fast path to accelerate the performance. Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 66 ++++++++++++++++++++++++++++++++++------ include/exec/tlb-flags.h | 4 ++- 2 files changed, 60 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5735f632896..7a44ae8238b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1034,7 +1034,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, hwaddr iotlb, xlat, sz, paddr_page; vaddr addr_page; int asidx, wp_flags, prot; - bool is_ram, is_romd; + bool is_ram, is_romd, is_iommu; =20 assert_cpu_is_self(cpu); =20 @@ -1049,29 +1049,38 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, =20 prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); - section =3D address_space_translate_for_iotlb_late(cpu, asidx, paddr_p= age, - &xlat, &sz, full->att= rs, - &prot); + + /* + * Use the early translation to check if it is an IOMMU region. + * This function stops at IOMMU regions without translating through th= em. + */ + section =3D address_space_translate_for_iotlb_early(cpu, asidx, paddr_= page, + &xlat, &sz, full->at= trs, + &prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx " prot=3D%x idx=3D%d\n", addr, full->phys_addr, prot, mmu_idx); =20 + is_iommu =3D memory_region_is_iommu(section->mr); + is_ram =3D memory_region_is_ram(section->mr); + is_romd =3D memory_region_is_romd(section->mr); + + full->is_iommu =3D is_iommu; + full->iommu_last_at =3D MMU_ACCESS_COUNT; + read_flags =3D full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |=3D TLB_INVALID_MASK; } =20 - is_ram =3D memory_region_is_ram(section->mr); - is_romd =3D memory_region_is_romd(section->mr); - if (is_ram || is_romd) { /* RAM and ROMD both have associated host memory. */ addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + xla= t; } else { - /* I/O does not; force the host address to NULL. */ + /* I/O and IOMMU does not; force the host address to NULL. */ addend =3D 0; } =20 @@ -1090,6 +1099,15 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, write_flags |=3D TLB_NOTDIRTY; } } + } else if (is_iommu) { + /* IOMMU */ + iotlb =3D xlat; + /* + * If IOMMU region is not translated, any access will go to + * the slow path and do the lazy IOMMU translation. + */ + read_flags |=3D TLB_IOMMU; + write_flags |=3D TLB_IOMMU; } else { /* I/O or ROMD */ iotlb =3D xlat; @@ -1568,6 +1586,11 @@ static int probe_access_internal(CPUState *cpu, vadd= r addr, flags &=3D tlb_addr; =20 *pfull =3D full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + + if (full->is_iommu) { + tlb_translate_iommu(cpu, mmu_idx, addr, access_type, full); + } + flags |=3D full->slow_flags[access_type]; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ @@ -1760,6 +1783,11 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, in= t mmu_idx, } =20 full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + + if (full->is_iommu) { + tlb_translate_iommu(cpu, mmu_idx, addr, access_type, full); + } + data->phys_addr =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); =20 /* We must have an iotlb entry for MMIO */ @@ -1833,6 +1861,11 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPage= Data *data, MemOp memop, } =20 full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + + if (full->is_iommu) { + tlb_translate_iommu(cpu, mmu_idx, addr, access_type, full); + } + flags =3D tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); flags |=3D full->slow_flags[access_type]; =20 @@ -1944,6 +1977,11 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, Me= mOpIdx oi, if (mmu_lookup1(cpu, &l->page[1], 0, l->mmu_idx, type, ra)) { uintptr_t index =3D tlb_index(cpu, l->mmu_idx, addr); l->page[0].full =3D &cpu->neg.tlb.d[l->mmu_idx].fulltlb[index]; + + if (l->page[0].full->is_iommu) { + tlb_translate_iommu(cpu, l->mmu_idx, addr, type, + l->page[0].full); + } } =20 flags =3D l->page[0].flags | l->page[1].flags; @@ -2001,6 +2039,17 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr = addr, MemOpIdx oi, tlb_addr =3D tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } =20 + full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + + if (full->is_iommu) { + /* + * Do IOMMU lazy translation before accessing addr_idx and TLB fla= gs. + * Generate TLB flags for both read and write. + */ + tlb_translate_iommu(cpu, mmu_idx, addr, MMU_DATA_LOAD, full); + tlb_translate_iommu(cpu, mmu_idx, addr, MMU_DATA_STORE, full); + } + /* * Let the guest notice RMW on a write-only page. * We have just verified that the page is writable. @@ -2035,7 +2084,6 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr a= ddr, MemOpIdx oi, } =20 /* Finish collecting tlb flags for both read and write. */ - full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; tlb_addr |=3D tlbe->addr_read; tlb_addr &=3D TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; tlb_addr |=3D full->slow_flags[MMU_DATA_STORE]; diff --git a/include/exec/tlb-flags.h b/include/exec/tlb-flags.h index 357e79095c9..d78f1c3dc64 100644 --- a/include/exec/tlb-flags.h +++ b/include/exec/tlb-flags.h @@ -52,10 +52,12 @@ #define TLB_DISCARD_WRITE (1 << 3) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << 4) +/* Set if TLB entry is a IOMMU region which requires lazy translation. */ +#define TLB_IOMMU (1 << 5) =20 #define TLB_SLOW_FLAGS_MASK \ (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED | \ - TLB_DISCARD_WRITE | TLB_MMIO) + TLB_DISCARD_WRITE | TLB_MMIO | TLB_IOMMU) =20 /* * Flags stored in CPUTLBEntry.addr_idx[x]. --=20 2.43.0