From nobody Tue May 26 20:35:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1778007083; cv=none; d=zohomail.com; s=zohoarc; b=iw+e40MQWTFyrg6loruvxJy0Lv3R6dMpPSxlAyqCI8i8040MYf2Mcx97y3JgSKE73H+9VkyYI8fDNt8GbpedvqUnJJYfHRZ5heEibJWNuwcZdLTDnsYnZm+AFGF37zEJbta9PzcddAYGeonZEOPfibQyuHCRJK87dhWPUpCDUuA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778007083; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iSlTLr4PLNpzYhYqZJq4BJSiCn3mNgEhOyCqyA5A3xI=; b=X9+jXfar6ZK7GRa5SDa0oiUbEplM8E+7giqgW9ro6Rm1B4U70RaZBB02P4jg6C7jnX/Yc2jHNOMBaBmy8xJEFgaCNRcyHKF327NeuF8SKWJNaEtC6KbeuFYyEpif2LTjVb/wtSA/frwPo7FnI+nb3fPNz/Cm6RDYpj36zrfhe2Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1778007083179419.9159440382541; Tue, 5 May 2026 11:51:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wKKr2-0000ev-SH; Tue, 05 May 2026 14:50:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wKKqx-0000eG-Io for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:44 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wKKqt-0006iG-CH for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:42 -0400 Received: from laptop.localdomain (unknown [86.121.140.248]) by linux.microsoft.com (Postfix) with ESMTPSA id 9FF6820B7169; Tue, 5 May 2026 11:50:33 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 9FF6820B7169 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1778007035; bh=iSlTLr4PLNpzYhYqZJq4BJSiCn3mNgEhOyCqyA5A3xI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D9NyuyZgmNg1QqsbxGrwzeKXolGOO6kEjwH6NMkaae08zgUerOTeQ7zPF9LD6oxVz 1a9evJGwwkMuQlimTpqPU7NbAFkABIcCaaT+jebdH8RVZSnYWlGNYydpOSk0DdXzWy D7Y7Gej3TivY4y3iPi4xvESIi2xBfM+Dcm0bJU5c= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= , Magnus Kulke , Zhao Liu , Wei Liu , Paolo Bonzini Subject: [PATCH v2 1/7] target/i386/mshv: remove duplicate function for reading vcpu registers Date: Tue, 5 May 2026 21:50:22 +0300 Message-ID: <20260505185028.237207-2-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260505185028.237207-1-dblanzeanu@linux.microsoft.com> References: <20260505185028.237207-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1778007086413154100 Remove function `fetch_guest_state` because it is a duplicate function of `mshv_load_regs` function. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Anirudh Rayabharam (Microsoft) Reviewed-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 4ed6e7548f..9defd05db6 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1291,25 +1291,6 @@ static int handle_pio_non_str(const CPUState *cpu, return 0; } =20 -static int fetch_guest_state(CPUState *cpu) -{ - int ret; - - ret =3D mshv_get_standard_regs(cpu); - if (ret < 0) { - error_report("Failed to get standard registers"); - return -1; - } - - ret =3D mshv_get_special_regs(cpu); - if (ret < 0) { - error_report("Failed to get special registers"); - return -1; - } - - return 0; -} - static int read_memory(const CPUState *cpu, uint64_t initial_gva, uint64_t initial_gpa, uint64_t gva, uint8_t *data, size_t len) @@ -1429,7 +1410,7 @@ static int handle_pio_str(CPUState *cpu, hv_x64_io_po= rt_intercept_message *info) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - ret =3D fetch_guest_state(cpu); + ret =3D mshv_load_regs(cpu); if (ret < 0) { error_report("Failed to fetch guest state"); return -1; --=20 2.53.0 From nobody Tue May 26 20:35:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1778007114; cv=none; d=zohomail.com; s=zohoarc; b=ezhL6MBiFkLObYTUnBJ07NTURCSvWJQ4vfHS8XSI26hF8ijbjkpir6a5gE/kgxGD44Z3+A6iswr2xCNXF5+jSBwqqv/ulrw8XwnxGf1ZiaQLmieyO8ZCQGH+90V09EWhUERnE+L5M79rQzHtZ1wV3/DqMWfbwh0Mx/aL2bRWQog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778007114; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1778007116602154100 Call mshv_arch_init_vcpu after the vcpu is created to ensure a valid vcpu fd. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Anirudh Rayabharam (Microsoft) Reviewed-by: Magnus Kulke --- accel/mshv/mshv-all.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index 58af674bd9..e3da583f21 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -415,13 +415,14 @@ static int mshv_init_vcpu(CPUState *cpu) int ret; =20 cpu->accel =3D g_new0(AccelCPUState, 1); - mshv_arch_init_vcpu(cpu); =20 ret =3D mshv_create_vcpu(vm_fd, vp_index, &cpu->accel->cpufd); if (ret < 0) { return -1; } =20 + mshv_arch_init_vcpu(cpu); + cpu->accel->dirty =3D true; =20 return 0; --=20 2.53.0 From nobody Tue May 26 20:35:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1778007120679154100 Define the `hv_vp_register_page` structure that the linux kernel uses to allow access to vcpu registers. This structure is going to be used in later patches to access vcpu registers. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Anirudh Rayabharam (Microsoft) Reviewed-by: Magnus Kulke --- include/hw/hyperv/hvgdk.h | 2 + include/hw/hyperv/hvhdk.h | 105 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+) diff --git a/include/hw/hyperv/hvgdk.h b/include/hw/hyperv/hvgdk.h index 71161f477c..e4be861716 100644 --- a/include/hw/hyperv/hvgdk.h +++ b/include/hw/hyperv/hvgdk.h @@ -9,6 +9,8 @@ #ifndef HW_HYPERV_HVGDK_H #define HW_HYPERV_HVGDK_H =20 +#include "hvgdk_mini.h" + #define HVGDK_H_VERSION (25125) =20 enum hv_unimplemented_msr_action { diff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h index 41af743847..4a3b543893 100644 --- a/include/hw/hyperv/hvhdk.h +++ b/include/hw/hyperv/hvhdk.h @@ -9,7 +9,11 @@ #ifndef HW_HYPERV_HVHDK_H #define HW_HYPERV_HVHDK_H =20 +#include "hvgdk.h" +#include "hvhdk_mini.h" + #define HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS 1 +#define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT 7 =20 struct hv_input_set_partition_property { uint64_t partition_id; @@ -246,4 +250,105 @@ typedef struct hv_input_register_intercept_result { union hv_register_intercept_result_parameters parameters; } QEMU_PACKED hv_input_register_intercept_result; =20 +/* Flags for dirty mask of hv_vp_register_page */ +enum hv_x64_register_class_type { + HV_X64_REGISTER_CLASS_GENERAL =3D 0, + HV_X64_REGISTER_CLASS_IP =3D 1, + HV_X64_REGISTER_CLASS_XMM =3D 2, + HV_X64_REGISTER_CLASS_SEGMENT =3D 3, + HV_X64_REGISTER_CLASS_FLAGS =3D 4, +}; + +union hv_vp_register_page_interrupt_vectors { + uint64_t as_uint64; + struct { + uint8_t vector_count; + uint8_t vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT]; + }; +}; + +struct hv_vp_register_page { + uint16_t version; + uint8_t isvalid; + uint8_t rsvdz; + uint32_t dirty; + + union { + struct { + /* General purpose registers (HV_X64_REGISTER_CLASS_GENERAL) */ + union { + struct { + uint64_t rax; + uint64_t rcx; + uint64_t rdx; + uint64_t rbx; + uint64_t rsp; + uint64_t rbp; + uint64_t rsi; + uint64_t rdi; + uint64_t r8; + uint64_t r9; + uint64_t r10; + uint64_t r11; + uint64_t r12; + uint64_t r13; + uint64_t r14; + uint64_t r15; + } QEMU_PACKED; + + uint64_t gp_registers[16]; + }; + /* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */ + uint64_t rip; + /* Flags (HV_X64_REGISTER_CLASS_FLAGS) */ + uint64_t rflags; + } QEMU_PACKED; + + uint64_t registers[18]; + }; + uint8_t reserved[8]; + /* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */ + union { + struct { + struct hv_u128 xmm0; + struct hv_u128 xmm1; + struct hv_u128 xmm2; + struct hv_u128 xmm3; + struct hv_u128 xmm4; + struct hv_u128 xmm5; + } QEMU_PACKED; + + struct hv_u128 xmm_registers[6]; + }; + /* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */ + union { + struct { + struct hv_x64_segment_register es; + struct hv_x64_segment_register cs; + struct hv_x64_segment_register ss; + struct hv_x64_segment_register ds; + struct hv_x64_segment_register fs; + struct hv_x64_segment_register gs; + } QEMU_PACKED; + + struct hv_x64_segment_register segment_registers[6]; + }; + /* Misc. control registers (cannot be set via this interface) */ + uint64_t cr0; + uint64_t cr3; + uint64_t cr4; + uint64_t cr8; + uint64_t efer; + uint64_t dr7; + union hv_x64_pending_interruption_register pending_interruption; + union hv_x64_interrupt_state_register interrupt_state; + uint64_t instruction_emulation_hints; + uint64_t xfem; + + uint8_t reserved1[0x100]; + + /* Interrupts injected as part of HvCallDispatchVp. */ + union hv_vp_register_page_interrupt_vectors interrupt_vectors; +} QEMU_PACKED; + #endif /* HW_HYPERV_HVHDK_H */ --=20 2.53.0 From nobody Tue May 26 20:35:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1778007122; cv=none; d=zohomail.com; s=zohoarc; b=IPPKVtYxuCumwLZa7O7IxWuMFNrMS7Vwdmhh687hO1dl17Ar1rvRU9yVYA8h0/yNQXBr4KEMIynQUF6BvbrYHwqnO50U3q1m9lPY2+SoRAMidQTQSR35dCYPulEVS6+8gP74hNfbtgZFbcK21Vg1Pc65CFTfa05BhQ5wvz5TmnE= ARC-Message-Signature: i=1; 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Tue, 05 May 2026 14:50:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wKKr4-0000fg-6K for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:50 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wKKr1-0006jG-Tf for qemu-devel@nongnu.org; Tue, 05 May 2026 14:50:49 -0400 Received: from laptop.localdomain (unknown [86.121.140.248]) by linux.microsoft.com (Postfix) with ESMTPSA id AD4BD20B716C; Tue, 5 May 2026 11:50:40 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com AD4BD20B716C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1778007042; bh=0BKwOecAhGjoVx5AIvhBMINDtDxE83/qd2X5k8o4a3M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b79crTMftNC+TelxPmY49Gsnezfg5vHhvkJapjNewH3I83BVriVlIgLzkKauWqL7x pc7pbmE9+sLvx94I6zjzZHZ7KdWUDQc5jofu0cpWBsxnct0EQ5B/1G/ESmtpV5QHOX TRBs3YiCaSP47FF2I3C6xNiaGfyy7ayfYgsGUo9Y= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= , Magnus Kulke , Zhao Liu , Wei Liu , Paolo Bonzini Subject: [PATCH v2 4/7] target/i386/mshv: hv_vp_register_page setup for the vcpu Date: Tue, 5 May 2026 21:50:25 +0300 Message-ID: <20260505185028.237207-5-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260505185028.237207-1-dblanzeanu@linux.microsoft.com> References: <20260505185028.237207-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1778007124679154100 When the vcpu is created, call mmap to configure access to the register pag= e. In case the call to mmap fails, we log an error and continue with the previous logic (using hypercalls). Update CPUArchState to store a pointer to the mmapped hv_vp_register_page. Signed-off-by: Doru Bl=C3=A2nzeanu --- target/i386/cpu.h | 5 +++++ target/i386/mshv/mshv-cpu.c | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 16de67e546..fd4c3712b1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2019,6 +2019,11 @@ typedef struct CPUArchState { uint64_t msr_bndcfgs; uint64_t efer; =20 +#ifdef CONFIG_MSHV + /* Shared register page */ + struct hv_vp_register_page *regs_page; +#endif + /* Beginning of state preserved by INIT (dummy marker). */ struct {} start_init_save; =20 diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 9defd05db6..3a3c269c33 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1587,6 +1587,7 @@ void mshv_arch_init_vcpu(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; AccelCPUState *state =3D cpu->accel; size_t page =3D HV_HYP_PAGE_SIZE; + void *regs_page; void *mem =3D qemu_memalign(page, 2 * page); =20 /* sanity check, to make sure we don't overflow the page */ @@ -1595,6 +1596,22 @@ void mshv_arch_init_vcpu(CPUState *cpu) + sizeof(hv_input_get_vp_registers) > HV_HYP_PAGE_SIZE)); =20 + + /* mmap the registers page */ + regs_page =3D mmap(NULL, page, PROT_READ | PROT_WRITE, + MAP_SHARED, mshv_vcpufd(cpu), + MSHV_VP_MMAP_OFFSET_REGISTERS * page); + if (regs_page =3D=3D MAP_FAILED) { + /* + * Error is not fatal, but we won't be able to use the + * fast path for register access + */ + error_report("register page mmap failed: %s", strerror(errno)); + env->regs_page =3D NULL; + } else { + env->regs_page =3D (struct hv_vp_register_page *) regs_page; + } + state->hvcall_args.base =3D mem; state->hvcall_args.input_page =3D mem; state->hvcall_args.output_page =3D (uint8_t *)mem + page; @@ -1608,6 +1625,11 @@ void mshv_arch_destroy_vcpu(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; AccelCPUState *state =3D cpu->accel; =20 + /* Unmap the register page */ + if (env->regs_page) { + munmap(env->regs_page, HV_HYP_PAGE_SIZE); + env->regs_page =3D NULL; + } g_free(state->hvcall_args.base); state->hvcall_args =3D (MshvHvCallArgs){0}; g_clear_pointer(&env->emu_mmio_buf, g_free); --=20 2.53.0 From nobody Tue May 26 20:35:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1778007092; cv=none; d=zohomail.com; s=zohoarc; b=Wr9YsPLZqIKwXzAAecQ69clRjZOObSImPKDoMBBLqgDD9NLFBApxNfUbvXLd9j65ScjhC0NEBsQv1wVC75wgPPgWIaDSAVTOf7MArv8aDublMMK/MqF0fIKKVsVniUA3JQ4URHMAyXDG5miBEg+fKnrL4qiNzWpfC0jhSsDsrNw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778007092; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hJxydqpkaxAkHgGCUh/fsgKB/bQh6BDju7BvGawDrFA=; b=kso7ht+SuaMFRDRhk+aRB0xt9j2vFftqDkYXSuVvIY5Rv2oKb/NvoG+2jlQJk/WA/5WBmxho/l0aXyGtGs/fuQMZh4Kg8TZO8gyapBadixEGgsdzy4IUW/ElNzqJfDTXU1CEjcOB3U/YqTK/fAKykMLCbsF/GFHIPxk05qPy+6M= ARC-Authentication-Results: i=1; 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Tue, 5 May 2026 11:50:43 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 4B23120B7168 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1778007044; bh=hJxydqpkaxAkHgGCUh/fsgKB/bQh6BDju7BvGawDrFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JQMjRLm4xmFoZenodmwBneojEJoWS9XVrugZBK6hLPl0+bIIA6Tm1hx7eGrq0Mi7g 0o55AQ7pNJVIb0uZGMsEtcLCrDYmR8fYu4wTg3hKOzoVeVtVEH5os7OlmXtHsnOoZc 4WNd5oeJ9mbihetNaSTb8Q+bBFNdrHf65oWHpra0= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= , Magnus Kulke , Zhao Liu , Wei Liu , Paolo Bonzini Subject: [PATCH v2 5/7] target/i386/mshv: use the register page to get registers Date: Tue, 5 May 2026 21:50:26 +0300 Message-ID: <20260505185028.237207-6-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260505185028.237207-1-dblanzeanu@linux.microsoft.com> References: <20260505185028.237207-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1778007094393158500 Change the mshv_load_regs to use the register page when it is mmapped and is valid. Otherwise use the existing logic that uses ioctls to fetch registers. When retrieving the special registers, there are some registers that are not present in the register page: TR, LDTR, GDTR, IDTR, CR2, APIC_BASE. As this registers are not likely to be used in an MMIO/PIO operation, and to avoid a hypercall overhead we do not retrieve them. Local testing showed no regression when using this logic. To properly retrieve all the necessary registers for each decoded operation implies having a mechanism that tracks the state of each register, which is beyond the scope of this patch series. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Anirudh Rayabharam (Microsoft) --- target/i386/mshv/mshv-cpu.c | 99 +++++++++++++++++++++++++++++++++---- 1 file changed, 90 insertions(+), 9 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 3a3c269c33..c84d3f76de 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -401,6 +401,80 @@ static void populate_special_regs(const hv_register_as= soc *assocs, cpu_set_apic_base(x86cpu->apic_state, assocs[16].value.reg64); } =20 +static void mshv_get_standard_regs_vp_page(CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + + /* General Purpose Registers */ + env->regs[R_EAX] =3D env->regs_page->rax; + env->regs[R_EBX] =3D env->regs_page->rbx; + env->regs[R_ECX] =3D env->regs_page->rcx; + env->regs[R_EDX] =3D env->regs_page->rdx; + env->regs[R_ESI] =3D env->regs_page->rsi; + env->regs[R_EDI] =3D env->regs_page->rdi; + env->regs[R_ESP] =3D env->regs_page->rsp; + env->regs[R_EBP] =3D env->regs_page->rbp; + env->regs[R_R8] =3D env->regs_page->r8; + env->regs[R_R9] =3D env->regs_page->r9; + env->regs[R_R10] =3D env->regs_page->r10; + env->regs[R_R11] =3D env->regs_page->r11; + env->regs[R_R12] =3D env->regs_page->r12; + env->regs[R_R13] =3D env->regs_page->r13; + env->regs[R_R14] =3D env->regs_page->r14; + env->regs[R_R15] =3D env->regs_page->r15; + + env->eip =3D env->regs_page->rip; + env->eflags =3D env->regs_page->rflags; + rflags_to_lflags(env); +} + +/* + * This function synchronizes the special registers present in the + * register vp page, which are not all the special registers. + * The rest of the special registers (LD, TR, GDT, IDT, CR2, APIC_BASE) + * are not synchronized to avoid the overhead of a hypercall. + * + * These special registers are not normally used by the guest, + * and are only used in some specific cases. + */ +static void mshv_get_special_regs_vp_page(CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + hv_x64_segment_register seg; + + /* Populate special registers that are in the VP register page */ + env->cr[0] =3D env->regs_page->cr0; + env->cr[3] =3D env->regs_page->cr3; + env->cr[4] =3D env->regs_page->cr4; + env->efer =3D env->regs_page->efer; + cpu_set_apic_tpr(x86cpu->apic_state, env->regs_page->cr8); + + /* Segment Registers - copy from packed struct to avoid unaligned acce= ss */ + memcpy(&seg, &env->regs_page->es, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_ES]); + memcpy(&seg, &env->regs_page->cs, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_CS]); + memcpy(&seg, &env->regs_page->ss, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_SS]); + memcpy(&seg, &env->regs_page->ds, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_DS]); + memcpy(&seg, &env->regs_page->fs, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_FS]); + memcpy(&seg, &env->regs_page->gs, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_GS]); +} + +static void mshv_get_registers_vp_page(CPUState *cpu) +{ + /* General Purpose Registers */ + mshv_get_standard_regs_vp_page(cpu); + + /* Special Registers */ + mshv_get_special_regs_vp_page(cpu); +} + =20 int mshv_get_special_regs(CPUState *cpu) { @@ -424,18 +498,25 @@ int mshv_get_special_regs(CPUState *cpu) =20 int mshv_load_regs(CPUState *cpu) { + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; int ret; =20 - ret =3D mshv_get_standard_regs(cpu); - if (ret < 0) { - error_report("Failed to load standard registers"); - return -1; - } + /* Use register vp page to optimize registers access */ + if (env->regs_page && env->regs_page->isvalid !=3D 0) { + mshv_get_registers_vp_page(cpu); + } else { + ret =3D mshv_get_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to load standard registers"); + return -1; + } =20 - ret =3D mshv_get_special_regs(cpu); - if (ret < 0) { - error_report("Failed to load special registers"); - return -1; + ret =3D mshv_get_special_regs(cpu); + if (ret < 0) { + error_report("Failed to load special registers"); + return -1; + } } =20 return 0; --=20 2.53.0 From nobody Tue May 26 20:35:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1778007088; cv=none; d=zohomail.com; s=zohoarc; b=OiutOi7zIwqFYmJ1nPC3SyrQVd8QVSanUopWaaYxIS6y8Qr3xlSx36I5UhE+X/EWVS7ONhKhhlVSdpZiPMMm7qmntbkLOT0cAfhPh7F6oqTai4fNJrNpOF/O+G5vj6Fmvph05dXSRZknsN19n+1dNS1YZ+XY2EzQPF9E0+L9w1c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778007088; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1778007090218154100 Update mshv_store_regs to use the register page when it is mmapped and valid to set registers. Otherwise use the ioctls to set the registers. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Anirudh Rayabharam (Microsoft) --- target/i386/mshv/mshv-cpu.c | 45 +++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index c84d3f76de..0cfac26a5c 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -285,14 +285,51 @@ static int set_standard_regs(const CPUState *cpu) return 0; } =20 +static void mshv_set_standard_regs_vp_page(CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + + env->regs_page->rax =3D env->regs[R_EAX]; + env->regs_page->rbx =3D env->regs[R_EBX]; + env->regs_page->rcx =3D env->regs[R_ECX]; + env->regs_page->rdx =3D env->regs[R_EDX]; + env->regs_page->rsi =3D env->regs[R_ESI]; + env->regs_page->rdi =3D env->regs[R_EDI]; + env->regs_page->rsp =3D env->regs[R_ESP]; + env->regs_page->rbp =3D env->regs[R_EBP]; + env->regs_page->r8 =3D env->regs[R_R8]; + env->regs_page->r9 =3D env->regs[R_R9]; + env->regs_page->r10 =3D env->regs[R_R10]; + env->regs_page->r11 =3D env->regs[R_R11]; + env->regs_page->r12 =3D env->regs[R_R12]; + env->regs_page->r13 =3D env->regs[R_R13]; + env->regs_page->r14 =3D env->regs[R_R14]; + env->regs_page->r15 =3D env->regs[R_R15]; + env->regs_page->rip =3D env->eip; + lflags_to_rflags(env); + env->regs_page->rflags =3D env->eflags; + + env->regs_page->dirty |=3D (1u << HV_X64_REGISTER_CLASS_GENERAL) + | (1u << HV_X64_REGISTER_CLASS_IP) + | (1u << HV_X64_REGISTER_CLASS_FLAGS); +} + int mshv_store_regs(CPUState *cpu) { + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; int ret; =20 - ret =3D set_standard_regs(cpu); - if (ret < 0) { - error_report("Failed to store standard registers"); - return -1; + /* Use register vp page to optimize registers access */ + if (env->regs_page && env->regs_page->isvalid !=3D 0) { + mshv_set_standard_regs_vp_page(cpu); + } else { + ret =3D set_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to store standard registers"); + return -1; + } } =20 return 0; --=20 2.53.0 From nobody Tue May 26 20:35:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1778007119; cv=none; d=zohomail.com; s=zohoarc; b=D8lMkESCqUWwaZHOUuOOfCI5kXarObS8m369JMBail2RfFeHbeXWZ9+JhOGOrtY2Synt685VJxx1wZV0D4/nHhakOkO/KmTywprqHJDjuGbRZwPxTpUFowAJZmHzS5URE7YXdp3AjAQKCBPgPDT/QbBZUK0u70SQANsFlJm3PN4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778007119; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qhK+besfkzswTlnKE72DUmc6HXtjGeutb1TQjNxHTQ8=; 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Tue, 05 May 2026 14:50:54 -0400 Received: from laptop.localdomain (unknown [86.121.140.248]) by linux.microsoft.com (Postfix) with ESMTPSA id 1AB0620B7169; Tue, 5 May 2026 11:50:47 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 1AB0620B7169 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1778007049; bh=qhK+besfkzswTlnKE72DUmc6HXtjGeutb1TQjNxHTQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L6w+FWDEZStU5PC2UWo0ZmO11OTl0XmAt/TGUI9YpdN+nkiwOCmkoTJiuS/4C8wa2 24MyHX46CDDILX5krU6GTPe/tanR33zYDcV+i6WS/wB7Pw8sD4pKvl7IC542ZOB21/ 3NPiPsaYwcZMdm1fe0fEjuWgq7sNOdsmx7GkNP7g= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= , Magnus Kulke , Zhao Liu , Wei Liu , Paolo Bonzini Subject: [PATCH v2 7/7] target/i386/mshv: fix pio handlers clobbering device-modified registers Date: Tue, 5 May 2026 21:50:28 +0300 Message-ID: <20260505185028.237207-8-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260505185028.237207-1-dblanzeanu@linux.microsoft.com> References: <20260505185028.237207-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1778007120146158500 When a device handler (e.g. vmport) calls cpu_synchronize_state() during I/O port dispatch, it sets cpu->accel->dirty =3D true and may modify registers directly in env. The old PIO code ignored this: it unconditionally wrote the stale info->rax from the VM-exit intercept message back to the hypervisor and then cleared dirty, discarding any register changes made by the device. Bifurcate both handlers on cpu->accel->dirty: handle_pio_non_str: - dirty path: update env->eip directly. For reads (IN), merge the I/O result into env->regs[R_EAX] (which may have been modified by the device) rather than info->rax. For writes (OUT), leave RAX untouched. Flush all registers via mshv_store_regs() and clear dirty. - non-dirty path: write RIP and RAX via set_x64_registers hypercall as before. handle_pio_str: - dirty path: update env->eip and the appropriate index register (RSI for OUTS, RDI for INS) directly. Flush via mshv_store_regs() and clear dirty. - non-dirty path: write the index register and RIP via set_x64_registers. Drop the RAX assignment that was here before; string I/O does not modify RAX, and set_x64_registers is hardcoded to write only 2 registers so the third slot was silently ignored anyway. Remove the unconditional "cpu->accel->dirty =3D false" at the end of both handlers. In the non-dirty fast path it was redundant (already false). In the dirty path it was actively harmful: it told the vcpu run loop that env was clean when it was not, losing the device's modifications. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 82 ++++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 23 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 0cfac26a5c..7be3fdcc45 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1348,7 +1348,7 @@ static int pio_write(uint64_t port, const uint8_t *da= ta, uintptr_t size, return ret; } =20 -static int handle_pio_non_str(const CPUState *cpu, +static int handle_pio_non_str(CPUState *cpu, hv_x64_io_port_intercept_message *info) { size_t len =3D info->access_info.access_size; @@ -1357,10 +1357,12 @@ static int handle_pio_non_str(const CPUState *cpu, uint32_t val, eax; const uint32_t eax_mask =3D 0xffffffffu >> (32 - len * 8); size_t insn_len; - uint64_t rip, rax; + uint64_t rip; uint32_t reg_names[2]; uint64_t reg_values[2]; uint16_t port =3D info->port_number; + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; =20 if (access_type =3D=3D HV_X64_INTERCEPT_ACCESS_TYPE_WRITE) { union { @@ -1391,21 +1393,40 @@ static int handle_pio_non_str(const CPUState *cpu, =20 /* Advance RIP and update RAX */ rip =3D info->header.rip + insn_len; - rax =3D info->rax; =20 - reg_names[0] =3D HV_X64_REGISTER_RIP; - reg_values[0] =3D rip; - reg_names[1] =3D HV_X64_REGISTER_RAX; - reg_values[1] =3D rax; + if (cpu->accel->dirty) { + env->eip =3D rip; + if (access_type !=3D HV_X64_INTERCEPT_ACCESS_TYPE_WRITE) { + /* + * For reads, merge the I/O result into the current RAX. + * Use env->regs[R_EAX] as the base since a device handler + * (e.g. vmport) may have called cpu_synchronize_state() + * and modified registers. + */ + eax =3D (((uint32_t)env->regs[R_EAX]) & ~eax_mask) + | (val & eax_mask); + env->regs[R_EAX] =3D (uint64_t)eax; + } + /* Sync modified standard registers back and clear dirty. */ + ret =3D mshv_store_regs(cpu); + if (ret < 0) { + error_report("Failed to store registers after PIO"); + return -1; + } + cpu->accel->dirty =3D false; + } else { + reg_names[0] =3D HV_X64_REGISTER_RIP; + reg_values[0] =3D rip; + reg_names[1] =3D HV_X64_REGISTER_RAX; + reg_values[1] =3D info->rax; =20 - ret =3D set_x64_registers(cpu, reg_names, reg_values); - if (ret < 0) { - error_report("Failed to set x64 registers"); - return -1; + ret =3D set_x64_registers(cpu, reg_names, reg_values); + if (ret < 0) { + error_report("Failed to set x64 registers"); + return -1; + } } =20 - cpu->accel->dirty =3D false; - return 0; } =20 @@ -1521,6 +1542,7 @@ static int handle_pio_str(CPUState *cpu, hv_x64_io_po= rt_intercept_message *info) bool repop =3D info->access_info.rep_prefix =3D=3D 1; size_t repeat =3D repop ? info->rcx : 1; size_t insn_len =3D info->header.instruction_length; + uint64_t rip; bool direction_flag; uint32_t reg_names[3]; uint64_t reg_values[3]; @@ -1554,18 +1576,32 @@ static int handle_pio_str(CPUState *cpu, hv_x64_io_= port_intercept_message *info) reg_values[0] =3D info->rdi; } =20 - reg_names[1] =3D HV_X64_REGISTER_RIP; - reg_values[1] =3D info->header.rip + insn_len; - reg_names[2] =3D HV_X64_REGISTER_RAX; - reg_values[2] =3D info->rax; + rip =3D info->header.rip + insn_len; =20 - ret =3D set_x64_registers(cpu, reg_names, reg_values); - if (ret < 0) { - error_report("Failed to set x64 registers"); - return -1; - } + if (cpu->accel->dirty) { + env->eip =3D rip; + if (access_type =3D=3D HV_X64_INTERCEPT_ACCESS_TYPE_WRITE) { + env->regs[R_ESI] =3D info->rsi; + } else { + env->regs[R_EDI] =3D info->rdi; + } + /* Sync modified standard registers back and clear dirty. */ + ret =3D mshv_store_regs(cpu); + if (ret < 0) { + error_report("Failed to store registers after string PIO"); + return -1; + } + cpu->accel->dirty =3D false; + } else { + reg_names[1] =3D HV_X64_REGISTER_RIP; + reg_values[1] =3D rip; =20 - cpu->accel->dirty =3D false; + ret =3D set_x64_registers(cpu, reg_names, reg_values); + if (ret < 0) { + error_report("Failed to set x64 registers"); + return -1; + } + } =20 return 0; } --=20 2.53.0