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Tue, 05 May 2026 04:20:16 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , kvm@vger.kernel.org, Alexander Graf , Mohamed Mediouni , Paolo Bonzini , Pedro Barbuda , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v5 1/7] target/arm: teach arm_cpu_has_work about halting reasons Date: Tue, 5 May 2026 12:20:07 +0100 Message-ID: <20260505112014.102993-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260505112014.102993-1-alex.bennee@linaro.org> References: <20260505112014.102993-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777980059029158500 With the advent of WFE and WFI we need to pay closer attention to the reason why the vCPU may be sleeping to figure out if we should wake it up. Create env->halt_reason to track this and then re-order the tests so we: - ignore everything is the vCPU is powered off - wake up if the event_register is set and we were in a WFE - otherwise any IRQ event does wake the vCPU up. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- v3 - move arm_set_cpu_power_state to internals.h - drop excess brackets v5 - more arm_set_cpu_power_state cases --- target/arm/cpu.h | 16 +++++++++++++++ target/arm/internals.h | 11 +++++++++++ target/arm/arm-powerctl.c | 6 +++--- target/arm/cpu.c | 40 +++++++++++++++++++++++++++----------- target/arm/kvm.c | 5 +++-- target/arm/machine.c | 2 +- target/arm/tcg/op_helper.c | 3 +++ 7 files changed, 66 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index be14a47c357..357359011cb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -257,6 +257,19 @@ typedef enum ARMFPStatusFlavour { } ARMFPStatusFlavour; #define FPST_COUNT 10 =20 +/** + * ARMHaltReason - the reason we have entered halt state + * + * To be able to correctly wake up via arm_cpu_has_work() we need to + * track the reason we went to sleep. + */ +typedef enum { + NOT_HALTED =3D 0, + HALT_PSCI, + HALT_WFI, + HALT_WFE +} ARMHaltReason; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -760,6 +773,9 @@ typedef struct CPUArchState { /* Optional fault info across tlb lookup. */ ARMMMUFaultInfo *tlb_fi; =20 + /* Reason the CPU is halted */ + ARMHaltReason halt_reason; + /* * The event register is shared by all ARM profiles (A/R/M), * so it is stored in the top-level CPU state. diff --git a/target/arm/internals.h b/target/arm/internals.h index a632584a4e0..4a1ea5465d7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1997,4 +1997,15 @@ bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, = uint64_t kvmidx, ARMCPRegMigToleranceType type); =20 =20 +/** + * arm_set_cpu_power_state() - set power state synced with halt_reason + */ +static inline void arm_set_cpu_power_state(ARMCPU *cpu, ARMPSCIState state) +{ + CPUARMState *env =3D &cpu->env; + + cpu->power_state =3D state; + env->halt_reason =3D state =3D=3D PSCI_OFF ? HALT_PSCI : NOT_HALTED; +} + #endif diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index a788376d1d3..a06be5cc997 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -78,7 +78,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cp= u_state, =20 /* Finally set the power status */ assert(bql_locked()); - target_cpu->power_state =3D PSCI_ON; + arm_set_cpu_power_state(target_cpu, PSCI_ON); } =20 int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id, @@ -186,7 +186,7 @@ static void arm_set_cpu_on_and_reset_async_work(CPUStat= e *target_cpu_state, =20 /* Finally set the power status */ assert(bql_locked()); - target_cpu->power_state =3D PSCI_ON; + arm_set_cpu_power_state(target_cpu, PSCI_ON); } =20 int arm_set_cpu_on_and_reset(uint64_t cpuid) @@ -239,7 +239,7 @@ static void arm_set_cpu_off_async_work(CPUState *target= _cpu_state, ARMCPU *target_cpu =3D ARM_CPU(target_cpu_state); =20 assert(bql_locked()); - target_cpu->power_state =3D PSCI_OFF; + arm_set_cpu_power_state(target_cpu, PSCI_OFF); target_cpu_state->halted =3D 1; target_cpu_state->exception_index =3D EXCP_HLT; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10feb639c4d..fb79981338c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -144,18 +144,36 @@ static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); =20 - if (arm_feature(&cpu->env, ARM_FEATURE_M)) { - if (cpu->env.event_register) { - return true; - } + /* + * Only another PSCI call can wake the CPU up in which case the + * power_state would be set by arm_set_cpu_on_and_reset_async_work() + */ + if (cpu->power_state =3D=3D PSCI_OFF) { + g_assert(cpu->env.halt_reason =3D=3D HALT_PSCI); + return false; + } + + /* + * A wake-up event should only wake us if we are halted on a WFE + */ + if (cpu->env.halt_reason =3D=3D HALT_WFE && cpu->env.event_register) { + cpu->env.halt_reason =3D NOT_HALTED; + return true; + } + + /* + * Otherwise pretty much any IRQ would wake us up + */ + if (cpu_test_interrupt(cs, + CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD + | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU= _INTERRUPT_VFNMI + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU= _INTERRUPT_VSERR + | CPU_INTERRUPT_EXITTB)) { + cpu->env.halt_reason =3D NOT_HALTED; + return true; } =20 - return (cpu->power_state !=3D PSCI_OFF) - && cpu_test_interrupt(cs, - CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_V= FNMI - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_V= SERR - | CPU_INTERRUPT_EXITTB); + return false; } #endif /* !CONFIG_USER_ONLY */ =20 @@ -326,7 +344,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t= ype) env->vfp.xregs[ARM_VFP_MVFR1] =3D cpu->isar.mvfr1; env->vfp.xregs[ARM_VFP_MVFR2] =3D cpu->isar.mvfr2; =20 - cpu->power_state =3D cs->start_powered_off ? PSCI_OFF : PSCI_ON; + arm_set_cpu_power_state(cpu, cs->start_powered_off ? PSCI_OFF : PSCI_O= N); =20 if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 64 bit CPUs always start in 64 bit mode */ diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d4a68874b88..c08e4797b32 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1143,11 +1143,12 @@ static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) if (cap_has_mp_state) { struct kvm_mp_state mp_state; int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); + ARMPSCIState state; if (ret) { return ret; } - cpu->power_state =3D (mp_state.mp_state =3D=3D KVM_MP_STATE_STOPPE= D) ? - PSCI_OFF : PSCI_ON; + state =3D (mp_state.mp_state =3D=3D KVM_MP_STATE_STOPPED) ? PSCI_O= FF : PSCI_ON; + arm_set_cpu_power_state(cpu, state); } return 0; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 8dc766d3225..dbd39e7ba76 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -916,7 +916,7 @@ static int get_power(QEMUFile *f, void *opaque, size_t = size, { ARMCPU *cpu =3D opaque; bool powered_off =3D qemu_get_byte(f); - cpu->power_state =3D powered_off ? PSCI_OFF : PSCI_ON; + arm_set_cpu_power_state(cpu, powered_off ? PSCI_OFF : PSCI_ON); return 0; } =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index e8f0996ed39..504526153a6 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -402,6 +402,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) target_el); } =20 + env->halt_reason =3D HALT_WFI; cs->exception_index =3D EXCP_HLT; cs->halted =3D 1; cpu_loop_exit(cs); @@ -463,6 +464,7 @@ void HELPER(wfit)(CPUARMState *env, uint32_t rd) } else { timer_mod(cpu->wfxt_timer, nexttick); } + env->halt_reason =3D HALT_WFI; cs->exception_index =3D EXCP_HLT; cs->halted =3D 1; cpu_loop_exit(cs); @@ -507,6 +509,7 @@ void HELPER(wfe)(CPUARMState *env) return; } =20 + env->halt_reason =3D HALT_WFE; cs->exception_index =3D EXCP_HLT; cs->halted =3D 1; cpu_loop_exit(cs); --=20 2.47.3 From nobody Sat May 30 13:54:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 05 May 2026 04:20:16 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , kvm@vger.kernel.org, Alexander Graf , Mohamed Mediouni , Paolo Bonzini , Pedro Barbuda , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v5 2/7] target/arm: redefine event stream fields Date: Tue, 5 May 2026 12:20:08 +0100 Message-ID: <20260505112014.102993-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260505112014.102993-1-alex.bennee@linaro.org> References: <20260505112014.102993-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777980054999158500 The event stream control bits are the same for both CNTHCTL and CNTKCTL so rather than duplicating the definitions rename them to be useful in both cases. We will need these in a later commit when we start implementing event streams. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/internals.h | 11 +++++++---- target/arm/helper.c | 8 ++++---- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4a1ea5465d7..24423a200ff 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -269,14 +269,17 @@ FIELD(VSTCR, SA, 30, 1) * have different bit definitions, and EL1PCTEN might be * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to * disambiguate if necessary. + * + * The event stream bits (EVN*) are in the same position for + * CNTKCTL_EL1/CTNKCTL. */ FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1) FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1) FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1) FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1) -FIELD(CNTHCTL, EVNTEN, 2, 1) -FIELD(CNTHCTL, EVNTDIR, 3, 1) -FIELD(CNTHCTL, EVNTI, 4, 4) +FIELD(CNTxCTL, EVNTEN, 2, 1) +FIELD(CNTxCTL, EVNTDIR, 3, 1) +FIELD(CNTxCTL, EVNTI, 4, 4) FIELD(CNTHCTL, EL0VTEN, 8, 1) FIELD(CNTHCTL, EL0PTEN, 9, 1) FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1) @@ -286,7 +289,7 @@ FIELD(CNTHCTL, EL1TVT, 13, 1) FIELD(CNTHCTL, EL1TVCT, 14, 1) FIELD(CNTHCTL, EL1NVPCT, 15, 1) FIELD(CNTHCTL, EL1NVVCT, 16, 1) -FIELD(CNTHCTL, EVNTIS, 17, 1) +FIELD(CNTxCTL, EVNTIS, 17, 1) FIELD(CNTHCTL, CNTVMASK, 18, 1) FIELD(CNTHCTL, CNTPMASK, 19, 1) =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e7677a584d..dfdb77a9fe2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1746,9 +1746,9 @@ static void gt_cnthctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, uint32_t valid_mask =3D R_CNTHCTL_EL0PCTEN_E2H1_MASK | R_CNTHCTL_EL0VCTEN_E2H1_MASK | - R_CNTHCTL_EVNTEN_MASK | - R_CNTHCTL_EVNTDIR_MASK | - R_CNTHCTL_EVNTI_MASK | + R_CNTxCTL_EVNTEN_MASK | + R_CNTxCTL_EVNTDIR_MASK | + R_CNTxCTL_EVNTI_MASK | R_CNTHCTL_EL0VTEN_MASK | R_CNTHCTL_EL0PTEN_MASK | R_CNTHCTL_EL1PCTEN_E2H1_MASK | @@ -1763,7 +1763,7 @@ static void gt_cnthctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, R_CNTHCTL_EL1TVCT_MASK | R_CNTHCTL_EL1NVPCT_MASK | R_CNTHCTL_EL1NVVCT_MASK | - R_CNTHCTL_EVNTIS_MASK; + R_CNTxCTL_EVNTIS_MASK; } if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D R_CNTHCTL_ECV_MASK; --=20 2.47.3 From nobody Sat May 30 13:54:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777980064; cv=none; d=zohomail.com; s=zohoarc; b=VOJsfHjCgy7E4sPDGi7mdr72Im3q/lf4gV91DvGKLDOYM3/Yj+mmuX4MXvTE0q2BQX+Atzp+kl5S7DT2w8tVAlZ46zZ1QSu8INfSvE1xtPTiO7xZ9zuEFm0hPwA8z4XC9OzRSav2/mS6r9a5ynh+HwbTKp+EOGMeoBpQ6FYmTSA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777980064; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 05 May 2026 04:20:17 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , kvm@vger.kernel.org, Alexander Graf , Mohamed Mediouni , Paolo Bonzini , Pedro Barbuda , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v5 3/7] target/arm: ensure aarch64 DISAS_WFE will exit Date: Tue, 5 May 2026 12:20:09 +0100 Message-ID: <20260505112014.102993-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260505112014.102993-1-alex.bennee@linaro.org> References: <20260505112014.102993-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777980065216158501 This mirrors the logic for DISAS_WFE in 32 bit world. As the WFE/WFI have similar behaviours shuffle the case statements around a little and update the commentary to cover both. Fixes: 252ec405768 (target-arm: implement WFE/YIELD as a yield for AArch64) Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- v4 - shuffle case statements, unify the comments. --- target/arm/tcg/translate-a64.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 9a27c4c6ec7..25f0a806512 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10916,25 +10916,25 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) case DISAS_NORETURN: case DISAS_SWI: break; - case DISAS_WFE: - gen_a64_update_pc(dc, 4); - gen_helper_wfe(tcg_env); - break; case DISAS_YIELD: gen_a64_update_pc(dc, 4); gen_helper_yield(tcg_env); break; + /* + * Both WFE/WFI can cause exceptions or exit the loop to + * halt so we have to make sure we have rectified the PC. + * However they can also return directly if they don't + * enter a wait state so we must add an exit block so we exit + * the loop and check for interrupts. + */ + case DISAS_WFE: + gen_a64_update_pc(dc, 4); + gen_helper_wfe(tcg_env); + tcg_gen_exit_tb(NULL, 0); + break; case DISAS_WFI: - /* - * This is a special case because we don't want to just halt - * the CPU if trying to debug across a WFI. - */ gen_a64_update_pc(dc, 4); gen_helper_wfi(tcg_env, tcg_constant_i32(4)); - /* - * The helper doesn't necessarily throw an exception, but we - * must go back to the main loop to check for interrupts anywa= y. - */ tcg_gen_exit_tb(NULL, 0); break; } --=20 2.47.3 From nobody Sat May 30 13:54:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777980047; cv=none; d=zohomail.com; s=zohoarc; b=IJguoaIyII4D5njXJ22qqQdB/MCR+vFIzGrqb8EPtSYcPfYNmA6pE3Q4Px9Zd6ciktRUSu1T761rLlcCUmDSQaQYKQuRl76TL6j/VHBWBTekWnczV39rYpFTTPqP/zzJPFfikk5q3xlmuaR1iHF00aPlThbkVN+iipS9WZxj/ys= ARC-Message-Signature: i=1; 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Tue, 05 May 2026 04:20:18 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , kvm@vger.kernel.org, Alexander Graf , Mohamed Mediouni , Paolo Bonzini , Pedro Barbuda , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v5 4/7] target/arm: implements SEV/SEVL for all modes Date: Tue, 5 May 2026 12:20:10 +0100 Message-ID: <20260505112014.102993-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260505112014.102993-1-alex.bennee@linaro.org> References: <20260505112014.102993-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777980049413158500 Remove the restrictions that make this a M-profile only operation and enable the instructions for all Arm profiles. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- v2 - fix alignment in a32.decode - set bool directly, defend with QEMU_BUILD_BUG_ON - s/instructions/profiles/ - share get_event_reg between translate/translate-a64 --- target/arm/tcg/translate.h | 18 ++++++++++++++++++ target/arm/tcg/a32.decode | 5 ++--- target/arm/tcg/a64.decode | 5 ++--- target/arm/tcg/t16.decode | 4 +--- target/arm/tcg/t32.decode | 4 +--- target/arm/tcg/op_helper.c | 4 +--- target/arm/tcg/translate-a64.c | 17 +++++++++++++++++ target/arm/tcg/translate.c | 13 ++++++++----- 8 files changed, 50 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 77fdc5f3a17..340848793d4 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -854,6 +854,24 @@ static inline void gen_restore_rmode(TCGv_i32 old, TCG= v_ptr fpst) gen_helper_set_rmode(old, old, fpst); } =20 +/* + * Event Register signalling. + * + * A bunch of activities trigger events, we just need to latch on to + * true. The event eventually gets consumed by WFE/WFET. + * + * user-mode treats these as NOPs. + */ + +static inline void gen_event_reg(void) +{ +#ifndef CONFIG_USER_ONLY + TCGv_i32 set_event =3D tcg_constant_i32(1); + QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, event_register) !=3D 1); + tcg_gen_st8_i32(set_event, tcg_env, offsetof(CPUARMState, event_regist= er)); +#endif +} + /* * Helpers for implementing sets of trans_* functions. * Defer the implementation of NAME to FUNC, with optional extra arguments. diff --git a/target/arm/tcg/a32.decode b/target/arm/tcg/a32.decode index f2ca4809495..547aa2b1490 100644 --- a/target/arm/tcg/a32.decode +++ b/target/arm/tcg/a32.decode @@ -192,9 +192,8 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ...= . @rd0mn WFE ---- 0011 0010 0000 1111 ---- 0000 0010 WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 =20 ESB ---- 0011 0010 0000 1111 ---- 0001 0000 ] diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 01b1b3e38be..dcb3099dd5c 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -237,9 +237,8 @@ ERETA 1101011 0100 11111 00001 m:1 11111 1111= 1 &reta # ERETAA, ERETAB YIELD 1101 0101 0000 0011 0010 0000 001 11111 WFE 1101 0101 0000 0011 0010 0000 010 11111 WFI 1101 0101 0000 0011 0010 0000 011 11111 - # We implement WFE to never block, so our SEV/SEVL are NOPs - # SEV 1101 0101 0000 0011 0010 0000 100 11111 - # SEVL 1101 0101 0000 0011 0010 0000 101 11111 + SEV 1101 0101 0000 0011 0010 0000 100 11111 + SEVL 1101 0101 0000 0011 0010 0000 101 11111 # Our DGL is a NOP because we don't merge memory accesses anyway. # DGL 1101 0101 0000 0011 0010 0000 110 11111 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 diff --git a/target/arm/tcg/t16.decode b/target/arm/tcg/t16.decode index 778fbf16275..9a8f89538ac 100644 --- a/target/arm/tcg/t16.decode +++ b/target/arm/tcg/t16.decode @@ -228,10 +228,8 @@ REVSH 1011 1010 11 ... ... @rdm WFE 1011 1111 0010 0000 WFI 1011 1111 0011 0000 =20 - # M-profile SEV is implemented. - # TODO: Implement SEV for other profiles, and SEVL for all profiles; m= ay help SMP performance. SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + SEVL 1011 1111 0101 0000 =20 # The canonical nop has the second nibble as 0000, but the whole of the # rest of the space is a reserved hint, behaves as nop. diff --git a/target/arm/tcg/t32.decode b/target/arm/tcg/t32.decode index 49b8d0037ec..8ae277fe112 100644 --- a/target/arm/tcg/t32.decode +++ b/target/arm/tcg/t32.decode @@ -369,10 +369,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm WFE 1111 0011 1010 1111 1000 0000 0000 0010 WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # M-profile SEV is implemented. - # TODO: Implement SEV for other profiles, and SEVL for all profile= s; may help SMP performance. SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 ESB 1111 0011 1010 1111 1000 0000 0001 0000 ] diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 504526153a6..2b1fb1e059d 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -476,9 +476,7 @@ void HELPER(sev)(CPUARMState *env) CPUState *cs =3D env_cpu(env); CPU_FOREACH(cs) { ARMCPU *target_cpu =3D ARM_CPU(cs); - if (arm_feature(&target_cpu->env, ARM_FEATURE_M)) { - target_cpu->env.event_register =3D true; - } + target_cpu->env.event_register =3D true; if (!qemu_cpu_is_self(cs)) { qemu_cpu_kick(cs); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 25f0a806512..07014717316 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2033,6 +2033,23 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_SEV(DisasContext *s, arg_SEV *a) +{ + /* + * SEV is a NOP for user-mode emulation. + */ +#ifndef CONFIG_USER_ONLY + gen_helper_sev(tcg_env); +#endif + return true; +} + +static bool trans_SEVL(DisasContext *s, arg_SEV *a) +{ + gen_event_reg(); + return true; +} + static bool trans_WFE(DisasContext *s, arg_WFI *a) { /* diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index ce427c5a3ca..50d0184e84e 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3246,17 +3246,20 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD = *a) static bool trans_SEV(DisasContext *s, arg_SEV *a) { /* - * Currently SEV is a NOP for non-M-profile and in user-mode emulation. - * For system-mode M-profile, it sets the event register. + * SEV is a NOP for user-mode emulation. */ #ifndef CONFIG_USER_ONLY - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_helper_sev(tcg_env); - } + gen_helper_sev(tcg_env); #endif return true; } =20 +static bool trans_SEVL(DisasContext *s, arg_SEV *a) +{ + gen_event_reg(); + return true; +} + static bool trans_WFE(DisasContext *s, arg_WFE *a) { /* --=20 2.47.3 From nobody Sat May 30 13:54:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 05 May 2026 04:20:19 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , kvm@vger.kernel.org, Alexander Graf , Mohamed Mediouni , Paolo Bonzini , Pedro Barbuda , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v5 5/7] target/arm: enable event stream on WFE instructions Date: Tue, 5 May 2026 12:20:11 +0100 Message-ID: <20260505112014.102993-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260505112014.102993-1-alex.bennee@linaro.org> References: <20260505112014.102993-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777980111572154100 Two generic timers (K and H) are capable of generating timer event stream events. Provide a helper to calculate when the nearest one will happen. Now we can calculate when the next event stream event is we can re-use the wfxt_timer and configure it to fire as we enter a WFE that is going to sleep. Reverse the M-profile logic so we can enter a sleep state in both profiles. To avoid issues with QEMU's incomplete ldst exclusive handling causing potential deadlocks in common WFE enabled locking patterns we take advantage of the architectures flexibility and treat being in the exclusive region as a reason to exit. Signed-off-by: Alex Benn=C3=A9e --- v2 - merged target/arm: add gt_calc_next_event_stream - update to use halt_reason - made arm_wfxt_timer_cb atomically consume halt_reason v4 - skip sleep if in the exclusive region - update commit message - remove the CF_PARALLEL guards so we work in smp v5 - use env_archcpu for ARMCPU rather then expensive QOM cast - rely on cpu->wfxt_timer to guard event stream leg --- target/arm/cpu.c | 13 +++ target/arm/tcg/op_helper.c | 145 ++++++++++++++++++++++++++++----- target/arm/tcg/translate-a64.c | 10 +-- target/arm/tcg/translate.c | 16 +--- 4 files changed, 142 insertions(+), 42 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fb79981338c..a23b7e87495 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -875,10 +875,23 @@ bool arm_cpu_exec_halt(CPUState *cs) } #endif =20 +/* + * Unlike almost everything else that messes with the halt_reason and + * event_register details the timer callbacks are not in the vCPU + * context. + * + * To prevent races we atomically consume a HALT_WFE and set the event + * register. Either way we trigger the an exit event. + */ static void arm_wfxt_timer_cb(void *opaque) { ARMCPU *cpu =3D opaque; CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + + if (qatomic_cmpxchg(&env->halt_reason, HALT_WFE, NOT_HALTED)) { + qatomic_set(&env->event_register, true); + } =20 /* * We expect the CPU to be halted; this will cause arm_cpu_is_work() diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 2b1fb1e059d..8284dacbdf6 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -483,6 +483,97 @@ void HELPER(sev)(CPUARMState *env) } } =20 +#ifndef CONFIG_USER_ONLY +/* + * Event Stream events don't do anything apart from wake up sleeping + * cores. These helpers calculate the next event stream event time so + * the WFE helper can decide when its next wake up tick will be. + */ +static int64_t gt_recalc_one_evt(CPUARMState *env, uint32_t control, uint6= 4_t offset) +{ + ARMCPU *cpu =3D env_archcpu(env); + bool evnten =3D FIELD_EX32(control, CNTxCTL, EVNTEN); + + if (evnten) { + int evnti =3D FIELD_EX32(control, CNTxCTL, EVNTI); + bool evntis =3D FIELD_EX32(control, CNTxCTL, EVNTIS); + bool evntdir =3D FIELD_EX32(control, CNTxCTL, EVNTDIR); + /* + * To figure out when the next event timer should fire we need + * to calculate which bit of the counter we want to flip and + * which transition counts. + * + * So we calculate 1 << bit - current lower bits and then add + * 1 << bit if the bit needs to flip twice to meet evntdir + */ + int bit =3D evntis ? evnti + 8 : evnti; + uint64_t count =3D gt_get_countervalue(env) - offset; + uint64_t target_bit =3D BIT_ULL(bit); + uint64_t lower_bits =3D MAKE_64BIT_MASK(0, bit - 1); + uint64_t next_tick =3D target_bit - (count & lower_bits); + uint64_t abstick; + + /* do we need to bit flip twice? */ + if (((count & target_bit) !=3D 0) ^ evntdir) { + next_tick +=3D target_bit; + } + + /* + * Note that the desired next expiry time might be beyond the + * signed-64-bit range of a QEMUTimer -- in this case we just + * set the timer for as far in the future as possible. When the + * timer expires we will reset the timer for any remaining period. + */ + if (uadd64_overflow(next_tick, offset, &abstick)) { + abstick =3D UINT64_MAX; + } + if (abstick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { + return INT64_MAX; + } else { + return abstick; + } + } + + return -1; +} + +/* + * Calculate the next event stream time and return it. Returns -1 if + * no event streams are enabled. It is up to the WFE helpers to decide + * on the next time. + */ +static int64_t gt_calc_next_event_stream(CPUARMState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint64_t hcr =3D arm_hcr_el2_eff(env); + int64_t next_time =3D -1; + uint64_t offset; + + /* Unless we are missing EL2 this can generate events */ + if (arm_feature(env, ARM_FEATURE_EL2)) { + offset =3D gt_direct_access_timer_offset(env, GTIMER_PHYS); + next_time =3D gt_recalc_one_evt(env, env->cp15.cnthctl_el2, offset= ); + } + + /* Event stream events from virtual counter enabled? */ + if (!cpu_isar_feature(aa64_vh, cpu) || + !((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE))) { + int64_t next_virt_time; + offset =3D gt_direct_access_timer_offset(env, GTIMER_VIRT); + next_virt_time =3D gt_recalc_one_evt(env, env->cp15.c14_cntkctl, o= ffset); + + /* is this earlier than the next physical event? */ + if (next_virt_time > 0) { + if (next_time < 0 || next_virt_time < next_time) { + next_time =3D next_virt_time; + } + } + } + + return next_time; +} +#endif + void HELPER(wfe)(CPUARMState *env) { #ifdef CONFIG_USER_ONLY @@ -495,32 +586,46 @@ void HELPER(wfe)(CPUARMState *env) #else /* * WFE (Wait For Event) is a hint instruction. - * For Cortex-M (M-profile), we implement the strict architectural beh= avior: + * * 1. Check the Event Register (set by SEV or SEVONPEND). * 2. If set, clear it and continue (consume the event). */ - if (arm_feature(env, ARM_FEATURE_M)) { - CPUState *cs =3D env_cpu(env); + CPUState *cs =3D env_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); + uint32_t excp; + int target_el =3D check_wfx_trap(env, true, &excp); =20 - if (env->event_register) { - env->event_register =3D false; - return; - } + if (env->event_register) { + env->event_register =3D false; + return; + } =20 - env->halt_reason =3D HALT_WFE; - cs->exception_index =3D EXCP_HLT; - cs->halted =3D 1; - cpu_loop_exit(cs); - } else { - /* - * For A-profile and others, we rely on the existing "yield" behav= ior. - * Don't actually halt the CPU, just yield back to top - * level loop. This is not going into a "low power state" - * (ie halting until some event occurs), so we never take - * a configurable trap to a different exception level - */ - HELPER(yield)(env); + /* + * If the CPU has entered the exclusive region we could sleep + * until the global monitor moves from Exclusive to Open Access. + * However it would be expensive for QEMU to fully model the + * global monitor and not doing so would potentially trigger + * deadlocks in WFE enabled locking code. However as WFE is a hint + * instruction the architecture allows for the PE to leave + * low-power state for any reason. QEMU chooses to treat being in + * an exclusive region as such and return directly. + */ + if (env->exclusive_addr !=3D -1) { + return; } + + /* For A-profile we also can be woken by the event stream */ + if (cpu->wfxt_timer) { + int64_t next_event =3D gt_calc_next_event_stream(env); + if (next_event > 0) { + timer_mod(cpu->wfxt_timer, next_event); + } + } + + env->halt_reason =3D HALT_WFE; + cs->exception_index =3D EXCP_HLT; + cs->halted =3D 1; + cpu_loop_exit(cs); #endif } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 07014717316..8b97136e78b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2052,15 +2052,7 @@ static bool trans_SEVL(DisasContext *s, arg_SEV *a) =20 static bool trans_WFE(DisasContext *s, arg_WFI *a) { - /* - * When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_WFE; - } + s->base.is_jmp =3D DISAS_WFE; return true; } =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 50d0184e84e..3ab49887ce6 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3262,19 +3262,9 @@ static bool trans_SEVL(DisasContext *s, arg_SEV *a) =20 static bool trans_WFE(DisasContext *s, arg_WFE *a) { - /* - * When running single-threaded TCG code, use the helper to ensure that - * the next round-robin scheduled vCPU gets a crack. - * - * For Cortex-M, we implement the architectural WFE behavior (sleeping - * until an event occurs or the Event Register is set). - * For other profiles, we currently treat this as a NOP or yield, - * to preserve existing performance characteristics. - */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_update_pc(s, curr_insn_len(s)); - s->base.is_jmp =3D DISAS_WFE; - } + /* For WFE, halt the vCPU until an event. */ + gen_update_pc(s, curr_insn_len(s)); + s->base.is_jmp =3D DISAS_WFE; return true; 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Tue, 05 May 2026 04:20:20 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , kvm@vger.kernel.org, Alexander Graf , Mohamed Mediouni , Paolo Bonzini , Pedro Barbuda , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v5 6/7] target/arm: handle the WFE trap case Date: Tue, 5 May 2026 12:20:12 +0100 Message-ID: <20260505112014.102993-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260505112014.102993-1-alex.bennee@linaro.org> References: <20260505112014.102993-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777980058928158500 Now WFE can actually suspend on A-profile we also need to handle when its trapped. To do this we need to pass the instruction size so we can deal with the is_16bit syndrome encoding. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/helper-defs.h | 2 +- target/arm/tcg/op_helper.c | 13 ++++++++++++- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 2 +- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index a05f2258f29..ebdf09be38a 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -54,7 +54,7 @@ DEF_HELPER_2(exception_swstep, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) -DEF_HELPER_1(wfe, void, env) +DEF_HELPER_2(wfe, void, env, i32) DEF_HELPER_2(wfit, void, env, i32) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 8284dacbdf6..1349bcc7929 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -574,7 +574,7 @@ static int64_t gt_calc_next_event_stream(CPUARMState *e= nv) } #endif =20 -void HELPER(wfe)(CPUARMState *env) +void HELPER(wfe)(CPUARMState *env, uint32_t insn_len) { #ifdef CONFIG_USER_ONLY /* @@ -600,6 +600,17 @@ void HELPER(wfe)(CPUARMState *env) return; } =20 + /* We might sleep, so now we check to see if we should trap */ + if (target_el) { + if (env->aarch64) { + env->pc -=3D insn_len; + } else { + env->regs[15] -=3D insn_len; + } + raise_exception(env, excp, syn_wfx(1, 0xe, 0, false, WFE, insn_len= =3D=3D 2), + target_el); + } + /* * If the CPU has entered the exclusive region we could sleep * until the global monitor moves from Exclusive to Open Access. diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8b97136e78b..a6f392a28f8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10938,7 +10938,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) */ case DISAS_WFE: gen_a64_update_pc(dc, 4); - gen_helper_wfe(tcg_env); + gen_helper_wfe(tcg_env, tcg_constant_i32(4)); tcg_gen_exit_tb(NULL, 0); break; case DISAS_WFI: diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 3ab49887ce6..686980b58e3 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -6836,7 +6836,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) tcg_gen_exit_tb(NULL, 0); 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Tue, 05 May 2026 04:20:19 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , kvm@vger.kernel.org, Alexander Graf , Mohamed Mediouni , Paolo Bonzini , Pedro Barbuda , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v5 7/7] target/arm: implement WFET Date: Tue, 5 May 2026 12:20:13 +0100 Message-ID: <20260505112014.102993-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260505112014.102993-1-alex.bennee@linaro.org> References: <20260505112014.102993-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777980115418154100 Now we have the event stream and SEV/SEVL implemented we can finally enable WFET for Aarch64. To avoid issues with QEMU's incomplete ldst exclusive handling causing potential deadlocks in common WFE enabled locking patterns we take advantage of the architectures flexibility and treat being in the exclusive region as a reason to exit. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- v2 - fix exception syndrome by using enum value - use env->halt_reason v3 - fix check_wfx_trap(s/false/true/) as it is a WFE v4 - defer expensive calculations until needed - treat cs->exclusive_addr as a IMPDEF WFE exit - update commit message --- target/arm/tcg/helper-defs.h | 1 + target/arm/tcg/op_helper.c | 95 ++++++++++++++++++++++++++++++++++ target/arm/tcg/translate-a64.c | 15 +++--- 3 files changed, 104 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index ebdf09be38a..5e4d828dd55 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -56,6 +56,7 @@ DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_2(wfe, void, env, i32) DEF_HELPER_2(wfit, void, env, i32) +DEF_HELPER_2(wfet, void, env, i32) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 1349bcc7929..d8d7557b880 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -640,6 +640,101 @@ void HELPER(wfe)(CPUARMState *env, uint32_t insn_len) #endif } =20 +void HELPER(wfet)(CPUARMState *env, uint32_t rd) +{ +#ifdef CONFIG_USER_ONLY + /* + * As for WFIT make it NOP here, because trying to raise EXCP_HLT + * would trigger an abort. + */ + return; +#else + CPUState *cs =3D env_cpu(env); + uint32_t excp; + int target_el; + ARMCPU *cpu; + uint64_t cntval, timeout, offset, cntvct, nexttick; + int64_t next_event; + + /* + * As for WFE if the event register is already set we can consume + * the event and return immediately. + */ + if (env->event_register) { + env->event_register =3D false; + return; + } + + /* + * Don't bother to go into our "low power state" if + * we would just wake up immediately. + * + * We want the value that we would get if we read CNTVCT_EL0 from + * the current exception level, so the direct_access offset, not + * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(), + * which calls VirtualCounterTimer(). + */ + cntval =3D gt_get_countervalue(env); + offset =3D gt_direct_access_timer_offset(env, GTIMER_VIRT); + cntvct =3D cntval - offset; + timeout =3D env->xregs[rd]; + if (cpu_has_work(cs) || cntvct >=3D timeout) { + return; + } + + /* We might sleep, so now we check to see if we should trap */ + target_el =3D check_wfx_trap(env, true, &excp); + if (target_el) { + env->pc -=3D 4; + raise_exception(env, excp, syn_wfx(1, 0xe, rd, true, WFET, false),= target_el); + } + + /* + * If the CPU has entered the exclusive region we could sleep + * until the global monitor moves from Exclusive to Open Access. + * However it would be expensive for QEMU to fully model the + * global monitor and not doing so would potentially trigger + * deadlocks in WFE enabled locking code. However as WFE is a hint + * instruction the architecture allows for the PE to leave + * low-power state for any reason. QEMU chooses to treat being in + * an exclusive region as such and return directly. + */ + if (env->exclusive_addr !=3D -1) { + return; + } + + /* + * Finally work out if the timeout or event stream will kick in + * earlier. + * + * The WFET should time out when CNTVCT_EL0 >=3D the specified value. + */ + cpu =3D env_archcpu(env); + if (uadd64_overflow(timeout, offset, &nexttick)) { + nexttick =3D UINT64_MAX; + } + if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { + nexttick =3D INT64_MAX; + } + + next_event =3D gt_calc_next_event_stream(env); + if (next_event > 0 && next_event < nexttick) { + timer_mod(cpu->wfxt_timer, next_event); + } else { + if (nexttick =3D=3D INT64_MAX) { + timer_mod_ns(cpu->wfxt_timer, INT64_MAX); + } else { + timer_mod(cpu->wfxt_timer, nexttick); + } + } + + env->halt_reason =3D HALT_WFE; + cs->exception_index =3D EXCP_HLT; + cs->halted =3D 1; + cpu_loop_exit(cs); +#endif +} + void HELPER(yield)(CPUARMState *env) { CPUState *cs =3D env_cpu(env); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a6f392a28f8..ead2a7ff81f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2086,14 +2086,15 @@ static bool trans_WFET(DisasContext *s, arg_WFET *a) return false; } =20 - /* - * We rely here on our WFE implementation being a NOP, so we - * don't need to do anything different to handle the WFET timeout - * from what trans_WFE does. - */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_WFE; + if (s->ss_active) { + /* Act like a NOP under architectural singlestep */ + return true; } + + gen_a64_update_pc(s, 4); + gen_helper_wfet(tcg_env, tcg_constant_i32(a->rd)); + /* Go back to the main loop to check for interrupts */ + s->base.is_jmp =3D DISAS_EXIT; return true; } =20 --=20 2.47.3