From nobody Sat May 30 19:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777546014; cv=none; d=zohomail.com; s=zohoarc; b=A3juAHTN6dmMy5jTxwCVWfuqlW6pyGGcxevMRHbG8Ryw8aEnMM4IWvNxzg3x4PSWVAGcAChlvxF1/JZ/LTxBYs+lUir0gbBOkNR2chjVAnTMR5Y5WpRGLhs8P75V9Rfl+QQGGoymW+vtHs3UbdEy9W0heJSTa4JQ3V5QDNpLC+w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777546014; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oXkCjDNNed+tdCztqK2sYupZhfXPPqZLJxXlVw3UrqI=; b=ju6B5ZuFcA5VZxqcZnqgYR+yphzBHOD+DDejexVpI0uZh9nOdXvdITDbh9Xg7A3kC+5aDCeCz+313siKFHfRxbBSSZNvDfoB+JjTNcjp8KhDwL0k9/mP1Ri1akyHDJdUdLzbWxy9fZrXbRLDZkQaSdWEoOWO8w6XACaJedKvnz0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777546014046276.397065070689; Thu, 30 Apr 2026 03:46:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wIOt3-0008K7-Ih; Thu, 30 Apr 2026 06:44:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wIOsw-0008GY-RK for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:49 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wIOst-0005Jp-HZ for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:46 -0400 Received: by mail-wr1-x441.google.com with SMTP id ffacd0b85a97d-43d73422431so685375f8f.2 for ; Thu, 30 Apr 2026 03:44:38 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-448af0fa81esm7222907f8f.19.2026.04.30.03.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 03:44:35 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id DD4785F92A; Thu, 30 Apr 2026 11:44:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777545877; x=1778150677; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oXkCjDNNed+tdCztqK2sYupZhfXPPqZLJxXlVw3UrqI=; b=a16HYuUZ3/Y0hcc30+I65qrgP/ti5Wb72t4SOWwu2hsCJAbZi0eFP/wBSyQ8s7hqB0 FEPXCL5jN0fvRHM4G5BTrjTbi1Xe7t3BpDlPEsgHOJng5Dho6Uwjm31kGgpg1YXmM/d/ OcPNv2hGtySdTXaODrfypTNngFnZxvHBiJ+oc+eoJo9Z9hW3poeplIjOWxB2dP/Ur0/P ERZTx2IzcPULXJVj2dgmUz9UEYNN1SklwZenEpOanNWvxvH6P9CGKllI4qZjy9VAbrJ5 LF+rOTdRAjU6IrO/0WSbiTp5Pkx0OfzFmdVdmkwfTbt7bS61PvrXEsjePFAQBIEItJBm As9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777545877; x=1778150677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=oXkCjDNNed+tdCztqK2sYupZhfXPPqZLJxXlVw3UrqI=; b=SvIjIHdkavmHNNRYxifIp+E5+jw2BV9ThbtdDWr2YpIcVi7ROWrTLXFx4LBYFC++5P 7hGbnWokAgXPgv4WmC/gd4k7CitWlo9JonmiFcmpz2N9P9V2aPPKOOrZywSibkCIC+KY pTpcqY3x4L6fIEs6BTt77nkDYRnFJ0/0EJDP42tnJxtYUiWnG6CXj+XF17RbRnH+xuuL 9geEaIreQmpme9MLJswIVExbQyMNwnT9OXA6UVYl4bSeRZGXt07W94ENieBbq/vVt/kv +RL4j88xKfmEMdwSCwGx3sZkwVWzaCwMWpfLK26XlmkQjpIpdOILCO0K7oZZyij2S9v8 liBA== X-Gm-Message-State: AOJu0YxBjp6grn2AEcZzLLMXPFY37hz6kJivNaPM8fF3RmDXn4Qj2+YK MmXND1RAPmEke2/D456KoDNTpjvxmgCVq5hYpk0YSJmF8ecH7FF0inp77hLcT4CiRP0= X-Gm-Gg: AeBDievhlcEzpoGOo4NRuUjW7WAFkO5Gwh1Cvm/xDLXQMqI/M0L3Myje3iZwYDWC8WS Icgo0+9NLURJDD48qcTXf+tlOgMkZYYILYnNuqwkYGry/DBU2dMmJshnkPv3Tk1Jr7IpUL0NtJW 06KcaB4pN6PkZ9J7iDVLP98Lzux1t48A0Zfz/IkFJ6o3/wRe8Z+IeMeSNdPQmQAsoBGVKbPEW8L hmZVlNC8LTKiJedOGYHeGSeWjVeDT2BB/elDLm9dQP3uhnfZfbbPQdNQNlRMiCCGyd1Md8tG4tj cYU/vKsfqb4imb4xrutvq8zyGKzBHcDMYh2RZ3LPlPtkH5HZTUlyowMUo/EkXszsR0ZgXBwGplu KVB28ASlCRUfYzPDEd1fmhDGGtp0tc3l7nnacHa2l8XJ1V7PUVqtz9IiSr/Fhi9M3nKhh3FI7Ds +T2Ig8/4qd82zz8eNicQN8NDDSj4CCwGBG+Q== X-Received: by 2002:a05:6000:24c5:b0:43f:e452:f391 with SMTP id ffacd0b85a97d-4493cb42f83mr4018286f8f.6.1777545876542; Thu, 30 Apr 2026 03:44:36 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Mohamed Mediouni , qemu-arm@nongnu.org, Pedro Barbuda , Peter Maydell , Paolo Bonzini , kvm@vger.kernel.org, Alexander Graf , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v4 1/7] target/arm: teach arm_cpu_has_work about halting reasons Date: Thu, 30 Apr 2026 11:44:28 +0100 Message-ID: <20260430104434.1482407-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260430104434.1482407-1-alex.bennee@linaro.org> References: <20260430104434.1482407-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777546014867158500 With the advent of WFE and WFI we need to pay closer attention to the reason why the vCPU may be sleeping to figure out if we should wake it up. Create env->halt_reason to track this and then re-order the tests so we: - ignore everything is the vCPU is powered off - wake up if the event_register is set and we were in a WFE - otherwise any IRQ event does wake the vCPU up. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - move arm_set_cpu_power_state to internals.h - drop excess brackets --- target/arm/cpu.h | 16 +++++++++++++++ target/arm/internals.h | 11 +++++++++++ target/arm/arm-powerctl.c | 4 +++- target/arm/cpu.c | 40 +++++++++++++++++++++++++++----------- target/arm/kvm.c | 5 +++-- target/arm/machine.c | 2 +- target/arm/tcg/op_helper.c | 3 +++ 7 files changed, 66 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index be14a47c357..357359011cb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -257,6 +257,19 @@ typedef enum ARMFPStatusFlavour { } ARMFPStatusFlavour; #define FPST_COUNT 10 =20 +/** + * ARMHaltReason - the reason we have entered halt state + * + * To be able to correctly wake up via arm_cpu_has_work() we need to + * track the reason we went to sleep. + */ +typedef enum { + NOT_HALTED =3D 0, + HALT_PSCI, + HALT_WFI, + HALT_WFE +} ARMHaltReason; + typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; @@ -760,6 +773,9 @@ typedef struct CPUArchState { /* Optional fault info across tlb lookup. */ ARMMMUFaultInfo *tlb_fi; =20 + /* Reason the CPU is halted */ + ARMHaltReason halt_reason; + /* * The event register is shared by all ARM profiles (A/R/M), * so it is stored in the top-level CPU state. diff --git a/target/arm/internals.h b/target/arm/internals.h index a632584a4e0..4a1ea5465d7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1997,4 +1997,15 @@ bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, = uint64_t kvmidx, ARMCPRegMigToleranceType type); =20 =20 +/** + * arm_set_cpu_power_state() - set power state synced with halt_reason + */ +static inline void arm_set_cpu_power_state(ARMCPU *cpu, ARMPSCIState state) +{ + CPUARMState *env =3D &cpu->env; + + cpu->power_state =3D state; + env->halt_reason =3D state =3D=3D PSCI_OFF ? HALT_PSCI : NOT_HALTED; +} + #endif diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index a788376d1d3..4ca63a54443 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -78,6 +78,7 @@ static void arm_set_cpu_on_async_work(CPUState *target_cp= u_state, =20 /* Finally set the power status */ assert(bql_locked()); + target_cpu->env.halt_reason =3D NOT_HALTED; target_cpu->power_state =3D PSCI_ON; } =20 @@ -186,6 +187,7 @@ static void arm_set_cpu_on_and_reset_async_work(CPUStat= e *target_cpu_state, =20 /* Finally set the power status */ assert(bql_locked()); + target_cpu->env.halt_reason =3D NOT_HALTED; target_cpu->power_state =3D PSCI_ON; } =20 @@ -239,7 +241,7 @@ static void arm_set_cpu_off_async_work(CPUState *target= _cpu_state, ARMCPU *target_cpu =3D ARM_CPU(target_cpu_state); =20 assert(bql_locked()); - target_cpu->power_state =3D PSCI_OFF; + arm_set_cpu_power_state(target_cpu, PSCI_OFF); target_cpu_state->halted =3D 1; target_cpu_state->exception_index =3D EXCP_HLT; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10feb639c4d..fb79981338c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -144,18 +144,36 @@ static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); =20 - if (arm_feature(&cpu->env, ARM_FEATURE_M)) { - if (cpu->env.event_register) { - return true; - } + /* + * Only another PSCI call can wake the CPU up in which case the + * power_state would be set by arm_set_cpu_on_and_reset_async_work() + */ + if (cpu->power_state =3D=3D PSCI_OFF) { + g_assert(cpu->env.halt_reason =3D=3D HALT_PSCI); + return false; + } + + /* + * A wake-up event should only wake us if we are halted on a WFE + */ + if (cpu->env.halt_reason =3D=3D HALT_WFE && cpu->env.event_register) { + cpu->env.halt_reason =3D NOT_HALTED; + return true; + } + + /* + * Otherwise pretty much any IRQ would wake us up + */ + if (cpu_test_interrupt(cs, + CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD + | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU= _INTERRUPT_VFNMI + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU= _INTERRUPT_VSERR + | CPU_INTERRUPT_EXITTB)) { + cpu->env.halt_reason =3D NOT_HALTED; + return true; } =20 - return (cpu->power_state !=3D PSCI_OFF) - && cpu_test_interrupt(cs, - CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_V= FNMI - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_V= SERR - | CPU_INTERRUPT_EXITTB); + return false; } #endif /* !CONFIG_USER_ONLY */ =20 @@ -326,7 +344,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t= ype) env->vfp.xregs[ARM_VFP_MVFR1] =3D cpu->isar.mvfr1; env->vfp.xregs[ARM_VFP_MVFR2] =3D cpu->isar.mvfr2; =20 - cpu->power_state =3D cs->start_powered_off ? PSCI_OFF : PSCI_ON; + arm_set_cpu_power_state(cpu, cs->start_powered_off ? PSCI_OFF : PSCI_O= N); =20 if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 64 bit CPUs always start in 64 bit mode */ diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d4a68874b88..c08e4797b32 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1143,11 +1143,12 @@ static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) if (cap_has_mp_state) { struct kvm_mp_state mp_state; int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); + ARMPSCIState state; if (ret) { return ret; } - cpu->power_state =3D (mp_state.mp_state =3D=3D KVM_MP_STATE_STOPPE= D) ? - PSCI_OFF : PSCI_ON; + state =3D (mp_state.mp_state =3D=3D KVM_MP_STATE_STOPPED) ? PSCI_O= FF : PSCI_ON; + arm_set_cpu_power_state(cpu, state); } return 0; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 8dc766d3225..dbd39e7ba76 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -916,7 +916,7 @@ static int get_power(QEMUFile *f, void *opaque, size_t = size, { ARMCPU *cpu =3D opaque; bool powered_off =3D qemu_get_byte(f); - cpu->power_state =3D powered_off ? PSCI_OFF : PSCI_ON; + arm_set_cpu_power_state(cpu, powered_off ? PSCI_OFF : PSCI_ON); return 0; } =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index e8f0996ed39..504526153a6 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -402,6 +402,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) target_el); } =20 + env->halt_reason =3D HALT_WFI; cs->exception_index =3D EXCP_HLT; cs->halted =3D 1; cpu_loop_exit(cs); @@ -463,6 +464,7 @@ void HELPER(wfit)(CPUARMState *env, uint32_t rd) } else { timer_mod(cpu->wfxt_timer, nexttick); } + env->halt_reason =3D HALT_WFI; cs->exception_index =3D EXCP_HLT; cs->halted =3D 1; cpu_loop_exit(cs); @@ -507,6 +509,7 @@ void HELPER(wfe)(CPUARMState *env) return; } =20 + env->halt_reason =3D HALT_WFE; cs->exception_index =3D EXCP_HLT; cs->halted =3D 1; cpu_loop_exit(cs); --=20 2.47.3 From nobody Sat May 30 19:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777545959; cv=none; d=zohomail.com; s=zohoarc; b=QdvuODP0Gh7YCGEVvkE5VTZezN6b13L9teiTIalVnQvRq8Gsb1HVsk7kCpd9qz9uccS4nSi2t9/XmNVCUjeeB9vhrH2aNsLf0VOSGpJkhr3kEmW2jAfAGBSNr+qBGd26IlOCdcmAfsDUpD5cnRklWkbLSHR04TyYHm90+LPxnl4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777545959; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RsPS9jH4wqzZMo8K63vD2xS0qPk68eIqWMM62PQ4Kyc=; b=DLQQ9GaEV+n2H/zLyPDO9lp2Q/R4jMTRgAB9acR3gG5E5YSJYG4QcM6GFHQE98Tfu5ZWN+GmIb7Pclbn/wSqLlBVpuPFxcR6MNqZMtPA6MA+3k1T1ardiU9v9arx1e1gkwQcBW3KHUPNCwb6areh4UjvPpXzSXKAF86ytAvdcS4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777545959314223.62011101207668; Thu, 30 Apr 2026 03:45:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wIOt8-0008N4-9K; Thu, 30 Apr 2026 06:44:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wIOsy-0008Gh-90 for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:49 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wIOsu-0005KK-70 for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:47 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-488d2079582so7547175e9.2 for ; Thu, 30 Apr 2026 03:44:39 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a7b912869sm40905485e9.6.2026.04.30.03.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 03:44:35 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id F21705F932; Thu, 30 Apr 2026 11:44:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777545878; x=1778150678; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RsPS9jH4wqzZMo8K63vD2xS0qPk68eIqWMM62PQ4Kyc=; b=GkYLoU7RzlX2y+q+NIgdbpvcvv1mse7E7j+W+kTbYrygyVEsy52tupqqaQORYxTsK7 tBL9SvROXHArEZW5wz7ipCfQCCbWQTLHW+Ir14kcyoDVIxSm9ph75bb6MWZFlINCMupo jETcsXOpEWQ2MSvYVwZdZmXYqOxh4/Yo0+v/9ve0s13WgmzOALup2vPHQ6D+JPFXCA51 oWFroQZtSCwtYJqC7ZQ0udybSftv0aHmrnLNxrVM4xg50NETlb6DJxJGSzzciPpOGPNw HVJ27uK+ncv7DxHbgZidU4uRGlqwzzOSB49kWJ6+jJBm/C6tvh3fv4RlDQzrqcmzeR1R 9QzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777545878; x=1778150678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=RsPS9jH4wqzZMo8K63vD2xS0qPk68eIqWMM62PQ4Kyc=; b=GKAsTwovmPhEmGKuvWXk2pD8iCr7BZRRNVzj864Vy3rlyJNd0i+64Qlrsru7yZ0bMe Dm6Tqlo57suMTHu5x8Zq/q8P9O6hTdTesHmBdgd1boxjomW59MXZyEjTJDSlq4+UZwZF vW6b56vHN3Wz9SwXbr8vEsz5nH0us2Ae9FgH1+vR0t4baCD4TpMJ1qymzJZlV+4cHdPI 9BgHO0omdZ1z/oQYSVM/6nWHrmnzdsrSLY34yW+RzJKxUxkjJe0wR6vN966UPc6WJj4l DXSH/kKNiHI/5fD8KZf6TZMd8P2plnpBGA0eG1UyNL7k1euavxtkFN0tclqBpQt5KfqN 9T7g== X-Gm-Message-State: AOJu0YwZYiuq9189bycak4IY94Q55aVzTyS+3oolK6EjFp55Twyo6iml 7qa3Ls/ToNhR/E1s7LxlF/094qwu70q8w45kN3GEOCwK+f9pzxg9wroeKSnc89esUxs= X-Gm-Gg: AeBDiet0R1Bq+lp7epZqgHcPBrI30heIZ8DWdb/BmiZbCEAyQz9lGOzSDCxkAm3/SeL XYVP8ikxqL+8pAyImuvAHKHk6bvk3YeiyeBxr2xpbTYRZ+MPDF+R9xDV+ofdHLNreVJ0vHR1X52 ocfZkVWBLxinasleB/cm2lA3NnsCF1bnQnXBFJA+qEIAlD1Gm1GIpWRIu5dGS57iJXhYJLGDhKn ubHf7JcrI17sPzleo19Ts4Mb9xvLfacVt/7nN8NcbjfryCKA28BVTpCh7+Mb0d1dkLfB5AUByUw 0WYhfbe4YQqx0hM92gX1jZsOOfiujnotNlegKG8AdubrNVI6vyVarvloW7TpLBvvqln6Ue8JeQK QDQe4eY6QrSf7dARC1eqhs9zpzRMhlLbX5WW+kwCEQZhNkvZYg42QESmEHOvjhxrDD0uMuAE9xZ NSIo3Jp6poBg7fKTI+CbDnI1DLi7FzVzAJ3A== X-Received: by 2002:a05:600c:45d4:b0:488:90ac:8f71 with SMTP id 5b1f17b1804b1-48a83d66cd4mr33804835e9.5.1777545878132; Thu, 30 Apr 2026 03:44:38 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Mohamed Mediouni , qemu-arm@nongnu.org, Pedro Barbuda , Peter Maydell , Paolo Bonzini , kvm@vger.kernel.org, Alexander Graf , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v4 2/7] target/arm: redefine event stream fields Date: Thu, 30 Apr 2026 11:44:29 +0100 Message-ID: <20260430104434.1482407-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260430104434.1482407-1-alex.bennee@linaro.org> References: <20260430104434.1482407-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777545961900154100 The event stream control bits are the same for both CNTHCTL and CNTKCTL so rather than duplicating the definitions rename them to be useful in both cases. We will need these in a later commit when we start implementing event streams. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/internals.h | 11 +++++++---- target/arm/helper.c | 8 ++++---- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4a1ea5465d7..24423a200ff 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -269,14 +269,17 @@ FIELD(VSTCR, SA, 30, 1) * have different bit definitions, and EL1PCTEN might be * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to * disambiguate if necessary. + * + * The event stream bits (EVN*) are in the same position for + * CNTKCTL_EL1/CTNKCTL. */ FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1) FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1) FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1) FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1) -FIELD(CNTHCTL, EVNTEN, 2, 1) -FIELD(CNTHCTL, EVNTDIR, 3, 1) -FIELD(CNTHCTL, EVNTI, 4, 4) +FIELD(CNTxCTL, EVNTEN, 2, 1) +FIELD(CNTxCTL, EVNTDIR, 3, 1) +FIELD(CNTxCTL, EVNTI, 4, 4) FIELD(CNTHCTL, EL0VTEN, 8, 1) FIELD(CNTHCTL, EL0PTEN, 9, 1) FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1) @@ -286,7 +289,7 @@ FIELD(CNTHCTL, EL1TVT, 13, 1) FIELD(CNTHCTL, EL1TVCT, 14, 1) FIELD(CNTHCTL, EL1NVPCT, 15, 1) FIELD(CNTHCTL, EL1NVVCT, 16, 1) -FIELD(CNTHCTL, EVNTIS, 17, 1) +FIELD(CNTxCTL, EVNTIS, 17, 1) FIELD(CNTHCTL, CNTVMASK, 18, 1) FIELD(CNTHCTL, CNTPMASK, 19, 1) =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e7677a584d..dfdb77a9fe2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1746,9 +1746,9 @@ static void gt_cnthctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, uint32_t valid_mask =3D R_CNTHCTL_EL0PCTEN_E2H1_MASK | R_CNTHCTL_EL0VCTEN_E2H1_MASK | - R_CNTHCTL_EVNTEN_MASK | - R_CNTHCTL_EVNTDIR_MASK | - R_CNTHCTL_EVNTI_MASK | + R_CNTxCTL_EVNTEN_MASK | + R_CNTxCTL_EVNTDIR_MASK | + R_CNTxCTL_EVNTI_MASK | R_CNTHCTL_EL0VTEN_MASK | R_CNTHCTL_EL0PTEN_MASK | R_CNTHCTL_EL1PCTEN_E2H1_MASK | @@ -1763,7 +1763,7 @@ static void gt_cnthctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, R_CNTHCTL_EL1TVCT_MASK | R_CNTHCTL_EL1NVPCT_MASK | R_CNTHCTL_EL1NVVCT_MASK | - R_CNTHCTL_EVNTIS_MASK; + R_CNTxCTL_EVNTIS_MASK; } if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D R_CNTHCTL_ECV_MASK; --=20 2.47.3 From nobody Sat May 30 19:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777545969; cv=none; d=zohomail.com; s=zohoarc; b=d4FnBvR1qVOYJkAYpZi1SzUVJWMT6W8riQC0jTJHw8n9mZWwIWB0ZyR/S6+Jyy3G8JzuBGGt9ehKVLxvT4ZzslN5B0UecsC7FfkDrHl3LFyV1qtqr1C99qu7mXgTohILJLyFX22rYitNC86bmrSoeDiWjQCcZZ8z+igckwCN8E8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777545969; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SJ3nvH0CdgnQGuiZq72mX6EJh1rauF0iDM3crLBhnzQ=; b=TX3IM71xs6U5sNqx+Pn1X7lmScuG1LiIFzc7csYPJSDhpf+Ob9mqcSuoB6eEFAPSdhuTj8GWX0eJLtakEhAPPEp/5AHeKWlf2tuH6A2cUBKHnhtf0U7QpWEfIbeUFtc0FTFtAPVdT31hab0euewvvP8SZqVkGdLjKtWc3EAHsOc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777545969523722.0222135831845; Thu, 30 Apr 2026 03:46:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wIOt6-0008LS-FE; Thu, 30 Apr 2026 06:44:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wIOsz-0008Gn-2A for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:49 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wIOsu-0005Kc-FP for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:48 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4891f625344so8408665e9.0 for ; Thu, 30 Apr 2026 03:44:40 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a7c32afb0sm38448105e9.35.2026.04.30.03.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 03:44:37 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 127B05F936; Thu, 30 Apr 2026 11:44:35 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777545880; x=1778150680; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SJ3nvH0CdgnQGuiZq72mX6EJh1rauF0iDM3crLBhnzQ=; b=opQ0Qhr8U7i0zeF5HOBl/YX5tgVYLyyzcu4C0IZMkx9KSFP3VI90sHq53DxOXIFbmC MGkeuF8o3q29iYKyVQo/feoznCkuKyKspX2OIowe+GvgyY5wAPELSFjAF8fG1rep8szO CaeHTwmA8Pu1Qs+BmCaqbIEjTJbVFR+HIx/XUMCKogaDfMoar0PoIF94/zv7tQmeR6FU mZWe0lEQSD3XF4c6Bo9Dyd6Jl4l9QovAf48BSXg3VchXK+w5H1edBG75K0nklRPZMrhF 4+88nekxPbaw2ugnUHI2qR5GdHA9m6fyf+jxK1blsV/NfpRcK6KhUpDweGyhL6MpUj7h qViQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777545880; x=1778150680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=SJ3nvH0CdgnQGuiZq72mX6EJh1rauF0iDM3crLBhnzQ=; b=VoseQZlPkZM9VXFjXzHdl5xwG+m89ng3JM6nXRlpWG79CRhvv0f6KJD1g/zOmXKtWJ kSox80YHs7FroKR7EXUSzazzpUXxCsYCCJ6wGKiQN/dZ+OUQm1bqwGAJcXdv08r/orsf 1vJgVmdk1VDwQSbHgaSbz9OML+TJODVCQ1qjq2Jki2U9316xQ/7Hv3NVBeURTiPFC7HE hVq3zzGziWltJ0vvOvMw7qtECq/YmptulNlBE5tIghz8ePg8xmTqFebkt5FYayULa9Sx tsQ3zAPW3ohOyfW2yViFqW5lkFBP1g9r2ZLpL6HIUarAsJbiC69mEJc/uNy7ELUEvNk+ kp+g== X-Gm-Message-State: AOJu0YwGRp3yBLm01pajG9Z0BS6D9G2xtJUeot+DFwOI2xXDiaEVw3bC 9NNoiw5k3v55e+79+Eb9RXDp6Rf5qPRivM662cVSZ0JACQ/gsbUUDiNdz382lnereKo= X-Gm-Gg: AeBDieuzFalv2xzrh9uO1hlWBNVMfTT7hyR/s7qk2YviZzEu4cVFN7QMFCRgEMV+3gO jhIjXmxmSZrzH3GID1rtEoyabKBBVuanPQMCF8tMj/LNJFZrypAvbN/TCmiEiX40Xf4Cj2AXkK1 065FCfB4NOMsHFVc1V8q6vauTltrr4kRTGod8JNRl1ww2Dhn6H/lt5FKw5Hv3FP8+0kfjlyTlkO WdyyrRFR7/YEETRTHauxmg6npqhgK9+ma5e+lOB22dStU+zAUWydopicP60tOBdZBO9wMfx/Llx N6YV7t+nbhKcdSPCMEmvvNPl0Z5RJEgEMQyslNUeHlk65tWM72fluu+vE1Yky9a6GNEqh4cFZZH DklY/2Xje5HkyGxQUXGTCnkb/SNcJVaomhwsC65Sth/HaRpcaKBBhMUI2msnIlzqgBZOLQuMC0w HkcokRuvKf2RdzLhxPS/asNY4Vs8IhnHtLng== X-Received: by 2002:a05:600c:8707:b0:489:1baf:8c03 with SMTP id 5b1f17b1804b1-48a86084573mr36555495e9.11.1777545879496; Thu, 30 Apr 2026 03:44:39 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Mohamed Mediouni , qemu-arm@nongnu.org, Pedro Barbuda , Peter Maydell , Paolo Bonzini , kvm@vger.kernel.org, Alexander Graf , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH v4 3/7] target/arm: ensure aarch64 DISAS_WFE will exit Date: Thu, 30 Apr 2026 11:44:30 +0100 Message-ID: <20260430104434.1482407-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260430104434.1482407-1-alex.bennee@linaro.org> References: <20260430104434.1482407-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777545970843158500 This mirrors the logic for DISAS_WFE in 32 bit world. As the WFE/WFI have similar behaviours shuffle the case statements around a little and update the commentary to cover both. Fixes: 252ec405768 (target-arm: implement WFE/YIELD as a yield for AArch64) Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- v4 - shuffle case statements, unify the comments. --- target/arm/tcg/translate-a64.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 9a27c4c6ec7..25f0a806512 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10916,25 +10916,25 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) case DISAS_NORETURN: case DISAS_SWI: break; - case DISAS_WFE: - gen_a64_update_pc(dc, 4); - gen_helper_wfe(tcg_env); - break; case DISAS_YIELD: gen_a64_update_pc(dc, 4); gen_helper_yield(tcg_env); break; + /* + * Both WFE/WFI can cause exceptions or exit the loop to + * halt so we have to make sure we have rectified the PC. + * However they can also return directly if they don't + * enter a wait state so we must add an exit block so we exit + * the loop and check for interrupts. + */ + case DISAS_WFE: + gen_a64_update_pc(dc, 4); + gen_helper_wfe(tcg_env); + tcg_gen_exit_tb(NULL, 0); + break; case DISAS_WFI: - /* - * This is a special case because we don't want to just halt - * the CPU if trying to debug across a WFI. - */ gen_a64_update_pc(dc, 4); gen_helper_wfi(tcg_env, tcg_constant_i32(4)); - /* - * The helper doesn't necessarily throw an exception, but we - * must go back to the main loop to check for interrupts anywa= y. - */ tcg_gen_exit_tb(NULL, 0); break; } --=20 2.47.3 From nobody Sat May 30 19:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777545922; cv=none; d=zohomail.com; s=zohoarc; b=AAdKkO4mLGmWi5CkkntLrbIjdv0W2TgxRA4i67902slp5zrmrIuCeBI/+iCxF8udLmFJnNqAVnTCVxutmYrS0PAn5gLHMbDLCoR36oaaD61MBDwV7tl2DI5Ron0TfnalUJMjd9TGzAFavhL559euDseS+FxGRdqxv9LqOw4TcuQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777545922; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=79oNSzazrmD/SxlRhRbJhCodKfa86P0QEATN+wnG5EA=; b=C0+yUR1KbZFNO3+xvcDHYp4r+Hr6BIft80+mTKB7Ksk5Yg2Gb2V0TAyYvzN1cxcxz6lhrCMj+tZrtdbY9RdgzoNkMOeIQBpGfx2SyP7nHpnpdpLvsm6ZQojIWnb4IB4BZyXXs1THXzTu246+UEJWpAI7P+Ogm1uk9YdTxXSBzLE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777545922810836.5646010099498; Thu, 30 Apr 2026 03:45:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wIOt9-0008O6-Ak; Thu, 30 Apr 2026 06:44:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wIOt0-0008H5-IM for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:51 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wIOsu-0005KU-Fs for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:50 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4893940bb5eso4454265e9.3 for ; Thu, 30 Apr 2026 03:44:40 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a7c2fb999sm57693735e9.6.2026.04.30.03.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 03:44:37 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 2EF7B5F93C; Thu, 30 Apr 2026 11:44:35 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777545879; x=1778150679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=79oNSzazrmD/SxlRhRbJhCodKfa86P0QEATN+wnG5EA=; b=iEDEtUBcc3dpwF5dVcfSzie8szrOzc0XhMB2fJk0NbGlrvbL4tmRPE/Xbd2T5crHJU 1Wx3FGhVnUQ/vwrXqQ6cslTK80dZtlmsGyuzp/KRqdEjHsQ2oDlPyncZAzMqYdN89cuO 5G39q9eqcoFJgvK+SQXAJDn5C5w2EjH+wt/W5Z0PS2evO9kDY0Q9kysmBX5LDN70skFa T4CjSmyfjVx/40MfUZwlGhsddEpmRqXs6OUdLXJRsKuWW1+axTt+h1p9+/BiE3JD9OiH hx/aL7LWJ+h2AifmFeZKwAe1sgVHeBmW6CS8KAdKRZrlzO17hpGCoQ7FAKprQMN9X8Q8 KJ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777545879; x=1778150679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=79oNSzazrmD/SxlRhRbJhCodKfa86P0QEATN+wnG5EA=; b=nTpXMS1c2V3zOvWPOkBowVnhaHBco/H3c6bhsKFRYksHn8JiSvLC66Gs3a+f/DrVaI bE1k399ZHa7VY/8ufStX1LpPX5GeVsWVifH3U396rBbsksjWI6ysGUtW8mCybgIv8IW5 ptq5rbdF80ATh9xbX3EGGK5EiCvuHtyu3+pVjwxI5BD1+Fz1am2NH8+fXkeyHIrrUc4h srnJWFOyAQ+v+3KwifjJDmV46jeUSKROTYdYr3by1o9xCsTIK2Hv81cYzOQ2Me90ld5W tBw8DuKUaCa4xp45uLYMEPliyVVWIvtUPMhx5XN6TaoGqqM1CFUshhOtzgi13KRByJkP t7wA== X-Gm-Message-State: AOJu0YwZY93L7TxE4KqiK0dm1o26q5mVAQsbo2bMFXI+5L0JDlj8eahr JHDhlC0sa5cxMh7s9oDM2c/R2OCaX6cviR8WolMWc8h7WVJ1WAeVYqNrYnDE8agZAG8= X-Gm-Gg: AeBDievvo6ZayZ/DGeq3lFJl7fHkKAmMRB9kWj5VLe+3Bn+mkaHIETm8czA/OfTbUsy VZRBgAV9Xq1yUeYez0EQhM51Jdx7kyv5WoDC1THHeLbNbLPEcaj2L38b7rvdGbx8sDyauJ7q8Ny y5hDK+RIDrhVKpV43eLv5O3Um0UXEMf24U+irBbM2RKfMkgETi2xEp1ckbCfeulrUOODvfJ0Azr qrw7Fwn13Z6Y2d8uFrw1jE7R27vuRfOmKw/5KMdCDBXPgZ6tK1p9itFisL6xNR2E/kOZ8dj0nYd LVRcztyMkUKOoe234lbCXbz6X3vJp3c65T5pg/iFR/ZPQ7+Q2PdMZYRummL6d7+96lEW0bTPwrk 1laiz7tplz0MhDC4vrq3XN/QCaYfTknzrb8UvtfrF/YlvAvVmdyCS4+I5m3G9rkCUHVb0q/ScYK IFLr3rPIfrjqSjqGWA8WUGCsRp76nu2gDx0g== X-Received: by 2002:a05:600c:4e46:b0:488:d243:8da9 with SMTP id 5b1f17b1804b1-48a844e49e3mr39845665e9.1.1777545878718; Thu, 30 Apr 2026 03:44:38 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Mohamed Mediouni , qemu-arm@nongnu.org, Pedro Barbuda , Peter Maydell , Paolo Bonzini , kvm@vger.kernel.org, Alexander Graf , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v4 4/7] target/arm: implements SEV/SEVL for all modes Date: Thu, 30 Apr 2026 11:44:31 +0100 Message-ID: <20260430104434.1482407-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260430104434.1482407-1-alex.bennee@linaro.org> References: <20260430104434.1482407-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777545925110158500 Remove the restrictions that make this a M-profile only operation and enable the instructions for all Arm profiles. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - fix alignment in a32.decode - set bool directly, defend with QEMU_BUILD_BUG_ON - s/instructions/profiles/ - share get_event_reg between translate/translate-a64 --- target/arm/tcg/translate.h | 18 ++++++++++++++++++ target/arm/tcg/a32.decode | 5 ++--- target/arm/tcg/a64.decode | 5 ++--- target/arm/tcg/t16.decode | 4 +--- target/arm/tcg/t32.decode | 4 +--- target/arm/tcg/op_helper.c | 4 +--- target/arm/tcg/translate-a64.c | 17 +++++++++++++++++ target/arm/tcg/translate.c | 13 ++++++++----- 8 files changed, 50 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 77fdc5f3a17..340848793d4 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -854,6 +854,24 @@ static inline void gen_restore_rmode(TCGv_i32 old, TCG= v_ptr fpst) gen_helper_set_rmode(old, old, fpst); } =20 +/* + * Event Register signalling. + * + * A bunch of activities trigger events, we just need to latch on to + * true. The event eventually gets consumed by WFE/WFET. + * + * user-mode treats these as NOPs. + */ + +static inline void gen_event_reg(void) +{ +#ifndef CONFIG_USER_ONLY + TCGv_i32 set_event =3D tcg_constant_i32(1); + QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, event_register) !=3D 1); + tcg_gen_st8_i32(set_event, tcg_env, offsetof(CPUARMState, event_regist= er)); +#endif +} + /* * Helpers for implementing sets of trans_* functions. * Defer the implementation of NAME to FUNC, with optional extra arguments. diff --git a/target/arm/tcg/a32.decode b/target/arm/tcg/a32.decode index f2ca4809495..547aa2b1490 100644 --- a/target/arm/tcg/a32.decode +++ b/target/arm/tcg/a32.decode @@ -192,9 +192,8 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ...= . @rd0mn WFE ---- 0011 0010 0000 1111 ---- 0000 0010 WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 =20 ESB ---- 0011 0010 0000 1111 ---- 0001 0000 ] diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 01b1b3e38be..dcb3099dd5c 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -237,9 +237,8 @@ ERETA 1101011 0100 11111 00001 m:1 11111 1111= 1 &reta # ERETAA, ERETAB YIELD 1101 0101 0000 0011 0010 0000 001 11111 WFE 1101 0101 0000 0011 0010 0000 010 11111 WFI 1101 0101 0000 0011 0010 0000 011 11111 - # We implement WFE to never block, so our SEV/SEVL are NOPs - # SEV 1101 0101 0000 0011 0010 0000 100 11111 - # SEVL 1101 0101 0000 0011 0010 0000 101 11111 + SEV 1101 0101 0000 0011 0010 0000 100 11111 + SEVL 1101 0101 0000 0011 0010 0000 101 11111 # Our DGL is a NOP because we don't merge memory accesses anyway. # DGL 1101 0101 0000 0011 0010 0000 110 11111 XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 diff --git a/target/arm/tcg/t16.decode b/target/arm/tcg/t16.decode index 778fbf16275..9a8f89538ac 100644 --- a/target/arm/tcg/t16.decode +++ b/target/arm/tcg/t16.decode @@ -228,10 +228,8 @@ REVSH 1011 1010 11 ... ... @rdm WFE 1011 1111 0010 0000 WFI 1011 1111 0011 0000 =20 - # M-profile SEV is implemented. - # TODO: Implement SEV for other profiles, and SEVL for all profiles; m= ay help SMP performance. SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + SEVL 1011 1111 0101 0000 =20 # The canonical nop has the second nibble as 0000, but the whole of the # rest of the space is a reserved hint, behaves as nop. diff --git a/target/arm/tcg/t32.decode b/target/arm/tcg/t32.decode index 49b8d0037ec..8ae277fe112 100644 --- a/target/arm/tcg/t32.decode +++ b/target/arm/tcg/t32.decode @@ -369,10 +369,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm WFE 1111 0011 1010 1111 1000 0000 0000 0010 WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # M-profile SEV is implemented. - # TODO: Implement SEV for other profiles, and SEVL for all profile= s; may help SMP performance. SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 ESB 1111 0011 1010 1111 1000 0000 0001 0000 ] diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 504526153a6..2b1fb1e059d 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -476,9 +476,7 @@ void HELPER(sev)(CPUARMState *env) CPUState *cs =3D env_cpu(env); CPU_FOREACH(cs) { ARMCPU *target_cpu =3D ARM_CPU(cs); - if (arm_feature(&target_cpu->env, ARM_FEATURE_M)) { - target_cpu->env.event_register =3D true; - } + target_cpu->env.event_register =3D true; if (!qemu_cpu_is_self(cs)) { qemu_cpu_kick(cs); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 25f0a806512..07014717316 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2033,6 +2033,23 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_SEV(DisasContext *s, arg_SEV *a) +{ + /* + * SEV is a NOP for user-mode emulation. + */ +#ifndef CONFIG_USER_ONLY + gen_helper_sev(tcg_env); +#endif + return true; +} + +static bool trans_SEVL(DisasContext *s, arg_SEV *a) +{ + gen_event_reg(); + return true; +} + static bool trans_WFE(DisasContext *s, arg_WFI *a) { /* diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index ce427c5a3ca..50d0184e84e 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3246,17 +3246,20 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD = *a) static bool trans_SEV(DisasContext *s, arg_SEV *a) { /* - * Currently SEV is a NOP for non-M-profile and in user-mode emulation. - * For system-mode M-profile, it sets the event register. + * SEV is a NOP for user-mode emulation. */ #ifndef CONFIG_USER_ONLY - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_helper_sev(tcg_env); - } + gen_helper_sev(tcg_env); #endif return true; } =20 +static bool trans_SEVL(DisasContext *s, arg_SEV *a) +{ + gen_event_reg(); + return true; +} + static bool trans_WFE(DisasContext *s, arg_WFE *a) { /* --=20 2.47.3 From nobody Sat May 30 19:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777545936; cv=none; d=zohomail.com; s=zohoarc; b=Fy7jmem13H0/KSneQULc0Yi3NN3yoPfMmsL2ApzlA6Hk12dDvIGIEgVQpZDJRbvEqxwKF0TBCQq2OXIMXIOnI+gSPJFthKtEXDnNryNZWk+zNVUGsPELcR9OkIbz6hqSaTHJfqKlTyGJufy/y1o2AudIV5J9S5wWf9W66gVpbsE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777545936; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MsEsn1YZYtVVUa13L2AGk1G4k+OQISTqb0SX28KGc3A=; b=VkZKM5ZsUtb6BW64p+Y1ZrAGnKH1I5f7adUWRIZ9V1VJNF+9HtlBXfQhTmxjBDljaV/MgUfLt3DraEn+oKHDWH0YBtC+Jnk5bwNSEMt3xf9BLzY30A3megXTFL3xhPrKG02RCqHsIOAeQlQjJiEwKwekDCow1m/mqXYvCtKEVpg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777545935959573.7138077547713; Thu, 30 Apr 2026 03:45:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wIOt6-0008LF-Fy; Thu, 30 Apr 2026 06:44:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wIOsz-0008Gq-75 for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:49 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wIOsu-0005Kt-7U for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:48 -0400 Received: by mail-wm1-x343.google.com with SMTP id 5b1f17b1804b1-488a88aeec9so7582165e9.2 for ; Thu, 30 Apr 2026 03:44:41 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a7c2fb999sm57694655e9.6.2026.04.30.03.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 03:44:38 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 494B35F941; Thu, 30 Apr 2026 11:44:35 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777545880; x=1778150680; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MsEsn1YZYtVVUa13L2AGk1G4k+OQISTqb0SX28KGc3A=; b=NYTAp05LPSdt9J8f0dKimOS0DBlBFpfgnUnzrS2JpXhzM0Xi/UzWQGHamfNTr5uCvB 85cuHxweWfrR0lWjsP1Xz//d6v8VS2dPeBXWqqSf/FzeqIyQWO2dpn45d4/eRmu9xVzd +aCRdAFil3fBy+Id7HxPE/QZs/RjrrTOKzradVEfdsMMh1TKKgBedqvvtd59kddnpiw0 qOtpaE8X1Lh5ThnDa74b2yy6R1N33brRnIJ7jpNFxHgCHiFYXjANInDe2ThEu0g3WE71 T9mdTL1ZnAt/1DVQ/vDlKwCVd6AmZupWQDx6eP0MCm7AzqQM+fGvul7zBD5SIF8ExQGz sXoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777545880; x=1778150680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=MsEsn1YZYtVVUa13L2AGk1G4k+OQISTqb0SX28KGc3A=; b=IExRrg91mxXyd7xoLv7ew5OsPlRs20U/lyLk7Vi+yfKacJBntDfY9Dx5nrMBq4gwPv JpFHUgVWkG/X5RsuViuQE6CCOXK0LVFqrdfM+8t5WMrms/rWMlecVoWytGf91l8Y/vAm tvVTcuyIXDPTMYG7UVXTs+qXTr+o91uy0o+IX5yEVGawt0rJNQC5bAeHIcqBJFW4VdVE TCAVpVEVXa0GDw4QbDd9c7uB+DcAKX1miiyF5sEUY1JlkDBx3iCuLYMkVKeN3XvuBikr BdIjgn0E4rcFVXWcZlgnVx4PgJR9oeOX35uiJsnwgIf++YxINQvS4IHWCUqQCKdp4l0n PO+g== X-Gm-Message-State: AOJu0YxOZUZWoVUVVXpSvTd0lN3dsTafM3Qiiv3B59+m5bK+IqZL05Eo o/3Et2PZG7zQuOfhwc4ULt0eQAoEXMkyDsDWsuLvVetoeHBqOMxK+Yk9VjviqGzXoKc= X-Gm-Gg: AeBDieu0eGpop4GryB2w0Ys3+xB0BpVlfSsH0u9ZKCN5VQzuvZMMbtDy8QwCTrrOD0g 5bXnOOXk7gnTY0UevHzRk1SVpVeieoN4BZ/N4mW1ASuRm/9SkcYP8sXOvd2B7cSni2+LeqWFHu2 QrYi0CtbLgUA0zgo1cnqzS3bzpPwehdTsc1+4T+kq9b7cMuADA7oYg+mh3Y6cKCplGCdLoVpnE+ e+ba5yoY05nLIuzJOfnQXDX55q2hlg4VNqSJ8ibXAm173Eahts2eqjk/FyokZ8MepBK5DWTp7H3 HTGorXpDTVT56jJRzetje9sfF/IHGp72sExRXsh8JUUdFk/3+LxxfXDPITg6LZhCyNF8GsplxtR po2UawPu3x2Coy2TLi5PstrCC1kaX7K8NhLsdRKVsH72WoOW7OC8sZvgDe7NnjshVEIxBcu8rHX PXgLMC2oU9UAliHACVfEulZMWQ8OxuW521fA== X-Received: by 2002:a05:600c:a00c:b0:48a:56d5:16f2 with SMTP id 5b1f17b1804b1-48a8415bbc1mr42026335e9.7.1777545880246; Thu, 30 Apr 2026 03:44:40 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Mohamed Mediouni , qemu-arm@nongnu.org, Pedro Barbuda , Peter Maydell , Paolo Bonzini , kvm@vger.kernel.org, Alexander Graf , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v4 5/7] target/arm: enable event stream on WFE instructions Date: Thu, 30 Apr 2026 11:44:32 +0100 Message-ID: <20260430104434.1482407-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260430104434.1482407-1-alex.bennee@linaro.org> References: <20260430104434.1482407-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777545937797154101 Two generic timers (K and H) are capable of generating timer event stream events. Provide a helper to calculate when the nearest one will happen. Now we can calculate when the next event stream event is we can re-use the wfxt_timer and configure it to fire as we enter a WFE that is going to sleep. Reverse the M-profile logic so we can enter a sleep state in both profiles. To avoid issues with QEMU's incomplete ldst exclusive handling causing potential deadlocks in common WFE enabled locking patterns we take advantage of the architectures flexibility and treat being in the exclusive region as a reason to exit. Signed-off-by: Alex Benn=C3=A9e --- v2 - merged target/arm: add gt_calc_next_event_stream - update to use halt_reason - made arm_wfxt_timer_cb atomically consume halt_reason v4 - skip sleep if in the exclusive region - update commit message - remove the CF_PARALLEL guards so we work in smp --- target/arm/cpu.c | 13 +++ target/arm/tcg/op_helper.c | 143 ++++++++++++++++++++++++++++----- target/arm/tcg/translate-a64.c | 10 +-- target/arm/tcg/translate.c | 16 +--- 4 files changed, 140 insertions(+), 42 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fb79981338c..a23b7e87495 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -875,10 +875,23 @@ bool arm_cpu_exec_halt(CPUState *cs) } #endif =20 +/* + * Unlike almost everything else that messes with the halt_reason and + * event_register details the timer callbacks are not in the vCPU + * context. + * + * To prevent races we atomically consume a HALT_WFE and set the event + * register. Either way we trigger the an exit event. + */ static void arm_wfxt_timer_cb(void *opaque) { ARMCPU *cpu =3D opaque; CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + + if (qatomic_cmpxchg(&env->halt_reason, HALT_WFE, NOT_HALTED)) { + qatomic_set(&env->event_register, true); + } =20 /* * We expect the CPU to be halted; this will cause arm_cpu_is_work() diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 2b1fb1e059d..d0f45522b05 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -483,6 +483,97 @@ void HELPER(sev)(CPUARMState *env) } } =20 +#ifndef CONFIG_USER_ONLY +/* + * Event Stream events don't do anything apart from wake up sleeping + * cores. These helpers calculate the next event stream event time so + * the WFE helper can decide when its next wake up tick will be. + */ +static int64_t gt_recalc_one_evt(CPUARMState *env, uint32_t control, uint6= 4_t offset) +{ + ARMCPU *cpu =3D env_archcpu(env); + bool evnten =3D FIELD_EX32(control, CNTxCTL, EVNTEN); + + if (evnten) { + int evnti =3D FIELD_EX32(control, CNTxCTL, EVNTI); + bool evntis =3D FIELD_EX32(control, CNTxCTL, EVNTIS); + bool evntdir =3D FIELD_EX32(control, CNTxCTL, EVNTDIR); + /* + * To figure out when the next event timer should fire we need + * to calculate which bit of the counter we want to flip and + * which transition counts. + * + * So we calculate 1 << bit - current lower bits and then add + * 1 << bit if the bit needs to flip twice to meet evntdir + */ + int bit =3D evntis ? evnti + 8 : evnti; + uint64_t count =3D gt_get_countervalue(env) - offset; + uint64_t target_bit =3D BIT_ULL(bit); + uint64_t lower_bits =3D MAKE_64BIT_MASK(0, bit - 1); + uint64_t next_tick =3D target_bit - (count & lower_bits); + uint64_t abstick; + + /* do we need to bit flip twice? */ + if (((count & target_bit) !=3D 0) ^ evntdir) { + next_tick +=3D target_bit; + } + + /* + * Note that the desired next expiry time might be beyond the + * signed-64-bit range of a QEMUTimer -- in this case we just + * set the timer for as far in the future as possible. When the + * timer expires we will reset the timer for any remaining period. + */ + if (uadd64_overflow(next_tick, offset, &abstick)) { + abstick =3D UINT64_MAX; + } + if (abstick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { + return INT64_MAX; + } else { + return abstick; + } + } + + return -1; +} + +/* + * Calculate the next event stream time and return it. Returns -1 if + * no event streams are enabled. It is up to the WFE helpers to decide + * on the next time. + */ +static int64_t gt_calc_next_event_stream(CPUARMState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint64_t hcr =3D arm_hcr_el2_eff(env); + int64_t next_time =3D -1; + uint64_t offset; + + /* Unless we are missing EL2 this can generate events */ + if (arm_feature(env, ARM_FEATURE_EL2)) { + offset =3D gt_direct_access_timer_offset(env, GTIMER_PHYS); + next_time =3D gt_recalc_one_evt(env, env->cp15.cnthctl_el2, offset= ); + } + + /* Event stream events from virtual counter enabled? */ + if (!cpu_isar_feature(aa64_vh, cpu) || + !((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE))) { + int64_t next_virt_time; + offset =3D gt_direct_access_timer_offset(env, GTIMER_VIRT); + next_virt_time =3D gt_recalc_one_evt(env, env->cp15.c14_cntkctl, o= ffset); + + /* is this earlier than the next physical event? */ + if (next_virt_time > 0) { + if (next_time < 0 || next_virt_time < next_time) { + next_time =3D next_virt_time; + } + } + } + + return next_time; +} +#endif + void HELPER(wfe)(CPUARMState *env) { #ifdef CONFIG_USER_ONLY @@ -495,32 +586,44 @@ void HELPER(wfe)(CPUARMState *env) #else /* * WFE (Wait For Event) is a hint instruction. - * For Cortex-M (M-profile), we implement the strict architectural beh= avior: + * * 1. Check the Event Register (set by SEV or SEVONPEND). * 2. If set, clear it and continue (consume the event). */ - if (arm_feature(env, ARM_FEATURE_M)) { - CPUState *cs =3D env_cpu(env); + CPUState *cs =3D env_cpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); =20 - if (env->event_register) { - env->event_register =3D false; - return; - } + if (env->event_register) { + env->event_register =3D false; + return; + } =20 - env->halt_reason =3D HALT_WFE; - cs->exception_index =3D EXCP_HLT; - cs->halted =3D 1; - cpu_loop_exit(cs); - } else { - /* - * For A-profile and others, we rely on the existing "yield" behav= ior. - * Don't actually halt the CPU, just yield back to top - * level loop. This is not going into a "low power state" - * (ie halting until some event occurs), so we never take - * a configurable trap to a different exception level - */ - HELPER(yield)(env); + /* + * If the CPU has entered the exclusive region we could sleep + * until the global monitor moves from Exclusive to Open Access. + * However it would be expensive for QEMU to fully model the + * global monitor and not doing so would potentially trigger + * deadlocks in WFE enabled locking code. However as WFE is a hint + * instruction the architecture allows for the PE to leave + * low-power state for any reason. QEMU chooses to treat being in + * an exclusive region as such and return directly. + */ + if (env->exclusive_addr !=3D -1) { + return; + } + + /* For A-profile we also can be woken by the event stream */ + if (arm_feature(env, ARM_FEATURE_AARCH64) && cpu->wfxt_timer) { + int64_t next_event =3D gt_calc_next_event_stream(env); + if (next_event > 0) { + timer_mod(cpu->wfxt_timer, next_event); + } } + + env->halt_reason =3D HALT_WFE; + cs->exception_index =3D EXCP_HLT; + cs->halted =3D 1; + cpu_loop_exit(cs); #endif } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 07014717316..8b97136e78b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2052,15 +2052,7 @@ static bool trans_SEVL(DisasContext *s, arg_SEV *a) =20 static bool trans_WFE(DisasContext *s, arg_WFI *a) { - /* - * When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_WFE; - } + s->base.is_jmp =3D DISAS_WFE; return true; } =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 50d0184e84e..3ab49887ce6 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3262,19 +3262,9 @@ static bool trans_SEVL(DisasContext *s, arg_SEV *a) =20 static bool trans_WFE(DisasContext *s, arg_WFE *a) { - /* - * When running single-threaded TCG code, use the helper to ensure that - * the next round-robin scheduled vCPU gets a crack. - * - * For Cortex-M, we implement the architectural WFE behavior (sleeping - * until an event occurs or the Event Register is set). - * For other profiles, we currently treat this as a NOP or yield, - * to preserve existing performance characteristics. - */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_update_pc(s, curr_insn_len(s)); - s->base.is_jmp =3D DISAS_WFE; - } + /* For WFE, halt the vCPU until an event. */ + gen_update_pc(s, curr_insn_len(s)); + s->base.is_jmp =3D DISAS_WFE; return true; } =20 --=20 2.47.3 From nobody Sat May 30 19:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777546022; cv=none; d=zohomail.com; s=zohoarc; b=RFOnLKoxDV+NDAR1vdAY/6gnQ4wvqWroTAXGwjvDYfrF+wJs242scFPMDqdlZIg+lu5RD46n4qfSi4UXniJ51aZr+hSbS+Bf9dYfzYFwMpR0mYQK6GopQw85d+9T0OsL89yV/WFyPXCjO6PVk1glOpcCBuQcXufeBE/xJgthL7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777546022; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IcPSBiwzrF8PlqagZ+bzBqOtmIa2hTG8ka0zp0wOeJQ=; b=ICw2Hx9k0h0yBF54sfIR1Z8m+G9r6tmTCS4tJVX0V1BkJvn8gZLM4nDa6QADbbiF3S5NhaUGUNUDlW01hZpygBFN4+KnaSMfDaLK6W65Db4xQqFfm1BB3NcgwJcKbGwAwTmjArNl/pc2DA0VjnMft06NRDA2oztdWKsv7VZoR0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177754602291951.74267407816285; Thu, 30 Apr 2026 03:47:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wIOt7-0008MY-70; Thu, 30 Apr 2026 06:44:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wIOt1-0008If-Ls for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:51 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wIOsv-0005LC-NR for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:51 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-488b150559bso5380835e9.1 for ; Thu, 30 Apr 2026 03:44:42 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a7c31c6ddsm39447895e9.27.2026.04.30.03.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 03:44:38 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 64EE35F944; Thu, 30 Apr 2026 11:44:35 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777545881; x=1778150681; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IcPSBiwzrF8PlqagZ+bzBqOtmIa2hTG8ka0zp0wOeJQ=; b=DsfR6PUzNJ8BWzigpIAZjf1xA7tNoZELc2oceB618l5Em9IP9AK2Y/1hxVKry8r6V1 ZYYF9QES1wVz68R+vgaipJy4d0hfxh9O4oFZ3ok9NyG3xwx4j2pWodQDGKAi2/xVN5oS oX8STPHa+s+r5HQ/GhgH9V7VHzkUuxecseLltYBe+tPWTSzFCn6How2iGg35jGxaO1yP ilQwB5Jq1c6IwHRMA5JxDNa+lwS4TLxjtTKmSx3+ygR7fT4nzk9N7Ez9+Hid70EZpXzC QaQMzecuDvvp7e/pI49xZ1pnhSvle9ttujTNKq2xxnDCIiodC+bO5fJgcKCsKWH3Zuwo S9tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777545881; x=1778150681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=IcPSBiwzrF8PlqagZ+bzBqOtmIa2hTG8ka0zp0wOeJQ=; b=OfAR2XASVZreT6Y0nj2w/akC0x0u+RSg+hCHWXqJb8WXGyPjj6dhwtTS/K1DDXwJzD Md74UBeXRe2Lu4l/SbXWcXVX/34L0Cu9NJ7aGW675rsw6tPPCqy4zaE85SCIeS4AoZXq qL4BpN7UqqTMzK9U37myKH/XA3ABXn6rFXE8mnTFDwUB+6HQOKXVdpEjyxCKQZoZE2kd 9juTOBJU3KH6YwGpB8H52MmEGne8Qx96+6PWz7JNgJcPftzFFzhbz+ja/2mGypVoKcjA VQMqcdEAlTsVre9e3xNgv6ZhupyvrQw0dX0WNIqv/X5EZnBhVNH+EV0MpfUcwr7YT+uQ w0EQ== X-Gm-Message-State: AOJu0YxBcViUJHg3KIrgrwVILXD5/1p6dQvoro+zaZyWXsTJO8khVAVE t89RIE2aBZDs/86lUMVficWde6tJlBGvtABCOoyVkeEIXDtoc0Df/C/Jxehtdhr1Fa0= X-Gm-Gg: AeBDieuMyQRblOWQGGWi1AL970kpah5t+80Si73oQylnIAKmSbhUGpLZPFOazSg604A I2i3rYcMe4jm8CulJREFyBa1id5J6WN74A0WjBPzGc3jRvDKxBlNTL5AGWG0swd30nFnTkaAfkD C8xIs41PhotdKqk4Ng1V5VBbZhSncwQmnbLE3da18V70Jxvr46Ybz7VGqMEXKcJQRUTOHC0NyhD EZkp5b3L/+dYBuzvOgYHBrL6DoHiCyg2r8Z1PwkidBsvBDowKwLwZky3A9wfWl3S37gqVFxQQBK T5Y7WV8LCWq3j3KGwRIec43T/3nGm3PrILHZhJZooOj/SwuteMn3DbGprzHww1Pnc2BvwE8LPQ/ Xf7plivaQ/IuE58i+OnJ2p+xCCGFXX3jpowTYNDEpApnl8WYL2IZuN8W8OkKygKdEGlMcwEADV0 qBkS54w0iK84q89rwqnWJRTkV7Sv/OLX1PXg== X-Received: by 2002:a05:600c:3e10:b0:488:bc6a:528d with SMTP id 5b1f17b1804b1-48a844721d9mr41943205e9.22.1777545880894; Thu, 30 Apr 2026 03:44:40 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Mohamed Mediouni , qemu-arm@nongnu.org, Pedro Barbuda , Peter Maydell , Paolo Bonzini , kvm@vger.kernel.org, Alexander Graf , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v4 6/7] target/arm: handle the WFE trap case Date: Thu, 30 Apr 2026 11:44:33 +0100 Message-ID: <20260430104434.1482407-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260430104434.1482407-1-alex.bennee@linaro.org> References: <20260430104434.1482407-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777546024663154100 Now WFE can actually suspend on A-profile we also need to handle when its trapped. To do this we need to pass the instruction size so we can deal with the is_16bit syndrome encoding. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/tcg/helper-defs.h | 2 +- target/arm/tcg/op_helper.c | 15 ++++++++++++++- target/arm/tcg/translate-a64.c | 2 +- target/arm/tcg/translate.c | 2 +- 4 files changed, 17 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index a05f2258f29..ebdf09be38a 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -54,7 +54,7 @@ DEF_HELPER_2(exception_swstep, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) -DEF_HELPER_1(wfe, void, env) +DEF_HELPER_2(wfe, void, env, i32) DEF_HELPER_2(wfit, void, env, i32) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index d0f45522b05..77ac6161e93 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -574,7 +574,7 @@ static int64_t gt_calc_next_event_stream(CPUARMState *e= nv) } #endif =20 -void HELPER(wfe)(CPUARMState *env) +void HELPER(wfe)(CPUARMState *env, uint32_t insn_len) { #ifdef CONFIG_USER_ONLY /* @@ -592,12 +592,25 @@ void HELPER(wfe)(CPUARMState *env) */ CPUState *cs =3D env_cpu(env); ARMCPU *cpu =3D ARM_CPU(cs); + uint32_t excp; + int target_el =3D check_wfx_trap(env, true, &excp); =20 if (env->event_register) { env->event_register =3D false; return; } =20 + /* We might sleep, so now we check to see if we should trap */ + if (target_el) { + if (env->aarch64) { + env->pc -=3D insn_len; + } else { + env->regs[15] -=3D insn_len; + } + raise_exception(env, excp, syn_wfx(1, 0xe, 0, false, WFE, insn_len= =3D=3D 2), + target_el); + } + /* * If the CPU has entered the exclusive region we could sleep * until the global monitor moves from Exclusive to Open Access. diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8b97136e78b..a6f392a28f8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10938,7 +10938,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) */ case DISAS_WFE: gen_a64_update_pc(dc, 4); - gen_helper_wfe(tcg_env); + gen_helper_wfe(tcg_env, tcg_constant_i32(4)); tcg_gen_exit_tb(NULL, 0); break; case DISAS_WFI: diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 3ab49887ce6..686980b58e3 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -6836,7 +6836,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) tcg_gen_exit_tb(NULL, 0); break; case DISAS_WFE: - gen_helper_wfe(tcg_env); + gen_helper_wfe(tcg_env, tcg_constant_i32(curr_insn_len(dc))); /* * The helper can return if the event register is set, so we * must go back to the main loop to check for events. --=20 2.47.3 From nobody Sat May 30 19:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777546013; cv=none; d=zohomail.com; s=zohoarc; b=HzunfprVfrZzBQxsODSe1DWX5RpewaR3bbYYvfyPJX9lzs7o1MbSePMPxgDenADXMPx/oRejZtxOwogHD1DMVHkObMabXQkKKV7275DP8z539rs9ApqTBO+5QmN+PZoG9tEG+TYblh8rz5KqfmJr+53rRA9epkv5GHEj24xOSKw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777546013; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5z/E+NEUk6p/y4Qsh2ZiVobxIRwHiu1lhqMJeWdQLKM=; b=ImHUWUYdwIMN3abWrScdPZgNVT+s/IFY20z9qcPD+QwI2a/4kcsOYN993e06vGXVatJuE8VR5yOhelcel/W19RV9UDnPwH/vkZggjVpYP/xTU3GvVNmEcr+8KsHiOPWHYJeBVgWynspsZ6GXD+JoDj74vZ+nubnqqnM/QAACaUg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17775460139241015.6148416293645; Thu, 30 Apr 2026 03:46:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wIOt7-0008Mf-PQ; Thu, 30 Apr 2026 06:44:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wIOsz-0008Gp-35 for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:49 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wIOsu-0005LO-Fi for qemu-devel@nongnu.org; Thu, 30 Apr 2026 06:44:48 -0400 Received: by mail-wm1-x344.google.com with SMTP id 5b1f17b1804b1-4891b0786beso5117015e9.1 for ; Thu, 30 Apr 2026 03:44:43 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-447b7217afesm12338368f8f.23.2026.04.30.03.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 03:44:39 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 7D1855F954; Thu, 30 Apr 2026 11:44:35 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777545882; x=1778150682; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5z/E+NEUk6p/y4Qsh2ZiVobxIRwHiu1lhqMJeWdQLKM=; b=uHsO6JMo6sVIpJLRApTlqkt024zQ+YnYE/Vu28o7qPGaFZfYyY84PYPyHY4GiBUQae BTQ9mv/r5/WgHQakUVNRgjGh2QS4MQnZUFfXHRAAY7IJ2HfBB6FzEdFMQ1UE0wX4C60Q UaqwXV2qNcZpwkPjj7derqRMNENeqPFVNNoqNnr0TxuD8v1XmuRuhmusj05zEX7IBscz /rIE5XEu8fQICXmUfGFvcwA5wAOx6mU3Vy3pAExtabexN/kNqMecVsh0+1i6rJ0rUWpL hlaTyP9tNd3NqzZ1t1H6RQ5vFQMgZwl6sBcbMCel+wX959hGaa23rh0G6XIxVwhoQ75h 73tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777545882; x=1778150682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=5z/E+NEUk6p/y4Qsh2ZiVobxIRwHiu1lhqMJeWdQLKM=; b=mbVPxEzZkf4Xvh/JADvzIXuOcZU1U47AG2YAhyW+mWz0/qDtWWF8nKgCrPCZuHv0Y0 fiqeCRE2KGBWWjKHU3nBm9wvsnGJKAfZqjJUmwq9E7woEir9lL+yBF7k80QtVJBOST+t YtcfdZvN14CS3zd1oWR7Ww8jNhqefDlwJG0W3joFBpRGAvyreOoBznkwW/OzVo9ARr0c V7KwDPYfLsUSBtlZE7Hv+Vg7LCNjRttl66s+MTYscRT/q+2QS8imMmXSFDp7q8rdzRWf rxkwdNU7H6qQIy3Ie+lcKqa0IYccRwjrLWZCJoBtV83S8kWaccUy00kGoP/bAdCB8Uk0 s47A== X-Gm-Message-State: AOJu0YwuMjGZKlVHwQnvj99kyG6nmL38v1UFh1HjxywDSeHbyFMjoh8u NuqNdE5LUo4g++/7uUN65UXzsE9kgtW+IBrtLwjn4r+vJ/EzSRaYLQ0w35h5rIxFdEWuYj+XKbu jRgyXOR7LshUf X-Gm-Gg: AeBDietQxPNfgCmPfXQWV8JT2NbaOK+yFxeq6yc69CVYDpUD2lP8nXLHcPycA8KkuZk tTbU4b7OakCic6aiVrS04dIFDGn3DrOWTSaMDINuNG4cjzK8ujKmycToqC0KeWh13Z5GJ+qOMyQ 95ikvsnkicVc594KzUfWwdJcv00b3ZxS3OkxqQVfFPFpfq/rMVz+yRel20BNh+1nOx6Ggo3opNf dy7eiOW2jZqmaxkcpD/hfUoe02EG6tvCQSKngVESaSlEqMpNeBcsh5H+t1gE5UrqkHqmeU7SMmS cDe7IPyczwmPj0Ff9A9uNE/9HNs32GQo08coETxyqFIK8qYGc8noWpJTgddKxQxgLuWl9Cr9XK1 52Axw6FyAezQ7cNp0C1u+iSJfm0eq0jiYcJV+2qmO481g7xuSyjC9DLuvBOExR9vW76lBVxO+tZ Z90/hyav2GQRj2SYPGiFQBG+mZY5qYlq0V5g== X-Received: by 2002:a5d:5847:0:b0:43f:e791:a347 with SMTP id ffacd0b85a97d-4493e982935mr3711927f8f.26.1777545881915; Thu, 30 Apr 2026 03:44:41 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Mohamed Mediouni , qemu-arm@nongnu.org, Pedro Barbuda , Peter Maydell , Paolo Bonzini , kvm@vger.kernel.org, Alexander Graf , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v4 7/7] target/arm: implement WFET Date: Thu, 30 Apr 2026 11:44:34 +0100 Message-ID: <20260430104434.1482407-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260430104434.1482407-1-alex.bennee@linaro.org> References: <20260430104434.1482407-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777546014870158500 Now we have the event stream and SEV/SEVL implemented we can finally enable WFET for Aarch64. To avoid issues with QEMU's incomplete ldst exclusive handling causing potential deadlocks in common WFE enabled locking patterns we take advantage of the architectures flexibility and treat being in the exclusive region as a reason to exit. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - fix exception syndrome by using enum value - use env->halt_reason v3 - fix check_wfx_trap(s/false/true/) as it is a WFE v4 - defer expensive calculations until needed - treat cs->exclusive_addr as a IMPDEF WFE exit - update commit message --- target/arm/tcg/helper-defs.h | 1 + target/arm/tcg/op_helper.c | 95 ++++++++++++++++++++++++++++++++++ target/arm/tcg/translate-a64.c | 15 +++--- 3 files changed, 104 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index ebdf09be38a..5e4d828dd55 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -56,6 +56,7 @@ DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_2(wfe, void, env, i32) DEF_HELPER_2(wfit, void, env, i32) +DEF_HELPER_2(wfet, void, env, i32) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 77ac6161e93..8421c548303 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -640,6 +640,101 @@ void HELPER(wfe)(CPUARMState *env, uint32_t insn_len) #endif } =20 +void HELPER(wfet)(CPUARMState *env, uint32_t rd) +{ +#ifdef CONFIG_USER_ONLY + /* + * As for WFIT make it NOP here, because trying to raise EXCP_HLT + * would trigger an abort. + */ + return; +#else + CPUState *cs =3D env_cpu(env); + uint32_t excp; + int target_el; + ARMCPU *cpu; + uint64_t cntval, timeout, offset, cntvct, nexttick; + int64_t next_event; + + /* + * As for WFE if the event register is already set we can consume + * the event and return immediately. + */ + if (env->event_register) { + env->event_register =3D false; + return; + } + + /* + * Don't bother to go into our "low power state" if + * we would just wake up immediately. + * + * We want the value that we would get if we read CNTVCT_EL0 from + * the current exception level, so the direct_access offset, not + * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(), + * which calls VirtualCounterTimer(). + */ + cntval =3D gt_get_countervalue(env); + offset =3D gt_direct_access_timer_offset(env, GTIMER_VIRT); + cntvct =3D cntval - offset; + timeout =3D env->xregs[rd]; + if (cpu_has_work(cs) || cntvct >=3D timeout) { + return; + } + + /* We might sleep, so now we check to see if we should trap */ + target_el =3D check_wfx_trap(env, true, &excp); + if (target_el) { + env->pc -=3D 4; + raise_exception(env, excp, syn_wfx(1, 0xe, rd, true, WFET, false),= target_el); + } + + /* + * If the CPU has entered the exclusive region we could sleep + * until the global monitor moves from Exclusive to Open Access. + * However it would be expensive for QEMU to fully model the + * global monitor and not doing so would potentially trigger + * deadlocks in WFE enabled locking code. However as WFE is a hint + * instruction the architecture allows for the PE to leave + * low-power state for any reason. QEMU chooses to treat being in + * an exclusive region as such and return directly. + */ + if (env->exclusive_addr !=3D -1) { + return; + } + + /* + * Finally work out if the timeout or event stream will kick in + * earlier. + * + * The WFET should time out when CNTVCT_EL0 >=3D the specified value. + */ + cpu =3D env_archcpu(env); + if (uadd64_overflow(timeout, offset, &nexttick)) { + nexttick =3D UINT64_MAX; + } + if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { + nexttick =3D INT64_MAX; + } + + next_event =3D gt_calc_next_event_stream(env); + if (next_event > 0 && next_event < nexttick) { + timer_mod(cpu->wfxt_timer, next_event); + } else { + if (nexttick =3D=3D INT64_MAX) { + timer_mod_ns(cpu->wfxt_timer, INT64_MAX); + } else { + timer_mod(cpu->wfxt_timer, nexttick); + } + } + + env->halt_reason =3D HALT_WFE; + cs->exception_index =3D EXCP_HLT; + cs->halted =3D 1; + cpu_loop_exit(cs); +#endif +} + void HELPER(yield)(CPUARMState *env) { CPUState *cs =3D env_cpu(env); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a6f392a28f8..ead2a7ff81f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2086,14 +2086,15 @@ static bool trans_WFET(DisasContext *s, arg_WFET *a) return false; } =20 - /* - * We rely here on our WFE implementation being a NOP, so we - * don't need to do anything different to handle the WFET timeout - * from what trans_WFE does. - */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_WFE; + if (s->ss_active) { + /* Act like a NOP under architectural singlestep */ + return true; } + + gen_a64_update_pc(s, 4); + gen_helper_wfet(tcg_env, tcg_constant_i32(a->rd)); + /* Go back to the main loop to check for interrupts */ + s->base.is_jmp =3D DISAS_EXIT; return true; } =20 --=20 2.47.3