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charset="utf-8" This patch adds new model for Axiado SoC AX3000 which supports 4 Cortex-A53 ARM64 CPUs Arm Generic Interrupt Controller v3 4 Cadence UARTs 1 SDHCI controller with eMMC PHY Signed-off-by: Kuan-Jui Chiu --- MAINTAINERS | 9 ++ hw/arm/Kconfig | 8 ++ hw/arm/ax3000-soc.c | 232 +++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 3 + hw/sd/Kconfig | 4 + hw/sd/axiado_sdhci.c | 100 +++++++++++++++ hw/sd/meson.build | 1 + include/hw/arm/ax3000-soc.h | 78 ++++++++++++ include/hw/sd/axiado_sdhci.h | 21 ++++ 9 files changed, 456 insertions(+) create mode 100644 hw/arm/ax3000-soc.c create mode 100644 hw/sd/axiado_sdhci.c create mode 100644 include/hw/arm/ax3000-soc.h create mode 100644 include/hw/sd/axiado_sdhci.h diff --git a/MAINTAINERS b/MAINTAINERS index 0a90204ae9..69da0df99a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1285,6 +1285,15 @@ M: Manos Pitsidianakis S: Maintained F: rust/hw/char/pl011/ =20 +Axiado SoCs and EVKs +M: Kuan-Jui Chiu +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/ax3000*.c +F: hw/*/axiado*.c +F: include/hw/arm/ax3000*.h +F: include/hw/*/axiado*.h + AVR Machines ------------- =20 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4e50fb1111..4fb23122fd 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -691,3 +691,11 @@ config ARMSSE select UNIMP select SSE_COUNTER select SSE_TIMER + +config AXIADO_SOC + bool + depends on ARM + select ARM_GIC + select CADENCE # UART + select AXIADO_SDHCI + select UNIMP diff --git a/hw/arm/ax3000-soc.c b/hw/arm/ax3000-soc.c new file mode 100644 index 0000000000..e845a64c2a --- /dev/null +++ b/hw/arm/ax3000-soc.c @@ -0,0 +1,232 @@ +/* + * Axiado SoC AX3000 + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "system/address-spaces.h" +#include "hw/arm/bsa.h" +#include "hw/arm/ax3000-soc.h" +#include "hw/misc/unimp.h" +#include "system/system.h" +#include "qobject/qlist.h" +#include "qom/object.h" +#include "hw/core/boards.h" + +static uint64_t pll_read(void *opaque, hwaddr offset, unsigned size) +{ + switch (offset) { + case CLKRST_CPU_PLL_POSTDIV_OFFSET: + return 0x20891b; + case CLKRST_CPU_PLL_STS_OFFSET: + return 0x01; + default: + return 0x00; + } +} + +static void pll_write(void *opaque, hwaddr offset, uint64_t val, unsigned = size) +{ + /* TBD */ +} + +static const MemoryRegionOps pll_ops =3D { + .read =3D pll_read, + .write =3D pll_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void ax3000_init(Object *obj) +{ + Ax3000SoCState *s =3D AX3000_SOC(obj); + Ax3000SoCClass *sc =3D AX3000_SOC_GET_CLASS(s); + int i; + + for (i =3D 0; i < sc->num_cpus; i++) { + g_autofree char *name =3D g_strdup_printf("cpu%d", i); + object_initialize_child(obj, name, &s->cpu[i], + ARM_CPU_TYPE_NAME("cortex-a53")); + } + + object_initialize_child(obj, "gic", &s->gic, gicv3_class_name()); + + for (i =3D 0; i < AX3000_NUM_UARTS; i++) { + g_autofree char *name =3D g_strdup_printf("uart%d", i); + object_initialize_child(obj, name, &s->uart[i], TYPE_CADENCE_UART); + } + + object_initialize_child(obj, "sdhci0", &s->sdhci0, TYPE_AXIADO_SDHCI); +} + +static void ax3000_realize(DeviceState *dev, Error **errp) +{ + Ax3000SoCState *s =3D AX3000_SOC(dev); + Ax3000SoCClass *sc =3D AX3000_SOC_GET_CLASS(s); + SysBusDevice *gic_sbd =3D SYS_BUS_DEVICE(&s->gic); + DeviceState *gic_dev =3D DEVICE(&s->gic); + QList *redist_region_count; + SysBusDevice *sdhci0_sbd; + DeviceState *card; + int i; + + /* CPUs */ + for (i =3D 0; i < sc->num_cpus; i++) { + object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000, + &error_abort); + + if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) { + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", + false, &error_abort); + } + + if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { + return; + } + } + + /* GIC */ + qdev_prop_set_uint32(gic_dev, "num-cpu", sc->num_cpus); + qdev_prop_set_uint32(gic_dev, "num-irq", + AX3000_NUM_IRQS + GIC_INTERNAL); + + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, sc->num_cpus); + qdev_prop_set_array(gic_dev, "redist-region-count", redist_region_coun= t); + + if (!sysbus_realize(gic_sbd, errp)) { + return; + } + + sysbus_mmio_map(gic_sbd, 0, AX3000_GIC_DIST_BASE); + sysbus_mmio_map(gic_sbd, 1, AX3000_GIC_REDIST_BASE); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, and + * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs. + */ + for (i =3D 0; i < sc->num_cpus; i++) { + DeviceState *cpu_dev =3D DEVICE(&s->cpu[i]); + int intidbase =3D AX3000_NUM_IRQS + i * GIC_INTERNAL; + qemu_irq irq; + + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs. + */ + static const int timer_irqs[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ + }; + + for (int j =3D 0; j < ARRAY_SIZE(timer_irqs); j++) { + irq =3D qdev_get_gpio_in(gic_dev, intidbase + timer_irqs[j]); + qdev_connect_gpio_out(cpu_dev, j, irq); + } + + irq =3D qdev_get_gpio_in(gic_dev, intidbase + ARCH_GIC_MAINT_IRQ); + qdev_connect_gpio_out_named(cpu_dev, "gicv3-maintenance-interrupt", + 0, irq); + + sysbus_connect_irq(gic_sbd, i, + qdev_get_gpio_in(cpu_dev, ARM_CPU_IRQ)); + sysbus_connect_irq(gic_sbd, i + sc->num_cpus, + qdev_get_gpio_in(cpu_dev, ARM_CPU_FIQ)); + sysbus_connect_irq(gic_sbd, i + 2 * sc->num_cpus, + qdev_get_gpio_in(cpu_dev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gic_sbd, i + 3 * sc->num_cpus, + qdev_get_gpio_in(cpu_dev, ARM_CPU_VFIQ)); + } + + /* DRAM */ + for (i =3D 0; i < AX3000_NUM_BANKS; i++) { + struct { + hwaddr addr; + size_t size; + const char *name; + } dram_table[] =3D { + { AX3000_DRAM0_BASE, AX3000_DRAM0_SIZE, "dram0" }, + { AX3000_DRAM1_BASE, AX3000_DRAM1_SIZE, "dram1" } + }; + + memory_region_init_ram(&s->dram[i], OBJECT(s), dram_table[i].name, + dram_table[i].size, &error_fatal); + memory_region_add_subregion(get_system_memory(), dram_table[i].add= r, + &s->dram[i]); + } + + /* UARTs */ + for (i =3D 0; i < AX3000_NUM_UARTS; i++) { + struct { + hwaddr addr; + unsigned int irq; + } serial_table[] =3D { + { AX3000_UART0_BASE, AX3000_UART0_IRQ }, + { AX3000_UART1_BASE, AX3000_UART1_IRQ }, + { AX3000_UART2_BASE, AX3000_UART2_IRQ }, + { AX3000_UART3_BASE, AX3000_UART3_IRQ } + }; + + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].ad= dr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + qdev_get_gpio_in(gic_dev, serial_table[i].irq)); + } + + /* Timer control */ + create_unimplemented_device("ax3000.timerctrl", AX3000_TIMER_CTRL, 32); + + /* PLL control */ + memory_region_init_io(&s->pll_ctrl, OBJECT(s), &pll_ops, s, + "ax3000.pllctrl", 32); + memory_region_add_subregion(get_system_memory(), AX3000_PLL_BASE, + &s->pll_ctrl); + + /* SDHCI */ + sdhci0_sbd =3D SYS_BUS_DEVICE(&s->sdhci0); + if (!sysbus_realize(sdhci0_sbd, errp)) { + return; + } + + sysbus_mmio_map(sdhci0_sbd, 0, AX3000_SDHCI0_BASE); + sysbus_mmio_map(sdhci0_sbd, 1, AX3000_EMMC_PHY_BASE); + sysbus_connect_irq(sdhci0_sbd, 0, + qdev_get_gpio_in(gic_dev, AX3000_SDHCI0_IRQ)); + + card =3D qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(card, "drive", + blk_by_legacy_dinfo((drive_get(IF_SD, 0, 0))), + &error_fatal); + qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal); +} + +static void ax3000_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + Ax3000SoCClass *sc =3D AX3000_SOC_CLASS(oc); + + dc->desc =3D "Axiado SoC AX3000"; + dc->realize =3D ax3000_realize; + sc->num_cpus =3D AX3000_NUM_CPUS; +} + +static const TypeInfo axiado_soc_types[] =3D { + { + .name =3D TYPE_AX3000_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ax3000SoCState), + .instance_init =3D ax3000_init, + .class_init =3D ax3000_class_init, + } +}; + +DEFINE_TYPES(axiado_soc_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index b187b946f0..e32f5eb0c7 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -105,6 +105,9 @@ arm_common_ss.add(when: 'CONFIG_SX1', if_true: files('o= map_sx1.c')) arm_common_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'= )) arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) =20 +arm_common_ss.add(when: ['CONFIG_AXIADO_SOC', 'TARGET_AARCH64'], if_true: = files( + 'ax3000-soc.c')) + arm_common_ss.add(files('boot.c')) =20 hw_arch +=3D {'arm': arm_ss} diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig index 633b9afec9..c69bf24f8d 100644 --- a/hw/sd/Kconfig +++ b/hw/sd/Kconfig @@ -23,3 +23,7 @@ config SDHCI_PCI config CADENCE_SDHCI bool select SDHCI + +config AXIADO_SDHCI + bool + select SDHCI diff --git a/hw/sd/axiado_sdhci.c b/hw/sd/axiado_sdhci.c new file mode 100644 index 0000000000..219d49079e --- /dev/null +++ b/hw/sd/axiado_sdhci.c @@ -0,0 +1,100 @@ +/* + * Axiado SD Host Controller + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/sd/axiado_sdhci.h" +#include "sdhci-internal.h" +#include "qapi/error.h" +#include "hw/core/qdev-properties.h" + +#define EMMC_PHY_ID 0x00 +#define EMMC_PHY_STATUS 0x50 + +static uint64_t emmc_phy_read(void *opaque, hwaddr offset, unsigned size) +{ + uint32_t val =3D 0x00; + + switch (offset) { + case EMMC_PHY_ID: + val =3D 0x3dff6870; + break; + case EMMC_PHY_STATUS: + /* Make DLL_RDY | CAL_DONE */ + val =3D (1u << 0) | (1u << 6); + break; + default: + break; + } + + return val; +} + +static void emmc_phy_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + /* TBD */ +} + +static const MemoryRegionOps emmc_phy_ops =3D { + .read =3D emmc_phy_read, + .write =3D emmc_phy_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void axiado_sdhci_realize(DeviceState *dev, Error **errp) +{ + AxiadoSDHCIState *s =3D AXIADO_SDHCI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + SysBusDevice *sdhci_sbd; + + object_initialize_child(OBJECT(s), "sdhci", &s->sdhci, + TYPE_SYSBUS_SDHCI); + + qdev_prop_set_uint64(DEVICE(&s->sdhci), "capareg", 0x216737eed0b0); + qdev_prop_set_uint64(DEVICE(&s->sdhci), "sd-spec-version", 3); + + sdhci_sbd =3D SYS_BUS_DEVICE(&s->sdhci); + sysbus_realize(sdhci_sbd, errp); + if (*errp) { + return; + } + + sysbus_init_mmio(sbd, sysbus_mmio_get_region(sdhci_sbd, 0)); + + /* Propagate IRQ from SDHCI and SD bus */ + sysbus_pass_irq(sbd, sdhci_sbd); + s->sd_bus =3D qdev_get_child_bus(DEVICE(sdhci_sbd), "sd-bus"); + + /* Initialize eMMC PHY MMIO */ + memory_region_init_io(&s->emmc_phy, OBJECT(s), &emmc_phy_ops, s, + "axiado.emmc-phy", 0x1000); + + sysbus_init_mmio(sbd, &s->emmc_phy); +} + +static void axiado_sdhci_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D axiado_sdhci_realize; + dc->desc =3D "Axiado SD Host Controller with eMMC PHY"; +} + +static const TypeInfo axiado_sdhci_info =3D { + .name =3D TYPE_AXIADO_SDHCI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AxiadoSDHCIState), + .class_init =3D axiado_sdhci_class_init, +}; + +static void axiado_sdhci_register_types(void) +{ + type_register_static(&axiado_sdhci_info); +} + +type_init(axiado_sdhci_register_types); diff --git a/hw/sd/meson.build b/hw/sd/meson.build index b43d45bc56..ebf09e30a4 100644 --- a/hw/sd/meson.build +++ b/hw/sd/meson.build @@ -10,3 +10,4 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('= aspeed_sdhci.c')) system_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhos= t.c')) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_sdhci.c')) system_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.= c')) +system_ss.add(when: 'CONFIG_AXIADO_SDHCI', if_true: files('axiado_sdhci.c'= )) diff --git a/include/hw/arm/ax3000-soc.h b/include/hw/arm/ax3000-soc.h new file mode 100644 index 0000000000..2708c9c672 --- /dev/null +++ b/include/hw/arm/ax3000-soc.h @@ -0,0 +1,78 @@ +/* + * Axiado SoC AX3000 + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef AXIADO_AX3000_H +#define AXIADO_AX3000_H + +#include "cpu.h" +#include "hw/intc/arm_gicv3_common.h" +#include "hw/char/cadence_uart.h" +#include "hw/sd/axiado_sdhci.h" +#include "hw/core/sysbus.h" +#include "qemu/units.h" + +#define TYPE_AX3000_SOC "ax3000" +OBJECT_DECLARE_TYPE(Ax3000SoCState, Ax3000SoCClass, AX3000_SOC) + +#define AX3000_DRAM0_BASE 0x3C000000 +#define AX3000_DRAM0_SIZE (1088 * MiB) +#define AX3000_DRAM1_BASE 0x400000000 +#define AX3000_DRAM1_SIZE (2 * GiB) + +#define AX3000_GIC_DIST_BASE 0x80300000 +#define AX3000_GIC_DIST_SIZE (64 * KiB) +#define AX3000_GIC_REDIST_BASE 0x80380000 +#define AX3000_GIC_REDIST_SIZE (512 * KiB) + +#define AX3000_UART0_BASE 0x80520000 +#define AX3000_UART1_BASE 0x805a0000 +#define AX3000_UART2_BASE 0x80620000 +#define AX3000_UART3_BASE 0x80520800 + +#define AX3000_SDHCI0_BASE 0x86000000 +#define AX3000_EMMC_PHY_BASE 0x80801C00 + +#define AX3000_TIMER_CTRL 0x8A020000 +#define AX3000_PLL_BASE 0x80000000 +#define CLKRST_CPU_PLL_POSTDIV_OFFSET 0x0C +#define CLKRST_CPU_PLL_STS_OFFSET 0x14 + +enum Ax3000Configuration { + AX3000_NUM_CPUS =3D 4, + AX3000_NUM_IRQS =3D 224, + AX3000_NUM_BANKS =3D 2, + AX3000_NUM_UARTS =3D 4, +}; + +typedef struct Ax3000SoCState { + SysBusDevice parent; + + ARMCPU cpu[AX3000_NUM_CPUS]; + GICv3State gic; + MemoryRegion dram[AX3000_NUM_BANKS]; + MemoryRegion pll_ctrl; + CadenceUARTState uart[AX3000_NUM_UARTS]; + AxiadoSDHCIState sdhci0; +} Ax3000SoCState; + +typedef struct Ax3000SoCClass { + SysBusDeviceClass parent; + + uint32_t num_cpus; +} Ax3000SoCClass; + +enum Ax3000Irqs { + AX3000_UART0_IRQ =3D 112, + AX3000_UART1_IRQ =3D 113, + AX3000_UART2_IRQ =3D 114, + AX3000_UART3_IRQ =3D 170, + + AX3000_SDHCI0_IRQ =3D 123, +}; + +#endif /* AXIADO_AX3000_H */ diff --git a/include/hw/sd/axiado_sdhci.h b/include/hw/sd/axiado_sdhci.h new file mode 100644 index 0000000000..85afebad93 --- /dev/null +++ b/include/hw/sd/axiado_sdhci.h @@ -0,0 +1,21 @@ +/* + * Axiado SD Host Controller + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "hw/sd/sdhci.h" +#include "qom/object.h" + +#define TYPE_AXIADO_SDHCI "axiado-sdhci" +OBJECT_DECLARE_SIMPLE_TYPE(AxiadoSDHCIState, AXIADO_SDHCI) + +typedef struct AxiadoSDHCIState { + SysBusDevice parent; + + SDHCIState sdhci; + MemoryRegion emmc_phy; + BusState *sd_bus; +} AxiadoSDHCIState; --=20 2.34.1 From nobody Sat May 30 19:21:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=axiado.com) ARC-Seal: i=2; a=rsa-sha256; t=1777540763; cv=pass; d=zohomail.com; s=zohoarc; b=cbtwru4eUocqUdFcLIDMXDX2kuaW3LgV+McKg13nYYDbX5UM63Ev1bHs2U3kGYUI5xxp0MuF/XlAdfpC0mK0X0SSDrpjSpxhbU8lTojhB94lk5kQHt6tjzmg6TPfQOKSzjzZr2g4BkEMwrnD0RfQDtUm2ZS9G8m23RkZUw1u76Q= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777540763; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Add EVK axiado-scm3003 built with AX3000 SoC Signed-off-by: Kuan-Jui Chiu --- hw/arm/Kconfig | 5 ++++ hw/arm/ax3000-boards.c | 52 ++++++++++++++++++++++++++++++++++ hw/arm/ax3000-evk.c | 27 ++++++++++++++++++ hw/arm/meson.build | 3 ++ include/hw/arm/ax3000-boards.h | 28 ++++++++++++++++++ 5 files changed, 115 insertions(+) create mode 100644 hw/arm/ax3000-boards.c create mode 100644 hw/arm/ax3000-evk.c create mode 100644 include/hw/arm/ax3000-boards.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4fb23122fd..e569d8ee9e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -699,3 +699,8 @@ config AXIADO_SOC select CADENCE # UART select AXIADO_SDHCI select UNIMP + +config AXIADO_EVK + bool + default y + select AXIADO_SOC diff --git a/hw/arm/ax3000-boards.c b/hw/arm/ax3000-boards.c new file mode 100644 index 0000000000..cadbac8edc --- /dev/null +++ b/hw/arm/ax3000-boards.c @@ -0,0 +1,52 @@ +/* + * Axiado Boards + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/arm/ax3000-boards.h" +#include "hw/arm/machines-qom.h" +#include "qemu/error-report.h" +#include "qom/object.h" + +static const char *ax3000_machine_get_default_cpu_type(const MachineState = *ms) +{ + return ARM_CPU_TYPE_NAME("cortex-a53"); +} + +static void ax3000_machine_init(MachineState *machine) +{ + Ax3000MachineState *ams =3D AX3000_MACHINE(machine); + + ams->soc =3D AX3000_SOC(object_new(TYPE_AX3000_SOC)); + object_property_add_child(OBJECT(machine), "soc", OBJECT(ams->soc)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(ams->soc), &error_fatal); +} + +static void ax3000_machine_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->init =3D ax3000_machine_init; + mc->default_cpus =3D AX3000_NUM_CPUS; + mc->min_cpus =3D AX3000_NUM_CPUS; + mc->max_cpus =3D AX3000_NUM_CPUS; + mc->get_default_cpu_type =3D ax3000_machine_get_default_cpu_type; +} + +static const TypeInfo ax3000_machine_types[] =3D { + { + .name =3D TYPE_AX3000_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(Ax3000MachineState), + .class_size =3D sizeof(Ax3000MachineClass), + .class_init =3D ax3000_machine_class_init, + .interfaces =3D aarch64_machine_interfaces, + .abstract =3D true, + } +}; + +DEFINE_TYPES(ax3000_machine_types) diff --git a/hw/arm/ax3000-evk.c b/hw/arm/ax3000-evk.c new file mode 100644 index 0000000000..a170848871 --- /dev/null +++ b/hw/arm/ax3000-evk.c @@ -0,0 +1,27 @@ +/* + * Axiado Evaluation Kit Emulation + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/arm/ax3000-boards.h" + +static void axiado_scm3003_class_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Axiado SCM3003 EVK Board"; +} + +static const TypeInfo ax3000_evk_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("axiado-scm3003"), + .parent =3D TYPE_AX3000_MACHINE, + .class_init =3D axiado_scm3003_class_init, + } +}; + +DEFINE_TYPES(ax3000_evk_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index e32f5eb0c7..39db50bcef 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -107,6 +107,9 @@ arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: fil= es('vexpress.c')) =20 arm_common_ss.add(when: ['CONFIG_AXIADO_SOC', 'TARGET_AARCH64'], if_true: = files( 'ax3000-soc.c')) +arm_common_ss.add(when: ['CONFIG_AXIADO_EVK', 'TARGET_AARCH64'], if_true: = files( + 'ax3000-boards.c', + 'ax3000-evk.c')) =20 arm_common_ss.add(files('boot.c')) =20 diff --git a/include/hw/arm/ax3000-boards.h b/include/hw/arm/ax3000-boards.h new file mode 100644 index 0000000000..4a632661e1 --- /dev/null +++ b/include/hw/arm/ax3000-boards.h @@ -0,0 +1,28 @@ +/* + * Axiado Boards + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef AXIADO_BOARD_H +#define AXIADO_BOARD_H + +#include "hw/core/boards.h" +#include "hw/arm/ax3000-soc.h" + +#define TYPE_AX3000_MACHINE MACHINE_TYPE_NAME("ax3000") +OBJECT_DECLARE_TYPE(Ax3000MachineState, Ax3000MachineClass, AX3000_MACHINE) + +typedef struct Ax3000MachineState { + MachineState parent; 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charset="utf-8" This patch add a new model for Cadence GPIO controller which supports 32 pins and interrupts for level-triggered/edge-triggered type on input pins. Also define new trace functions for analysis purpose and new configuration = to enable this model. Signed-off-by: Kuan-Jui Chiu --- hw/gpio/Kconfig | 3 + hw/gpio/cadence_gpio.c | 301 +++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 1 + hw/gpio/trace-events | 5 + include/hw/gpio/cadence_gpio.h | 55 ++++++ 5 files changed, 365 insertions(+) create mode 100644 hw/gpio/cadence_gpio.c create mode 100644 include/hw/gpio/cadence_gpio.h diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index a209294c20..fcc7c70bd5 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -30,3 +30,6 @@ config PCF8574 =20 config ZAURUS_SCOOP bool + +config CADENCE_GPIO + bool diff --git a/hw/gpio/cadence_gpio.c b/hw/gpio/cadence_gpio.c new file mode 100644 index 0000000000..2410753abc --- /dev/null +++ b/hw/gpio/cadence_gpio.c @@ -0,0 +1,301 @@ +/* + * Cadence GPIO emulation. + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/gpio/cadence_gpio.h" +#include "hw/core/irq.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "trace.h" + +static void cdns_gpio_update_irq(CadenceGPIOState *s) +{ + qemu_set_irq(s->irq, s->isr ? 1 : 0); +} + +static void cdns_gpio_update_isr_per_line(CadenceGPIOState *s, int line, + uint32_t new) +{ + uint32_t old =3D extract32(s->inpvr, line, 1); + uint32_t ivr =3D extract32(s->ivr, line, 1); + + /* Deassert in bypass mode or not input pin */ + if (extract32(s->bmr, line, 1) || !extract32(s->dmr, line, 1) || + extract32(s->imr, line, 1)) { + s->isr =3D deposit32(s->isr, line, 1, 0); + return; + } + + if (extract32(s->itr, line, 1)) { + /* Level-triggered */ + if (ivr && new) { + /* High level */ + s->isr =3D deposit32(s->isr, line, 1, 1); + } + if (!ivr && !new) { + /* Low level */ + s->isr =3D deposit32(s->isr, line, 1, 1); + } + } else { + /* Edge-triggered */ + if (extract32(s->ioar, line, 1) && (old !=3D new)) { + /* On any edge */ + s->isr =3D deposit32(s->isr, line, 1, 1); + } else { + if (ivr && !old && new) { + /* Rising edge */ + s->isr =3D deposit32(s->isr, line, 1, 1); + } + if (!ivr && old && !new) { + /* Falling edge */ + s->isr =3D deposit32(s->isr, line, 1, 1); + } + } + } +} + +static void cdns_gpio_update_isr(CadenceGPIOState *s) +{ + for (int i =3D 0; i < CDNS_GPIO_NUM; i++) { + uint32_t level =3D extract32(s->inpvr, i, 1); + cdns_gpio_update_isr_per_line(s, i, level); + } +} + +static void cdns_gpio_set(void *opaque, int line, int level) +{ + CadenceGPIOState *s =3D CADENCE_GPIO(opaque); + uint32_t new =3D level ? 1 : 0; + + trace_cdns_gpio_set(DEVICE(s)->canonical_path, line, level); + + cdns_gpio_update_isr_per_line(s, line, new); + + /* Sync INPVR with new value */ + s->inpvr =3D deposit32(s->inpvr, line, 1, new); + + cdns_gpio_update_irq(s); +} + +static inline void cdns_gpio_update_output_irq(CadenceGPIOState *s) +{ + for (int i =3D 0; i < CDNS_GPIO_NUM; i++) { + /* Forward the output value to corresponding irq */ + if (!extract32(s->bmr, i, 1) && !extract32(s->dmr, i, 1) && + extract32(s->oer, i, 1) && s->output[i]) { + qemu_set_irq(s->output[i], extract32(s->ovr, i, 1)); + } + } +} + +static uint64_t cdns_gpio_read(void *opaque, hwaddr offset, unsigned size) +{ + CadenceGPIOState *s =3D CADENCE_GPIO(opaque); + uint32_t reg_value =3D 0x0; + + switch (offset) { + case CDNS_GPIO_BYPASS_MODE: + reg_value =3D s->bmr; + break; + + case CDNS_GPIO_DIRECTION_MODE: + reg_value =3D s->dmr; + break; + + case CDNS_GPIO_OUTPUT_EN: + reg_value =3D s->oer; + break; + + case CDNS_GPIO_OUTPUT_VALUE: + reg_value =3D s->ovr; + break; + + case CDNS_GPIO_INPUT_VALUE: + reg_value =3D s->inpvr; + break; + + case CDNS_GPIO_IRQ_MASK: + reg_value =3D s->imr; + break; + + case CDNS_GPIO_IRQ_STATUS: + reg_value =3D s->isr; + break; + + case CDNS_GPIO_IRQ_TYPE: + reg_value =3D s->itr; + break; + + case CDNS_GPIO_IRQ_VALUE: + reg_value =3D s->ivr; + break; + + case CDNS_GPIO_IRQ_ANY_EDGE: + reg_value =3D s->ioar; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" + HWADDR_PRIx "\n", TYPE_CADENCE_GPIO, __func__, offse= t); + break; + } + + trace_cdns_gpio_read(DEVICE(s)->canonical_path, offset, reg_value); + + return reg_value; +} + +static void cdns_gpio_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + CadenceGPIOState *s =3D CADENCE_GPIO(opaque); + + trace_cdns_gpio_write(DEVICE(s)->canonical_path, offset, value); + + switch (offset) { + case CDNS_GPIO_BYPASS_MODE: + s->bmr =3D value; + cdns_gpio_update_output_irq(s); + cdns_gpio_update_isr(s); + cdns_gpio_update_irq(s); + break; + + case CDNS_GPIO_DIRECTION_MODE: + s->dmr =3D value; + cdns_gpio_update_output_irq(s); + cdns_gpio_update_isr(s); + cdns_gpio_update_irq(s); + break; + + case CDNS_GPIO_OUTPUT_EN: + s->oer =3D value; + cdns_gpio_update_output_irq(s); + break; + + case CDNS_GPIO_OUTPUT_VALUE: + s->ovr =3D value; + cdns_gpio_update_output_irq(s); + break; + + case CDNS_GPIO_IRQ_EN: + s->imr &=3D ~value; + cdns_gpio_update_isr(s); + cdns_gpio_update_irq(s); + break; + + case CDNS_GPIO_IRQ_DIS: + s->imr |=3D value; + cdns_gpio_update_isr(s); + cdns_gpio_update_irq(s); + break; + + case CDNS_GPIO_IRQ_TYPE: + s->itr =3D value; + break; + + case CDNS_GPIO_IRQ_VALUE: + s->ivr =3D value; + break; + + case CDNS_GPIO_IRQ_ANY_EDGE: + s->ioar =3D value; + break; + + case CDNS_GPIO_INPUT_VALUE: + case CDNS_GPIO_IRQ_MASK: + case CDNS_GPIO_IRQ_STATUS: + /* Read-Only */ + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" + HWADDR_PRIx "\n", TYPE_CADENCE_GPIO, __func__, offse= t); + break; + } +} + +static const MemoryRegionOps cdns_gpio_ops =3D { + .read =3D cdns_gpio_read, + .write =3D cdns_gpio_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const VMStateDescription vmstate_cdns_gpio =3D { + .name =3D TYPE_CADENCE_GPIO, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(bmr, CadenceGPIOState), + VMSTATE_UINT32(dmr, CadenceGPIOState), + VMSTATE_UINT32(oer, CadenceGPIOState), + VMSTATE_UINT32(ovr, CadenceGPIOState), + VMSTATE_UINT32(inpvr, CadenceGPIOState), + VMSTATE_UINT32(imr, CadenceGPIOState), + VMSTATE_UINT32(isr, CadenceGPIOState), + VMSTATE_UINT32(itr, CadenceGPIOState), + VMSTATE_UINT32(ivr, CadenceGPIOState), + VMSTATE_UINT32(ioar, CadenceGPIOState), + VMSTATE_END_OF_LIST() + } +}; + +static void cdns_gpio_reset(DeviceState *dev) +{ + CadenceGPIOState *s =3D CADENCE_GPIO(dev); + + s->bmr =3D 0; + s->dmr =3D 0; + s->oer =3D 0; + s->ovr =3D 0; + s->inpvr =3D 0; + s->imr =3D 0xffffffff; + s->isr =3D 0; + s->itr =3D 0; + s->ivr =3D 0; + s->ioar =3D 0; +} + +static void cdns_gpio_init(Object *obj) +{ + CadenceGPIOState *s =3D CADENCE_GPIO(obj); + + memory_region_init_io(&s->iomem, obj, &cdns_gpio_ops, s, + TYPE_CADENCE_GPIO, CDNS_GPIO_REG_SIZE); + + qdev_init_gpio_in(DEVICE(s), cdns_gpio_set, CDNS_GPIO_NUM); + qdev_init_gpio_out(DEVICE(s), s->output, CDNS_GPIO_NUM); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static void cdns_gpio_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, cdns_gpio_reset); + dc->vmsd =3D &vmstate_cdns_gpio; + dc->desc =3D "Cadence GPIO controller"; +} + +static const TypeInfo cdns_gpio_info =3D { + .name =3D TYPE_CADENCE_GPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(CadenceGPIOState), + .instance_init =3D cdns_gpio_init, + .class_init =3D cdns_gpio_class_init, +}; + +static void cdns_gpio_register_types(void) +{ + type_register_static(&cdns_gpio_info); +} + +type_init(cdns_gpio_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 6a67ee958f..0555f44b6a 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -19,3 +19,4 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('= aspeed_gpio.c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sgpio.c')) system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c')) +system_ss.add(when: 'CONFIG_CADENCE_GPIO', if_true: files('cadence_gpio.c'= )) diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index cea896b28f..80ca783a03 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -46,3 +46,8 @@ stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s ad= dr: 0x%" PRIx64 " " stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s add= r: 0x%" PRIx64 " val: 0x%" PRIx64 "" stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) = "GPIO%s from: 0x%x to: 0x%x" stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPI= O%s disconnected pins: 0x%x levels: 0x%x" + +# cadence_gpio.c +cdns_gpio_read(const char *path, uint64_t offset, uint32_t value) "%s:reg[= 0x%04" PRIx64 "] -> 0x%" PRIx32 +cdns_gpio_write(const char *path, uint64_t offset, uint64_t value) "%s:reg= [0x%04" PRIx64 "] <- 0x%04" PRIx64 +cdns_gpio_set(const char *path, int line, int level) "%s:[%d] <- %d" diff --git a/include/hw/gpio/cadence_gpio.h b/include/hw/gpio/cadence_gpio.h new file mode 100644 index 0000000000..ed3f77b894 --- /dev/null +++ b/include/hw/gpio/cadence_gpio.h @@ -0,0 +1,55 @@ +/* + * Cadence GPIO registers definition. + * + * Author: Kuan-Jui Chiu + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef CADENCE_GPIO_H +#define CADENCE_GPIO_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" + +#define TYPE_CADENCE_GPIO "cadence_gpio" +OBJECT_DECLARE_SIMPLE_TYPE(CadenceGPIOState, CADENCE_GPIO) + +#define CDNS_GPIO_REG_SIZE 0x400 +#define CDNS_GPIO_NUM 32 + +#define CDNS_GPIO_BYPASS_MODE 0x00 +#define CDNS_GPIO_DIRECTION_MODE 0x04 +#define CDNS_GPIO_OUTPUT_EN 0x08 +#define CDNS_GPIO_OUTPUT_VALUE 0x0c +#define CDNS_GPIO_INPUT_VALUE 0x10 +#define CDNS_GPIO_IRQ_MASK 0x14 +#define CDNS_GPIO_IRQ_EN 0x18 +#define CDNS_GPIO_IRQ_DIS 0x1c +#define CDNS_GPIO_IRQ_STATUS 0x20 +#define CDNS_GPIO_IRQ_TYPE 0x24 +#define CDNS_GPIO_IRQ_VALUE 0x28 +#define CDNS_GPIO_IRQ_ANY_EDGE 0x2c + +struct CadenceGPIOState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + + uint32_t bmr; + uint32_t dmr; + uint32_t oer; + uint32_t ovr; + uint32_t inpvr; + uint32_t imr; + uint32_t isr; + uint32_t itr; + uint32_t ivr; + uint32_t ioar; + qemu_irq irq; + qemu_irq output[CDNS_GPIO_NUM]; +}; + +#endif /* CADENCE_GPIO_H */ --=20 2.34.1 From nobody Sat May 30 19:21:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=axiado.com) ARC-Seal: i=2; a=rsa-sha256; t=1777540763; cv=pass; d=zohomail.com; s=zohoarc; b=ei0wt7xJLBSB08pxucGDbf8MrjBUpqmLN3y5+zyEqa3wxuqlMCSDztzst6dazgSVGsJlWxStIfd1Ak2H26kqJOx0lxaNcvzgF70w/INPiKlRkZxrpnxhmMyvEadM2Hq+PpKTBuRecQXk/mdaDzay6Ksbe+RIYjlgbw3iBObbkSU= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777540763; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Enable 8 Cadence GPIO controllers into Axiado AX3000 SoC Signed-off-by: Kuan-Jui Chiu Reviewed-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/ax3000-soc.c | 30 ++++++++++++++++++++++++++++++ include/hw/arm/ax3000-soc.h | 23 ++++++++++++++++++++++- 3 files changed, 53 insertions(+), 1 deletion(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e569d8ee9e..3adca2923c 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -697,6 +697,7 @@ config AXIADO_SOC depends on ARM select ARM_GIC select CADENCE # UART + select CADENCE_GPIO select AXIADO_SDHCI select UNIMP =20 diff --git a/hw/arm/ax3000-soc.c b/hw/arm/ax3000-soc.c index e845a64c2a..b5669cd5ba 100644 --- a/hw/arm/ax3000-soc.c +++ b/hw/arm/ax3000-soc.c @@ -59,6 +59,11 @@ static void ax3000_init(Object *obj) } =20 object_initialize_child(obj, "sdhci0", &s->sdhci0, TYPE_AXIADO_SDHCI); + + for (i =3D 0; i < AX3000_NUM_GPIOS; i++) { + g_autofree char *name =3D g_strdup_printf("gpio%d", i); + object_initialize_child(obj, name, &s->gpio[i], TYPE_CADENCE_GPIO); + } } =20 static void ax3000_realize(DeviceState *dev, Error **errp) @@ -207,6 +212,31 @@ static void ax3000_realize(DeviceState *dev, Error **e= rrp) blk_by_legacy_dinfo((drive_get(IF_SD, 0, 0))), &error_fatal); qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal); + + /* GPIOs */ + for (i =3D 0; i < AX3000_NUM_GPIOS; i++) { + struct { + hwaddr addr; + unsigned int irq; + } gpio_table[] =3D { + { AX3000_GPIO0_BASE, AX3000_GPIO0_IRQ }, + { AX3000_GPIO1_BASE, AX3000_GPIO1_IRQ }, + { AX3000_GPIO2_BASE, AX3000_GPIO2_IRQ }, + { AX3000_GPIO3_BASE, AX3000_GPIO3_IRQ }, + { AX3000_GPIO4_BASE, AX3000_GPIO4_IRQ }, + { AX3000_GPIO5_BASE, AX3000_GPIO5_IRQ }, + { AX3000_GPIO6_BASE, AX3000_GPIO6_IRQ }, + { AX3000_GPIO7_BASE, AX3000_GPIO7_IRQ } + }; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, + qdev_get_gpio_in(gic_dev, gpio_table[i].irq)); + } } =20 static void ax3000_class_init(ObjectClass *oc, const void *data) diff --git a/include/hw/arm/ax3000-soc.h b/include/hw/arm/ax3000-soc.h index 2708c9c672..aa388f79f0 100644 --- a/include/hw/arm/ax3000-soc.h +++ b/include/hw/arm/ax3000-soc.h @@ -12,6 +12,7 @@ #include "cpu.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/char/cadence_uart.h" +#include "hw/gpio/cadence_gpio.h" #include "hw/sd/axiado_sdhci.h" #include "hw/core/sysbus.h" #include "qemu/units.h" @@ -37,6 +38,15 @@ OBJECT_DECLARE_TYPE(Ax3000SoCState, Ax3000SoCClass, AX30= 00_SOC) #define AX3000_SDHCI0_BASE 0x86000000 #define AX3000_EMMC_PHY_BASE 0x80801C00 =20 +#define AX3000_GPIO0_BASE 0x80500000 +#define AX3000_GPIO1_BASE 0x80580000 +#define AX3000_GPIO2_BASE 0x80600000 +#define AX3000_GPIO3_BASE 0x80680000 +#define AX3000_GPIO4_BASE 0x80700000 +#define AX3000_GPIO5_BASE 0x80780000 +#define AX3000_GPIO6_BASE 0x80800000 +#define AX3000_GPIO7_BASE 0x80880000 + #define AX3000_TIMER_CTRL 0x8A020000 #define AX3000_PLL_BASE 0x80000000 #define CLKRST_CPU_PLL_POSTDIV_OFFSET 0x0C @@ -47,6 +57,7 @@ enum Ax3000Configuration { AX3000_NUM_IRQS =3D 224, AX3000_NUM_BANKS =3D 2, AX3000_NUM_UARTS =3D 4, + AX3000_NUM_GPIOS =3D 8, }; =20 typedef struct Ax3000SoCState { @@ -57,6 +68,7 @@ typedef struct Ax3000SoCState { MemoryRegion dram[AX3000_NUM_BANKS]; MemoryRegion pll_ctrl; CadenceUARTState uart[AX3000_NUM_UARTS]; + CadenceGPIOState gpio[AX3000_NUM_GPIOS]; AxiadoSDHCIState sdhci0; } Ax3000SoCState; =20 @@ -72,7 +84,16 @@ enum Ax3000Irqs { AX3000_UART2_IRQ =3D 114, AX3000_UART3_IRQ =3D 170, =20 - AX3000_SDHCI0_IRQ =3D 123, + AX3000_SDHCI0_IRQ =3D 123, + + AX3000_GPIO0_IRQ =3D 183, + AX3000_GPIO1_IRQ =3D 184, + AX3000_GPIO2_IRQ =3D 185, + AX3000_GPIO3_IRQ =3D 186, + AX3000_GPIO4_IRQ =3D 187, + AX3000_GPIO5_IRQ =3D 188, + AX3000_GPIO6_IRQ =3D 189, + AX3000_GPIO7_IRQ =3D 190, }; =20 #endif /* AXIADO_AX3000_H */ --=20 2.34.1