From nobody Sat May 30 19:21:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1777384912; cv=none; d=zohomail.com; s=zohoarc; b=DODd41iRrQFsKXXaW+xWz4KINm6TgMmqSxIE3Xa/jad33Hw28pCDGmgaHjNsNawbh7hjPeLLsFVI5UYLnNQl8hPQV22sPUn1fG5DWcxb4brNYt45y6VUROwkKYif5V+xy+505Y+oJf+f0wk3OewDEgNRhpSmYZyvrhJmQeF3f94= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777384912; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iSlTLr4PLNpzYhYqZJq4BJSiCn3mNgEhOyCqyA5A3xI=; b=RvuuzvNPf9Ef8G1X29tAjaIIE+ct1cANvSyZI5f/XQUE8YqxG/Q/Hdcam9FtlsG0PABEK4/DLZuWXD/Bl5ETEEmWOkZiPd44GbyUnX2Gyt3M2sATv0rRYLCSKR8128cPy0ehNIf1b0PyCmQnEX/NzrwlwM2tfJ7/bi9dwIi7kNs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777384912307842.0324751068888; Tue, 28 Apr 2026 07:01:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHizX-0003wQ-Ii; Tue, 28 Apr 2026 10:00:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHiq9-0002St-1u for qemu-devel@nongnu.org; Tue, 28 Apr 2026 09:51:05 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHiq7-0005jm-LG for qemu-devel@nongnu.org; Tue, 28 Apr 2026 09:51:04 -0400 Received: from laptop.localdomain (unknown [86.121.140.248]) by linux.microsoft.com (Postfix) with ESMTPSA id C4E6520B716D; Tue, 28 Apr 2026 06:51:01 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com C4E6520B716D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1777384263; bh=iSlTLr4PLNpzYhYqZJq4BJSiCn3mNgEhOyCqyA5A3xI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CTuFWs3C+ULWsLZQqNiBMcTvY5wxTlGD1mLcdepZ1TK6qvYFymEwAuLBT/9zdDb6J f/wa94gY826bQ1N5xDpzd6MoJMJe31gfqNi+FwjdouvQ9YYv6kyDFb9kMv3HvPVSA9 t0iEsikj4Ek0oZEeSUaZjwCmq8IZCzBleJIVEHIE= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Paolo Bonzini , Zhao Liu Subject: [PATCH 1/6] target/i386/mshv: remove duplicate function for reading vcpu registers Date: Tue, 28 Apr 2026 16:50:48 +0300 Message-ID: <20260428135053.251200-2-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260428135053.251200-1-dblanzeanu@linux.microsoft.com> References: <20260428135053.251200-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 28 Apr 2026 10:00:15 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1777384913565158500 Remove function `fetch_guest_state` because it is a duplicate function of `mshv_load_regs` function. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 4ed6e7548f..9defd05db6 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1291,25 +1291,6 @@ static int handle_pio_non_str(const CPUState *cpu, return 0; } =20 -static int fetch_guest_state(CPUState *cpu) -{ - int ret; - - ret =3D mshv_get_standard_regs(cpu); - if (ret < 0) { - error_report("Failed to get standard registers"); - return -1; - } - - ret =3D mshv_get_special_regs(cpu); - if (ret < 0) { - error_report("Failed to get special registers"); - return -1; - } - - return 0; -} - static int read_memory(const CPUState *cpu, uint64_t initial_gva, uint64_t initial_gpa, uint64_t gva, uint8_t *data, size_t len) @@ -1429,7 +1410,7 @@ static int handle_pio_str(CPUState *cpu, hv_x64_io_po= rt_intercept_message *info) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - ret =3D fetch_guest_state(cpu); + ret =3D mshv_load_regs(cpu); if (ret < 0) { error_report("Failed to fetch guest state"); return -1; --=20 2.53.0 From nobody Sat May 30 19:21:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1777384893; cv=none; d=zohomail.com; s=zohoarc; b=XyRDuKS6uVaxVjvBXjQMckYK4zvL9qs8RsdoxK1QAcggGP+dwWwuXqM0CUPmpSdRSIX7+DE1xcEhcKkdnAaAVoUoq1Pl7cuXnIO6vXuJZ8vgAUdxaTLhh0+wE6+YSVzerV7TduAuS8iqiDFc4XO7dF9DpMdEZqs5Ss6K2wLAjlE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777384893; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 28 Apr 2026 09:51:06 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHiq9-0005k3-J3 for qemu-devel@nongnu.org; Tue, 28 Apr 2026 09:51:06 -0400 Received: from laptop.localdomain (unknown [86.121.140.248]) by linux.microsoft.com (Postfix) with ESMTPSA id ABF8A20B716F; Tue, 28 Apr 2026 06:51:03 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com ABF8A20B716F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1777384265; bh=cCzS8CmGlshnbYniLVjptcNLUpofdOr25KSIqYcvxcE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KyB5dmNjNfJ1Bw9pm9mK5kPC2KH1Hm0UevPpBJhIErbdfXK4xCfAZ5tvkVP9lV/go TUQz5INk0o7ChX9a6ZG6QpTmJeALtKd51SKpVTNgjJQGKGuhnLivoroJQPzqxtiOnv 7TDkQxSVRO6WQHFXKBEI7yqEHw/9yl4WFd0vHaVs= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Paolo Bonzini , Zhao Liu Subject: [PATCH 2/6] accel/mshv: move vcpu arch specific initialization after vcpu creation Date: Tue, 28 Apr 2026 16:50:49 +0300 Message-ID: <20260428135053.251200-3-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260428135053.251200-1-dblanzeanu@linux.microsoft.com> References: <20260428135053.251200-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 28 Apr 2026 10:00:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1777384896401154100 Call mshv_arch_init_vcpu after the vcpu is created to ensure a valid vcpu fd. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Magnus Kulke --- accel/mshv/mshv-all.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index 58af674bd9..e3da583f21 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -415,13 +415,14 @@ static int mshv_init_vcpu(CPUState *cpu) int ret; =20 cpu->accel =3D g_new0(AccelCPUState, 1); - mshv_arch_init_vcpu(cpu); =20 ret =3D mshv_create_vcpu(vm_fd, vp_index, &cpu->accel->cpufd); if (ret < 0) { return -1; } =20 + mshv_arch_init_vcpu(cpu); + cpu->accel->dirty =3D true; =20 return 0; --=20 2.53.0 From nobody Sat May 30 19:21:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1777384915; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LYhAsljsNH8Fze7X7qLlONLrF6eA/2SZ4P1w+2pCowMkN91G60EYjKqvlTAXs3uDI J6bsxFO06fJsQkIpuA1xB6E5sgDXJEsbyNdTSSVneyc5CbSNDbOWIhQGc/lwUt7gXJ RDHDO1sUe9LR4faPcJc9BSfN2uFs5CJRKND3lGTs= From: =?UTF-8?q?Doru=20Bl=C3=A2nzeanu?= To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Paolo Bonzini , Zhao Liu Subject: [PATCH 3/6] include/hw/hyperv: add hv_vp_register_page struct definition Date: Tue, 28 Apr 2026 16:50:50 +0300 Message-ID: <20260428135053.251200-4-dblanzeanu@linux.microsoft.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260428135053.251200-1-dblanzeanu@linux.microsoft.com> References: <20260428135053.251200-1-dblanzeanu@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 28 Apr 2026 10:00:24 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1777384916624154100 Define the `hv_vp_register_page` structure that the linux kernel uses to allow access to vcpu registers. This structure is going to be used in later patches to access vcpu registers. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Mohamed Mediouni --- include/hw/hyperv/hvgdk_mini.h | 103 +++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index c3a8f33280..07e322865a 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -474,6 +474,109 @@ struct hv_input_assert_virtual_interrupt { uint16_t rsvd_z1; } QEMU_PACKED; =20 +/* Flags for dirty mask of hv_vp_register_page */ +enum hv_x64_register_class_type { + HV_X64_REGISTER_CLASS_GENERAL =3D 0, + HV_X64_REGISTER_CLASS_IP =3D 1, + HV_X64_REGISTER_CLASS_XMM =3D 2, + HV_X64_REGISTER_CLASS_SEGMENT =3D 3, + HV_X64_REGISTER_CLASS_FLAGS =3D 4, +}; + +#define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT 7 + +union hv_vp_register_page_interrupt_vectors { + uint64_t as_uint64; + struct { + uint8_t vector_count; + uint8_t vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT]; + }; +}; + +struct hv_vp_register_page { + uint16_t version; + uint8_t isvalid; + uint8_t rsvdz; + uint32_t dirty; + + union { + struct { + /* General purpose registers (HV_X64_REGISTER_CLASS_GENERAL) */ + union { + struct { + uint64_t rax; + uint64_t rcx; + uint64_t rdx; + uint64_t rbx; + uint64_t rsp; + uint64_t rbp; + uint64_t rsi; + uint64_t rdi; + uint64_t r8; + uint64_t r9; + uint64_t r10; + uint64_t r11; + uint64_t r12; + uint64_t r13; + uint64_t r14; + uint64_t r15; + } QEMU_PACKED; + + uint64_t gp_registers[16]; + }; + /* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */ + uint64_t rip; + /* Flags (HV_X64_REGISTER_CLASS_FLAGS) */ + uint64_t rflags; + } QEMU_PACKED; + + uint64_t registers[18]; + }; + uint8_t reserved[8]; + /* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */ + union { + struct { + struct hv_u128 xmm0; + struct hv_u128 xmm1; + struct hv_u128 xmm2; + struct hv_u128 xmm3; + struct hv_u128 xmm4; + struct hv_u128 xmm5; + } QEMU_PACKED; + + struct hv_u128 xmm_registers[6]; + }; + /* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */ + union { + struct { + struct hv_x64_segment_register es; + struct hv_x64_segment_register cs; + struct hv_x64_segment_register ss; + struct hv_x64_segment_register ds; + struct hv_x64_segment_register fs; + struct hv_x64_segment_register gs; + } QEMU_PACKED; + + struct hv_x64_segment_register segment_registers[6]; + }; + /* Misc. control registers (cannot be set via this interface) */ + uint64_t cr0; + uint64_t cr3; + uint64_t cr4; + uint64_t cr8; + uint64_t efer; + uint64_t dr7; + union hv_x64_pending_interruption_register pending_interruption; + union hv_x64_interrupt_state_register interrupt_state; + uint64_t instruction_emulation_hints; + uint64_t xfem; + + uint8_t reserved1[0x100]; + + /* Interrupts injected as part of HvCallDispatchVp. */ + union hv_vp_register_page_interrupt_vectors interrupt_vectors; +} QEMU_PACKED; + /* /dev/mshv */ #define MSHV_CREATE_PARTITION _IOW(MSHV_IOCTL, 0x00, struct mshv_create_= partition) #define MSHV_CREATE_VP _IOW(MSHV_IOCTL, 0x01, struct mshv_create_= vp) --=20 2.53.0 From nobody Sat May 30 19:21:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 28 Apr 2026 10:00:25 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1777384895994158500 When the vcpu is created, call mmap to configure access to the register pag= e. Update CPUArchState to store a pointer to the mmapped hv_vp_register_page. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Mohamed Mediouni --- target/i386/cpu.h | 3 +++ target/i386/mshv/mshv-cpu.c | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0b539155c4..0108e2157b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2016,6 +2016,9 @@ typedef struct CPUArchState { uint64_t msr_bndcfgs; uint64_t efer; =20 + /* Shared register page */ + struct hv_vp_register_page *regs_page; + /* Beginning of state preserved by INIT (dummy marker). */ struct {} start_init_save; =20 diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 9defd05db6..42b6fb1912 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1595,6 +1595,19 @@ void mshv_arch_init_vcpu(CPUState *cpu) + sizeof(hv_input_get_vp_registers) > HV_HYP_PAGE_SIZE)); =20 + + /* mmap the registers page */ + void *rp =3D mmap(NULL, page, PROT_READ | PROT_WRITE, + MAP_SHARED, mshv_vcpufd(cpu), + MSHV_VP_MMAP_OFFSET_REGISTERS * page); + if (rp =3D=3D MAP_FAILED) { + warn_report("register page mmap failed, falling back to hypercalls= : %s", + strerror(errno)); + env->regs_page =3D NULL; + } else { + env->regs_page =3D (struct hv_vp_register_page *) rp; + } + state->hvcall_args.base =3D mem; state->hvcall_args.input_page =3D mem; state->hvcall_args.output_page =3D (uint8_t *)mem + page; @@ -1608,6 +1621,11 @@ void mshv_arch_destroy_vcpu(CPUState *cpu) CPUX86State *env =3D &x86_cpu->env; AccelCPUState *state =3D cpu->accel; =20 + /* Unmap the register page */ + if (env->regs_page) { + munmap(env->regs_page, HV_HYP_PAGE_SIZE); + env->regs_page =3D NULL; + } g_free(state->hvcall_args.base); state->hvcall_args =3D (MshvHvCallArgs){0}; g_clear_pointer(&env->emu_mmio_buf, g_free); --=20 2.53.0 From nobody Sat May 30 19:21:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 28 Apr 2026 10:00:26 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1777384895955158501 Change the mshv_load_regs to use the register page when it is mmapped and is valid. Otherwise use the existing logic that uses ioctls to fetch registers. When retrieving the special registers, there are some registers that are not present in the register page: TR, LDTR, GDTR, IDTR, CR2, APIC_BASE. For this ones we still need to use ioctls to correctly fetch. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-by: Mohamed Mediouni --- target/i386/mshv/mshv-cpu.c | 137 +++++++++++++++++++++++++++++++++--- 1 file changed, 128 insertions(+), 9 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 42b6fb1912..7949493e97 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -107,6 +107,15 @@ static enum hv_register_name FPU_REGISTER_NAMES[26] = =3D { HV_X64_REGISTER_XMM_CONTROL_STATUS, }; =20 +static enum hv_register_name NON_VP_PAGE_REGISTER_NAMES[6] =3D { + HV_X64_REGISTER_TR, + HV_X64_REGISTER_LDTR, + HV_X64_REGISTER_GDTR, + HV_X64_REGISTER_IDTR, + HV_X64_REGISTER_CR2, + HV_X64_REGISTER_APIC_BASE, +}; + static int translate_gva(const CPUState *cpu, uint64_t gva, uint64_t *gpa, uint64_t flags) { @@ -401,6 +410,105 @@ static void populate_special_regs(const hv_register_a= ssoc *assocs, cpu_set_apic_base(x86cpu->apic_state, assocs[16].value.reg64); } =20 +static void mshv_get_standard_regs_vp_page(CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + + /* General Purpose Registers */ + env->regs[R_EAX] =3D env->regs_page->rax; + env->regs[R_EBX] =3D env->regs_page->rbx; + env->regs[R_ECX] =3D env->regs_page->rcx; + env->regs[R_EDX] =3D env->regs_page->rdx; + env->regs[R_ESI] =3D env->regs_page->rsi; + env->regs[R_EDI] =3D env->regs_page->rdi; + env->regs[R_ESP] =3D env->regs_page->rsp; + env->regs[R_EBP] =3D env->regs_page->rbp; + env->regs[R_R8] =3D env->regs_page->r8; + env->regs[R_R9] =3D env->regs_page->r9; + env->regs[R_R10] =3D env->regs_page->r10; + env->regs[R_R11] =3D env->regs_page->r11; + env->regs[R_R12] =3D env->regs_page->r12; + env->regs[R_R13] =3D env->regs_page->r13; + env->regs[R_R14] =3D env->regs_page->r14; + env->regs[R_R15] =3D env->regs_page->r15; + + env->eip =3D env->regs_page->rip; + env->eflags =3D env->regs_page->rflags; + rflags_to_lflags(env); +} + +static int mshv_get_special_regs_vp_page(CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + struct hv_register_assoc assocs[ARRAY_SIZE(NON_VP_PAGE_REGISTER_NAMES)= ]; + int ret; + size_t n_regs =3D ARRAY_SIZE(NON_VP_PAGE_REGISTER_NAMES); + hv_x64_segment_register seg; + + /* Populate special registers that are in the VP register page */ + env->cr[0] =3D env->regs_page->cr0; + env->cr[3] =3D env->regs_page->cr3; + env->cr[4] =3D env->regs_page->cr4; + env->efer =3D env->regs_page->efer; + cpu_set_apic_tpr(x86cpu->apic_state, env->regs_page->cr8); + + /* Segment Registers - copy from packed struct to avoid unaligned acce= ss */ + memcpy(&seg, &env->regs_page->es, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_ES]); + memcpy(&seg, &env->regs_page->cs, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_CS]); + memcpy(&seg, &env->regs_page->ss, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_SS]); + memcpy(&seg, &env->regs_page->ds, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_DS]); + memcpy(&seg, &env->regs_page->fs, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_FS]); + memcpy(&seg, &env->regs_page->gs, sizeof(hv_x64_segment_register)); + populate_segment_reg(&seg, &env->segs[R_GS]); + + /* The rest of the special registers that are not in the VP register p= age */ + for (size_t i =3D 0; i < n_regs; i++) { + assocs[i].name =3D NON_VP_PAGE_REGISTER_NAMES[i]; + } + + ret =3D get_generic_regs(cpu, assocs, n_regs); + if (ret < 0) { + error_report("failed to get non-vp-page special registers"); + return -1; + } + + /* Non-VP page registers - TR, LDTR, GDTR, IDTR, CR2, APIC_BASE */ + populate_segment_reg(&assocs[0].value.segment, &env->tr); + populate_segment_reg(&assocs[1].value.segment, &env->ldt); + + populate_table_reg(&assocs[2].value.table, &env->gdt); + populate_table_reg(&assocs[3].value.table, &env->idt); + env->cr[2] =3D assocs[4].value.reg64; + + cpu_set_apic_base(x86cpu->apic_state, assocs[5].value.reg64); + + return ret; +} + +static int mshv_get_registers_vp_page(CPUState *cpu) +{ + int ret; + + /* General Purpose Registers */ + mshv_get_standard_regs_vp_page(cpu); + + /* Special Registers - makes a hypercall */ + ret =3D mshv_get_special_regs_vp_page(cpu); + if (ret < 0) { + error_report("failed to get special registers for vp page"); + return -1; + } + + return 0; +} + =20 int mshv_get_special_regs(CPUState *cpu) { @@ -424,18 +532,29 @@ int mshv_get_special_regs(CPUState *cpu) =20 int mshv_load_regs(CPUState *cpu) { + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; int ret; =20 - ret =3D mshv_get_standard_regs(cpu); - if (ret < 0) { - error_report("Failed to load standard registers"); - return -1; - } + /* Use register vp page to optimize registers access */ + if (env->regs_page && env->regs_page->isvalid !=3D 0) { + ret =3D mshv_get_registers_vp_page(cpu); + if (ret < 0) { + error_report("Failed to load registers from vp page"); + return -1; + } + } else { + ret =3D mshv_get_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to load standard registers"); + return -1; + } =20 - ret =3D mshv_get_special_regs(cpu); - if (ret < 0) { - error_report("Failed to load special registers"); - return -1; + ret =3D mshv_get_special_regs(cpu); + if (ret < 0) { + error_report("Failed to load special registers"); + return -1; + } } =20 return 0; --=20 2.53.0 From nobody Sat May 30 19:21:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1777384899; cv=none; d=zohomail.com; s=zohoarc; b=RdttyOMoBtzQxMHvGgOCXvIUqljvG/QRfJ+dT0eySHq67WjpxLXqA7wzxOsgIxbXbPp4EclRXRcF1224QNPwy/Rv+j7ubdIjGkdiarIcGmDmnF8uzla8Qj7rjtX+Ik/ro+amMsMUVkEc9EKSUGTmRrJ2wWI9dDxws1p5/qM+dqE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777384899; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=dblanzeanu@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 28 Apr 2026 10:00:29 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1777384902163154100 Update mshv_store_regs to use the register page when it is mmapped and valid to set registers. Otherwise use the ioctls to set the registers. Signed-off-by: Doru Bl=C3=A2nzeanu Reviewed-By: Magnus Kulke Reviewed-by: Mohamed Mediouni --- target/i386/mshv/mshv-cpu.c | 45 +++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 7949493e97..6bb3e6d4a9 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -294,14 +294,51 @@ static int set_standard_regs(const CPUState *cpu) return 0; } =20 +static void mshv_set_standard_regs_vp_page(CPUState *cpu) +{ + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; + + env->regs_page->rax =3D env->regs[R_EAX]; + env->regs_page->rbx =3D env->regs[R_EBX]; + env->regs_page->rcx =3D env->regs[R_ECX]; + env->regs_page->rdx =3D env->regs[R_EDX]; + env->regs_page->rsi =3D env->regs[R_ESI]; + env->regs_page->rdi =3D env->regs[R_EDI]; + env->regs_page->rsp =3D env->regs[R_ESP]; + env->regs_page->rbp =3D env->regs[R_EBP]; + env->regs_page->r8 =3D env->regs[R_R8]; + env->regs_page->r9 =3D env->regs[R_R9]; + env->regs_page->r10 =3D env->regs[R_R10]; + env->regs_page->r11 =3D env->regs[R_R11]; + env->regs_page->r12 =3D env->regs[R_R12]; + env->regs_page->r13 =3D env->regs[R_R13]; + env->regs_page->r14 =3D env->regs[R_R14]; + env->regs_page->r15 =3D env->regs[R_R15]; + env->regs_page->rip =3D env->eip; + lflags_to_rflags(env); + env->regs_page->rflags =3D env->eflags; + + env->regs_page->dirty |=3D (1u << HV_X64_REGISTER_CLASS_GENERAL) + | (1u << HV_X64_REGISTER_CLASS_IP) + | (1u << HV_X64_REGISTER_CLASS_FLAGS); +} + int mshv_store_regs(CPUState *cpu) { + X86CPU *x86cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86cpu->env; int ret; =20 - ret =3D set_standard_regs(cpu); - if (ret < 0) { - error_report("Failed to store standard registers"); - return -1; + /* Use register vp page to optimize registers access */ + if (env->regs_page && env->regs_page->isvalid !=3D 0) { + mshv_set_standard_regs_vp_page(cpu); + } else { + ret =3D set_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to store standard registers"); + return -1; + } } =20 return 0; --=20 2.53.0