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The co-processor syndromes are split between single and duel register moves. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 124 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 102 insertions(+), 22 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 517fb2368b..29462aa103 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -78,7 +78,7 @@ enum arm_exception_class { =20 /* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */ FIELD(SYNDROME, EC, 26, 6) -FIELD(SYNDROME, IL, 25, 1) +FIELD(SYNDROME, IL, 25, 1) /* IL=3D1 for 32 bit instructions */ FIELD(SYNDROME, ISS, 0, 25) =20 typedef enum { @@ -172,7 +172,7 @@ static inline uint32_t syn_aa64_smc(uint32_t imm16) static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) { uint32_t res =3D syn_set_ec(0, EC_AA32_SVC); - res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); return res; } @@ -203,58 +203,138 @@ static inline uint32_t syn_aa64_bkpt(uint32_t imm16) static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) { uint32_t res =3D syn_set_ec(0, EC_AA32_BKPT); - res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); return res; } =20 +/* + * ISS encoding for an exception from MSR, MRS, or System instruction + * in AArch64 state. + */ +FIELD(SYSREG_ISS, ISREAD, 0, 1) /* Direction, 1 is read */ +FIELD(SYSREG_ISS, CRM, 1, 4) +FIELD(SYSREG_ISS, RT, 5, 5) +FIELD(SYSREG_ISS, CRN, 10, 4) +FIELD(SYSREG_ISS, OP1, 14, 3) +FIELD(SYSREG_ISS, OP2, 17, 3) +FIELD(SYSREG_ISS, OP0, 20, 2) + static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, int crn, int crm, int rt, int isread) { - return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) - | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_SYSTEMREGISTERTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, SYSREG_ISS, OP0, op0); + res =3D FIELD_DP32(res, SYSREG_ISS, OP2, op2); + res =3D FIELD_DP32(res, SYSREG_ISS, OP1, op1); + res =3D FIELD_DP32(res, SYSREG_ISS, CRN, crn); + res =3D FIELD_DP32(res, SYSREG_ISS, RT, rt); + res =3D FIELD_DP32(res, SYSREG_ISS, CRM, crm); + res =3D FIELD_DP32(res, SYSREG_ISS, ISREAD, isread); + + return res; } =20 +/* + * ISS encoding for an exception from an MCR or MRC access + * (move to/from co-processor) + */ +FIELD(COPROC_ISS, ISREAD, 0, 1) +FIELD(COPROC_ISS, CRM, 1, 4) +FIELD(COPROC_ISS, RT, 5, 5) +FIELD(COPROC_ISS, CRN, 10, 4) +FIELD(COPROC_ISS, OP1, 14, 3) +FIELD(COPROC_ISS, OP2, 17, 3) +FIELD(COPROC_ISS, COND, 20, 4) +FIELD(COPROC_ISS, CV, 24, 1) + static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int op= c2, int crn, int crm, int rt, int isre= ad, bool is_16bit) { - return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP14RTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, COPROC_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_ISS, OP2, opc2); + res =3D FIELD_DP32(res, COPROC_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_ISS, CRN, crn); + res =3D FIELD_DP32(res, COPROC_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int op= c2, int crn, int crm, int rt, int isre= ad, bool is_16bit) { - return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP15RTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, COPROC_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_ISS, OP2, opc2); + res =3D FIELD_DP32(res, COPROC_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_ISS, CRN, crn); + res =3D FIELD_DP32(res, COPROC_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_ISS, ISREAD, isread); + + return res; } =20 +/* + * ISS encoding for an exception from an MCRR or MRRC access + * (move to/from co-processor with 2 regs) + */ +FIELD(COPROC_R2_ISS, ISREAD, 0, 1) +FIELD(COPROC_R2_ISS, CRM, 1, 4) +FIELD(COPROC_R2_ISS, RT, 5, 5) +FIELD(COPROC_R2_ISS, RT2, 10, 5) +FIELD(COPROC_R2_ISS, OP1, 16, 4) +FIELD(COPROC_R2_ISS, COND, 20, 4) +FIELD(COPROC_R2_ISS, CV, 24, 1) + static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int c= rm, int rt, int rt2, int isread, bool is_16bit) { - return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP14RRTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, COPROC_R2_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_R2_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_R2_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int c= rm, int rt, int rt2, int isread, bool is_16bit) { - return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP15RRTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, COPROC_R2_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_R2_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_R2_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, --=20 2.43.0