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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294098; x=1777898898; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YcYVYYNIRSP1snD5TdIYSPjOwpX5L7NMhYaBvEW9/ZM=; b=nRmmEamjySujWYaZNUHRrIEyHD5H0pmhkgx4W5S3I01EVUtaCfPxsWDWsYL0i9ZU5v 6AkJHUtlrI3eYpvMgOV/9xObp9eg2xVAfpLbdHCN8dhVTjrDxUT899y7ntt1Es1Fs1zI /hHuzEHHgBkSR05Gc5/xNx88/6ylKmiA3XdEW1vayWfZERpLVGKxwsByjKUz13E1MJ0H Vt0zE0E4p8V+2YmfKqWgcTkqM3ufK7OtkKn6V088BI/9Rnb/LX54B+0Ia3x4UYOq9Wwu ui0Qvuz5XZZuYww4d/Rbgwydhn/bdyRlbjatyOSlrlb/15wIpAgQehSmh2dmr2UYwIvR 26qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294098; x=1777898898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=YcYVYYNIRSP1snD5TdIYSPjOwpX5L7NMhYaBvEW9/ZM=; b=TYxupQW4IrnGitr3uc7/K96mvTy/u7MCCKXz7gx9gY+Q82Fd53YiM4mMz9MC2/2zoV 44xNlezRJZYYws2azfRSPpt3gN4+2dqdowYgN5dZvCsRVGCYeMDQKTcGcSpdsxpDiSo+ bIemaNnorAN7AjGS2fHdso3/5cEHygYi3O3eYb9E77sCidULR1OHcZulbWMWZD9yREKo Ph39PxHTfSGyqjCPO1O79/rXzaSx7e4IF8RxHrX8C9Fi1n+YujdPJ/lyRweYAcrxmbIM oh0OH6JqAmUC5NCUpzbYzWQrahaQoamq5t3D8b4osW3ipSUOP12d5VVQ66x9fI6lKnnS TjtQ== X-Gm-Message-State: AOJu0Yxlxh4eVg7iXd6aBytwX1yf3jR7SjHkCZu8yeUDYpmX/4hOmU34 KNWIfHQAQ5Mar0VSVviPiZH+rvwIXM3o+GHKjwJWKDHknpzHCT53GeL5TBX+LVdzep4jDItyukh hamsP X-Gm-Gg: AeBDieuVNPecX3tVFCmweYsGPa7FB0Z8/XY0uBw24J9b2vhIh7EvJIP7viNJxnWb10O wR5Mv13LZ8BX1A31EAphCdhZtF/NZXkDNRDMNIj7pCz76uqxDiHxxNtxj46XeVeQkC2euI1B8wS 5xSPGVVbwvLHWIXDlhIqj+6WtqmCzXNcCQzA6WAA8NYDKWc2xG5d7R0oImK2Q4wYCEcDuG18No4 YRECZRU8poLY7of3dolhfv1ooWGPYMX6gAoRzChEaH3G173cqkkqb6aadsR/G1ba7K0WMrZlKoR TPwzKK1DTr9j4W4PN022O1z06RtJUGUWCG5tmUtvqE39yS9JrW0Pt7JKKkv6bX+/EO52oMuEcAS rSk+DJNl8OGepZEQ5FZ3d2pnAHre1Dxoj/u6Fqfj+9Q7vWQdzj9+cLAk6NHEy50WmvkDQ0ruQHE yHCJyboM8MKquiIY+mc4Rk/xY1fB3fsQc7gEUUYVQBt/bCpe9O/lNDV7iZ2wvR0R009noYpILeM 5DI9J9/U8vGlaAY2Lvo1kyMyUcQn/IA20uTu437cA== X-Received: by 2002:a05:600c:1d05:b0:489:1baf:8c03 with SMTP id 5b1f17b1804b1-4891baf8d2cmr441990475e9.11.1777294097635; Mon, 27 Apr 2026 05:48:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/63] target/arm: migrate basic syndrome helpers to registerfields Date: Mon, 27 Apr 2026 13:47:15 +0100 Message-ID: <20260427124738.966578-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294746171154100 From: Alex Benn=C3=A9e We have a registerfields interface which we can use for defining fields alongside helpers to access them. Define the basic syndrome layout and convert the helpers that take the imm16 data directly. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 75 ++++++++++++++++++++++++++++++++----------- 1 file changed, 57 insertions(+), 18 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index bff61f052c..517fb2368b 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -25,7 +25,7 @@ #ifndef TARGET_ARM_SYNDROME_H #define TARGET_ARM_SYNDROME_H =20 -#include "qemu/bitops.h" +#include "hw/core/registerfields.h" =20 /* Valid Syndrome Register EC field values */ enum arm_exception_class { @@ -76,6 +76,11 @@ enum arm_exception_class { EC_AA64_BKPT =3D 0x3c, }; =20 +/* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */ +FIELD(SYNDROME, EC, 26, 6) +FIELD(SYNDROME, IL, 25, 1) +FIELD(SYNDROME, ISS, 0, 25) + typedef enum { SME_ET_AccessTrap, SME_ET_Streaming, @@ -113,12 +118,12 @@ typedef enum { =20 static inline uint32_t syn_get_ec(uint32_t syn) { - return syn >> ARM_EL_EC_SHIFT; + return FIELD_EX32(syn, SYNDROME, EC); } =20 static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec) { - return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec); + return FIELD_DP32(syn, SYNDROME, EC, ec); } =20 /* @@ -133,49 +138,74 @@ static inline uint32_t syn_set_ec(uint32_t syn, uint3= 2_t ec) */ static inline uint32_t syn_uncategorized(void) { - return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_UNCATEGORIZED); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 +FIELD(ISS_IMM16, IMM16, 0, 16) + static inline uint32_t syn_aa64_svc(uint32_t imm16) { - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_SVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_hvc(uint32_t imm16) { - return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_HVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_smc(uint32_t imm16) { - return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_SMC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) { - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); + uint32_t res =3D syn_set_ec(0, EC_AA32_SVC); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_hvc(uint32_t imm16) { - return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA32_HVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_smc(void) { - return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_AA32_SMC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) { - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff= ); + uint32_t res =3D syn_set_ec(0, EC_AA64_BKPT); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) { - return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); + uint32_t res =3D syn_set_ec(0, EC_AA32_BKPT); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, @@ -246,7 +276,9 @@ static inline uint32_t syn_simd_access_trap(int cv, int= cond, bool is_16bit) =20 static inline uint32_t syn_sve_access_trap(void) { - return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_SVEACCESSTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 /* @@ -361,12 +393,16 @@ static inline uint32_t syn_wfx(int cv, int cond, int = ti, bool is_16bit) =20 static inline uint32_t syn_illegalstate(void) { - return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_ILLEGALSTATE); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_pcalignment(void) { - return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_PCALIGNMENT); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn) @@ -388,7 +424,10 @@ static inline uint32_t syn_gcs_gcsstr(int ra, int rn) =20 static inline uint32_t syn_serror(uint32_t extra) { - return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; + uint32_t res =3D syn_set_ec(0, EC_SERROR); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, SYNDROME, ISS, extra); + return res; } =20 static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, --=20 2.43.0