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Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/arm); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260414005348.4767-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/m_helper.c | 6 +-- target/arm/tcg/mve_helper.c | 79 ++++++++++++++++++++----------------- 2 files changed, 45 insertions(+), 40 deletions(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index a0cb8cb021..f5954ce9bf 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -634,7 +634,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) =20 /* Note that these stores can throw exceptions on MPU faults */ ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); cpu_stl_mmu(env, sp, nextinst, oi, GETPC()); cpu_stl_mmu(env, sp + 4, saved_psr, oi, GETPC()); @@ -1055,7 +1055,7 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fpt= r) bool lspact =3D env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; uintptr_t ra =3D GETPC(); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); =20 assert(env->v7m.secure); @@ -1131,7 +1131,7 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) ARMCPU *cpu =3D env_archcpu(env); uintptr_t ra =3D GETPC(); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); =20 /* fptr is the value of Rn, the frame pointer we load the FP regs from= */ diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index a67d90d6c7..cc58e0502f 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -194,23 +194,23 @@ static void mve_advance_vpt(CPUARMState *env) } =20 DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t) -DO_VLDR(vldrh, MO_TEUW, 2, uint16_t, ldw, 2, uint16_t) -DO_VLDR(vldrw, MO_TEUL, 4, uint32_t, ldl, 4, uint32_t) +DO_VLDR(vldrh, MO_TE | MO_UW, 2, uint16_t, ldw, 2, uint16_t) +DO_VLDR(vldrw, MO_TE | MO_UL, 4, uint32_t, ldl, 4, uint32_t) =20 DO_VSTR(vstrb, MO_UB, 1, stb, 1, uint8_t) -DO_VSTR(vstrh, MO_TEUW, 2, stw, 2, uint16_t) -DO_VSTR(vstrw, MO_TEUL, 4, stl, 4, uint32_t) +DO_VSTR(vstrh, MO_TE | MO_UW, 2, stw, 2, uint16_t) +DO_VSTR(vstrw, MO_TE | MO_UL, 4, stl, 4, uint32_t) =20 DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t) DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t) DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t) DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t) -DO_VLDR(vldrh_sw, MO_TESW, 2, int16_t, ldw, 4, int32_t) -DO_VLDR(vldrh_uw, MO_TEUW, 2, uint16_t, ldw, 4, uint32_t) +DO_VLDR(vldrh_sw, MO_TE | MO_SW, 2, int16_t, ldw, 4, int32_t) +DO_VLDR(vldrh_uw, MO_TE | MO_UW, 2, uint16_t, ldw, 4, uint32_t) =20 DO_VSTR(vstrb_h, MO_UB, 1, stb, 2, int16_t) DO_VSTR(vstrb_w, MO_UB, 1, stb, 4, int32_t) -DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) +DO_VSTR(vstrh_w, MO_TE | MO_UW, 2, stw, 4, int32_t) =20 #undef DO_VLDR #undef DO_VSTR @@ -295,7 +295,7 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ if (!(eci_mask & 1)) { \ continue; \ @@ -321,7 +321,7 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ if (!(eci_mask & 1)) { \ continue; \ @@ -345,42 +345,47 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) =20 DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD= , false) DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD= , false) -DO_VLDR_SG(vldrh_sg_sw, MO_TESW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_= ADD, false) +DO_VLDR_SG(vldrh_sg_sw, MO_TE | MO_SW, int16_t, ldw, 4, + int32_t, uint32_t, ADDR_ADD, false) =20 DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD= , false) DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_A= DD, false) DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_A= DD, false) -DO_VLDR_SG(vldrh_sg_uh, MO_TEUW, uint16_t, ldw, 2, uint16_t, uint16_t, ADD= R_ADD, false) -DO_VLDR_SG(vldrh_sg_uw, MO_TEUW, uint16_t, ldw, 4, uint32_t, uint32_t, ADD= R_ADD, false) -DO_VLDR_SG(vldrw_sg_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADD= R_ADD, false) +DO_VLDR_SG(vldrh_sg_uh, MO_TE | MO_UW, uint16_t, ldw, 2, + uint16_t, uint16_t, ADDR_ADD, false) +DO_VLDR_SG(vldrh_sg_uw, MO_TE | MO_UW, uint16_t, ldw, 4, + uint32_t, uint32_t, ADDR_ADD, false) +DO_VLDR_SG(vldrw_sg_uw, MO_TE | MO_UL, uint32_t, ldl, 4, + uint32_t, uint32_t, ADDR_ADD, false) DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) =20 -DO_VLDR_SG(vldrh_sg_os_sw, MO_TESW, int16_t, ldw, 4, +DO_VLDR_SG(vldrh_sg_os_sw, MO_TE | MO_SW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrh_sg_os_uh, MO_TEUW, uint16_t, ldw, 2, +DO_VLDR_SG(vldrh_sg_os_uh, MO_TE | MO_UW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrh_sg_os_uw, MO_TEUW, uint16_t, ldw, 4, +DO_VLDR_SG(vldrh_sg_os_uw, MO_TE | MO_UW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrw_sg_os_uw, MO_TEUL, uint32_t, ldl, 4, +DO_VLDR_SG(vldrw_sg_os_uw, MO_TE | MO_UL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false) DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) =20 DO_VSTR_SG(vstrb_sg_ub, MO_UB, stb, 1, uint8_t, ADDR_ADD, false) DO_VSTR_SG(vstrb_sg_uh, MO_UB, stb, 2, uint16_t, ADDR_ADD, false) DO_VSTR_SG(vstrb_sg_uw, MO_UB, stb, 4, uint32_t, ADDR_ADD, false) -DO_VSTR_SG(vstrh_sg_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD, false) -DO_VSTR_SG(vstrh_sg_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD, false) -DO_VSTR_SG(vstrw_sg_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrw_sg_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, false) DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) =20 -DO_VSTR_SG(vstrh_sg_os_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD_OSH, false) -DO_VSTR_SG(vstrh_sg_os_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD_OSH, false) -DO_VSTR_SG(vstrw_sg_os_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD_OSW, false) +DO_VSTR_SG(vstrh_sg_os_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD_OSH, = false) +DO_VSTR_SG(vstrh_sg_os_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD_OSH, = false) +DO_VSTR_SG(vstrw_sg_os_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD_OSW, = false) DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) =20 -DO_VLDR_SG(vldrw_sg_wb_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, = ADDR_ADD, true) +DO_VLDR_SG(vldrw_sg_wb_uw, MO_TE | MO_UL, uint32_t, ldl, 4, + uint32_t, uint32_t, ADDR_ADD, true) DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) -DO_VSTR_SG(vstrw_sg_wb_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, true) +DO_VSTR_SG(vstrw_sg_wb_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, true) DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) =20 /* @@ -408,7 +413,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ uint32_t addr, data; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -434,7 +439,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) int y; /* y counts 0 2 0 2 */ \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -461,7 +466,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) uint32_t *qd; \ int y; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -500,7 +505,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) uint32_t addr, data; \ uint8_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -526,7 +531,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) int e; \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -551,7 +556,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) uint32_t addr, data; \ uint32_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -582,7 +587,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ uint32_t addr, data; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -609,7 +614,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) int y; /* y counts 0 2 0 2 */ \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -635,7 +640,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) uint32_t *qd; \ int y; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -674,7 +679,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) uint32_t addr, data; \ uint8_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -701,7 +706,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) int e; \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -727,7 +732,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) uint32_t addr, data; \ uint32_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ --=20 2.43.0