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Mon, 27 Apr 2026 05:47:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/63] hw/arm/fsl-imx8mm: Add GPIO controllers Date: Mon, 27 Apr 2026 13:46:43 +0100 Message-ID: <20260427124738.966578-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294246795154100 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma Enabled GPIO controller emulation Also updated the GPIO IRQ lines of iMX8MM Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/fsl-imx8mm.c | 54 +++++++++++++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 14 ++++++++++ 2 files changed, 68 insertions(+) diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 633b121630..85bce5a788 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -180,6 +180,11 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_GPIOS; i++) { + g_autofree char *name =3D g_strdup_printf("gpio%d", i + 1); + object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); + } + for (i =3D 0; i < FSL_IMX8MM_NUM_USDHCS; i++) { g_autofree char *name =3D g_strdup_printf("usdhc%d", i + 1); object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); @@ -365,6 +370,54 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr, &s->ocram); =20 + /* GPIOs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_GPIOS; i++) { + static const struct { + hwaddr addr; + unsigned int irq_low; + unsigned int irq_high; + } gpio_table[FSL_IMX8MM_NUM_GPIOS] =3D { + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO1].addr, + FSL_IMX8MM_GPIO1_LOW_IRQ, + FSL_IMX8MM_GPIO1_HIGH_IRQ + }, + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO2].addr, + FSL_IMX8MM_GPIO2_LOW_IRQ, + FSL_IMX8MM_GPIO2_HIGH_IRQ + }, + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO3].addr, + FSL_IMX8MM_GPIO3_LOW_IRQ, + FSL_IMX8MM_GPIO3_HIGH_IRQ + }, + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO4].addr, + FSL_IMX8MM_GPIO4_LOW_IRQ, + FSL_IMX8MM_GPIO4_HIGH_IRQ + }, + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO5].addr, + FSL_IMX8MM_GPIO5_LOW_IRQ, + FSL_IMX8MM_GPIO5_HIGH_IRQ + }, + }; + object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, + &error_abort); + object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", + true, &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, + qdev_get_gpio_in(gicdev, gpio_table[i].irq_low)= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, + qdev_get_gpio_in(gicdev, gpio_table[i].irq_high= )); + } + /* USDHCs */ for (i =3D 0; i < FSL_IMX8MM_NUM_USDHCS; i++) { static const struct { @@ -423,6 +476,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_CCM: case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: + case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5: case FSL_IMX8MM_PCIE1: case FSL_IMX8MM_PCIE_PHY1: case FSL_IMX8MM_RAM: diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 3181c02574..4fe27b9575 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -12,6 +12,7 @@ =20 #include "cpu.h" #include "hw/char/imx_serial.h" +#include "hw/gpio/imx_gpio.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" @@ -30,6 +31,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM) =20 enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_CPUS =3D 4, + FSL_IMX8MM_NUM_GPIOS =3D 5, FSL_IMX8MM_NUM_IRQS =3D 128, FSL_IMX8MM_NUM_UARTS =3D 4, FSL_IMX8MM_NUM_USDHCS =3D 3, @@ -40,6 +42,7 @@ struct FslImx8mmState { =20 ARMCPU cpu[FSL_IMX8MM_NUM_CPUS]; GICv3State gic; + IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS]; IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMX7SNVSState snvs; @@ -171,6 +174,17 @@ enum FslImx8mmIrqs { FSL_IMX8MM_UART3_IRQ =3D 28, FSL_IMX8MM_UART4_IRQ =3D 29, =20 + FSL_IMX8MM_GPIO1_LOW_IRQ =3D 64, + FSL_IMX8MM_GPIO1_HIGH_IRQ =3D 65, + FSL_IMX8MM_GPIO2_LOW_IRQ =3D 66, + FSL_IMX8MM_GPIO2_HIGH_IRQ =3D 67, + FSL_IMX8MM_GPIO3_LOW_IRQ =3D 68, + FSL_IMX8MM_GPIO3_HIGH_IRQ =3D 69, + FSL_IMX8MM_GPIO4_LOW_IRQ =3D 70, + FSL_IMX8MM_GPIO4_HIGH_IRQ =3D 71, + FSL_IMX8MM_GPIO5_LOW_IRQ =3D 72, + FSL_IMX8MM_GPIO5_HIGH_IRQ =3D 73, + FSL_IMX8MM_PCI_INTA_IRQ =3D 122, FSL_IMX8MM_PCI_INTB_IRQ =3D 123, FSL_IMX8MM_PCI_INTC_IRQ =3D 124, --=20 2.43.0