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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.47.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:47:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294060; x=1777898860; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fMqIfKVMLj1oTZTKwDNNLVPnYy0OK2XdZ9Xj1/3bKSY=; b=n76StaKCZQGT4Fw50HQfha2zTO5e6+NliDICipJzHRxie5tDuXrZOdr2XwRtXrcYbs nA0P5wJiu3Y85lqWdVHJZWWg3gTO10k6bLtwQkSBreEFimIS7BmO49GIiTX/IFY5h4Lv fveyCkP6nFPkutBQShgiFHK9wD+VHXyLoxTO1UmlunSDWyhcXYV4I1vjqB7aTp0TPUGS mEiwFn5I8ArSTWr92Mq30VZAV4gFmEBj1ezT4owibcfO2hPpHeYJ2DhQrVeQLBii2kbU Uys/w9Km+hxWenSuYOpoHHHxqzSBAtyulEZQDWm6UBJxkO0I3IJpy9RsqedCIuLzqbM9 lQEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294060; x=1777898860; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=fMqIfKVMLj1oTZTKwDNNLVPnYy0OK2XdZ9Xj1/3bKSY=; b=fIfo1lC8/Z/nyxA9K2KU/oc1LraHhcJFQRadUHpM6nlPXVYp3QBzKE/zrZ4fsk7kzW y4cHzzTGYQOT68e4ZycotlwkVV0QuFkI0Lb0APpl8e56fvlP0VggzIMZ2KckyNLJ9KZI alMIvxSvePYrrR5vPXJ9OvpKZmHydD+Qp09nYN/Yz49mrBfq0VHan0Z4Uj85/IYQWCg6 NC/xazTjilZaQcUD2EMLyO7Lu7dlLZbNnPRjWPJrGRAjk5qUW04CfSIU9fcVnsVOYbL4 RrHuoj8c7TGv+cMiiBPuyFMss+0VdluSZr+uW9fpup7rh7QM7lIWn7ShnCFX2s0pwxKy yOAA== X-Gm-Message-State: AOJu0YwSERFooFPbP3WTuPuq3s86A93qizva6LVQM5KtjX3MrrGo1gcr JJMHVxpwIbEtTNqIjWLV9DxSV6NQM2ARxoqQEgb0Ilocy7TG4YXXOLP6K9mP1uZuXLXc2VX9R2b WmbJi X-Gm-Gg: AeBDieuiuCH3bwiNgftpPa90AbdzGi2eZwx9iUu5d9s8E3Ye4jubuvk9vFcZ8WIL1Vc k/PVnSbWLN/KURYKP1Rs3mx7VoXMEY55DqcTFynx4fCmJFbnZFncXj56zfTP1K579jaHjfgmQ74 xZpWmjFFzCF3AD7JfB5+rAp+HLCVZlRFVgBJtMhu9dHLTn8suwYKVjYOHACSa9s12L+aP+r8/4G vN8vWWAc+Pz8nqTnmEO3KQZHte2KTsK6Bdgh8DDnvyxSmuryZnE9vSk7J/PuaJ3IYppXogRu2vN WNuu7HqpEKR0xo3vPr331kQojgS5UwYHCETBymKIxHHlZeTtf7FbN1j+RXVCL396jSCrcifTFk7 /T9u3rno6hYLSPiB/XLaGc8sfOXBUTr+pcs8Kd7L4vgSc0YTtVLvaoJFY8ag39VufIk+zKwLmsY COVFcgfE2IWuF0R0/Qv+zeiHyvdVXx+VtATAVb2Ort+F4ETSPbPrJBuq/DQUuZOco/MZM/znQhL itA4MGJVGxRABez1X86bEil4+hjReJ8G4cf0obYDw== X-Received: by 2002:a05:600c:c4a1:b0:488:c014:34da with SMTP id 5b1f17b1804b1-488fb77ed1bmr582973345e9.26.1777294060364; Mon, 27 Apr 2026 05:47:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/63] docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list Date: Mon, 27 Apr 2026 13:46:35 +0100 Message-ID: <20260427124738.966578-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294616216154100 From: Alex Benn=C3=A9e This is just a documentation tweak as we already support both. FEAT_AA32 implies FEAT_AA32EL0. FEAT_AA64 implies FEAT_AA64EL[0123]. This is however useful if you are using emulation.rst as a source of truth of what QEMU emulates and when cross checking with Features.json from Arm. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20260421093506.616307-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 7787691853..8cd7fe7b00 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -7,6 +7,7 @@ QEMU's TCG emulation includes support for the Armv5, Armv6,= Armv7, Armv8 and Armv9 versions of the A-profile architecture. It also has suppor= t for the following architecture extensions: =20 +- FEAT_AA32 (PE Support for AArch32) - FEAT_AA32BF16 (AArch32 BFloat16 instructions) - FEAT_AA32EL0 (Support for AArch32 at EL0) - FEAT_AA32EL1 (Support for AArch32 at EL1) @@ -14,6 +15,7 @@ the following architecture extensions: - FEAT_AA32EL3 (Support for AArch32 at EL3) - FEAT_AA32HPD (AArch32 hierarchical permission disables) - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) +- FEAT_AA64 (PE uses AArch64 after last reboot) - FEAT_AA64EL0 (Support for AArch64 at EL0) - FEAT_AA64EL1 (Support for AArch64 at EL1) - FEAT_AA64EL2 (Support for AArch64 at EL2) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294126; cv=none; d=zohomail.com; s=zohoarc; b=fcgfIfWA9Plq5bFP29dKsgZ9eqEhfKftRP8gxoaIaJTnWpOx55bvqJ2EgCiW1/Yn5af1XIjf0HsttsKE8hAfaduAM1HFyiYCBW93ejj+icqKnTFMaW2uAqiFiepvCwC4W1VsqQz9fLNKsspvQT6RRRDvzGmlkJ0JjKv1T7sSMvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294126; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=HXsLmW2jGYoRiDIuLlRkqP/OZldqurSl8UauGyt6qB0=; b=gVHk1ZKBqQnXIqR+URImyr9icgmzRoBMtLvjmNZOftR5ELi6MfocvEQRzMKhmp0Mn5/jx3ykH4VdFmtYX0nsMD2VNJmCsOLoFjVqAONuJPSe1zY14j6T7csL0kfmNFzBUyQt02qRjRboC5uM1TsldMMDSoC0jTNB4RDOmgMgJus= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294126214485.1784881016316; Mon, 27 Apr 2026 05:48:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLO8-00089i-P5; Mon, 27 Apr 2026 08:48:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNL-0007lG-9D for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNG-0005Pc-W7 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:46 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-488a88aeec9so127015785e9.2 for ; Mon, 27 Apr 2026 05:47:42 -0700 (PDT) Received: from lanath.. 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Set default RAM size to 2GB and default CPU count to 4 to match the real i.MX8MM EVK hardware configuration. Documentation is shared with imx8mp-evk to avoid duplication. Signed-off-by: Gaurav Sharma [PMM: fixed over-long lines in doc] Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Peter Maydell --- MAINTAINERS | 11 +- docs/system/arm/{imx8mp-evk.rst =3D> imx8m.rst} | 49 ++- docs/system/target-arm.rst | 2 +- hw/arm/Kconfig | 12 + hw/arm/fsl-imx8mm.c | 377 ++++++++++++++++++ hw/arm/imx8mm-evk.c | 112 ++++++ hw/arm/meson.build | 2 + include/hw/arm/fsl-imx8mm.h | 158 ++++++++ 8 files changed, 709 insertions(+), 14 deletions(-) rename docs/system/arm/{imx8mp-evk.rst =3D> imx8m.rst} (58%) create mode 100644 hw/arm/fsl-imx8mm.c create mode 100644 hw/arm/imx8mm-evk.c create mode 100644 include/hw/arm/fsl-imx8mm.h diff --git a/MAINTAINERS b/MAINTAINERS index 35529266a2..8167d42876 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -913,6 +913,15 @@ F: hw/pci-host/designware.c F: include/hw/pci-host/designware.h F: docs/system/arm/mcimx7d-sabre.rst =20 +MCIMX8MM-EVK / iMX8MM +M: Gaurav Sharma +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/fsl-imx8mm.c +F: hw/arm/imx8mm-evk.c +F: include/hw/arm/fsl-imx8mm.h +F: docs/system/arm/imx8m.rst + MCIMX8MP-EVK / i.MX8MP M: Bernhard Beschow L: qemu-arm@nongnu.org @@ -925,7 +934,7 @@ F: hw/rtc/rs5c372.c F: include/hw/arm/fsl-imx8mp.h F: include/hw/misc/imx8mp_*.h F: include/hw/pci-host/fsl_imx8m_phy.h -F: docs/system/arm/imx8mp-evk.rst +F: docs/system/arm/imx8m.rst F: tests/functional/aarch64/test_imx8mp_evk.py F: tests/qtest/rs5c372-test.c =20 diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8m.rst similarity index 58% rename from docs/system/arm/imx8mp-evk.rst rename to docs/system/arm/imx8m.rst index e60a422824..afbc33b2f4 100644 --- a/docs/system/arm/imx8mp-evk.rst +++ b/docs/system/arm/imx8m.rst @@ -1,13 +1,15 @@ -NXP i.MX 8M Plus Evaluation Kit (``imx8mp-evk``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +NXP i.MX 8M Plus and i.MX 8M Mini Evaluation Kits (``imx8mp-evk``, ``imx8m= m-evk``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =20 -The ``imx8mp-evk`` machine models the i.MX 8M Plus Evaluation Kit, based o= n an -i.MX 8M Plus SoC. +The ``imx8mp-evk`` and ``imx8mm-evk`` machine models the i.MX 8M Plus +and i.MX 8M Mini Evaluation Kits, based on i.MX 8M Plus and i.MX8M +Mini SoCs. =20 Supported devices ----------------- =20 -The ``imx8mp-evk`` machine implements the following devices: +The ``imx8mp-evk`` and ``imx8mm-evk`` machines implement the +following devices: =20 * Up to 4 Cortex-A53 cores * Generic Interrupt Controller (GICv3) @@ -27,8 +29,8 @@ The ``imx8mp-evk`` machine implements the following devic= es: Boot options ------------ =20 -The ``imx8mp-evk`` machine can start a Linux kernel directly using the sta= ndard -``-kernel`` functionality. +The ``imx8mp-evk`` and ``imx8mm-evk`` machines can start a Linux +kernel directly using the standard ``-kernel`` functionality. =20 Direct Linux Kernel Boot '''''''''''''''''''''''' @@ -38,11 +40,20 @@ is to generate an image with Buildroot. Version 2024.11= .1 is tested at the time of writing and involves two steps. First run the following commands in the toplevel directory of the Buildroot source tree: =20 +For i.MX 8M Plus EVK: + .. code-block:: bash =20 $ make freescale_imx8mpevk_defconfig $ make =20 +For i.MX 8M Mini EVK: + +.. code-block:: bash + + $ make freescale_imx8mmevk_defconfig + $ make + Once finished successfully there is an ``output/image`` subfolder. Navigat= e into it and resize the SD card image to a power of two: =20 @@ -52,6 +63,8 @@ it and resize the SD card image to a power of two: =20 Now that everything is prepared the machine can be started as follows: =20 +For i.MX 8M Plus EVK: + .. code-block:: bash =20 $ qemu-system-aarch64 -M imx8mp-evk \ @@ -61,6 +74,16 @@ Now that everything is prepared the machine can be start= ed as follows: -append "root=3D/dev/mmcblk2p2" \ -drive file=3Dsdcard.img,if=3Dsd,bus=3D2,format=3Draw,id=3Dmmcblk2 =20 +For i.MX 8M Mini EVK: + +.. code-block:: bash + + $ qemu-system-aarch64 -M imx8mm-evk -smp 4 -m 2G \ + -display none -serial null -serial stdio \ + -kernel Image \ + -dtb imx8mm-evk.dtb \ + -append "root=3D/dev/mmcblk2p2" \ + -drive file=3Dsdcard.img,if=3Dsd,bus=3D2,format=3Draw,id=3Dmmcblk2 =20 KVM Acceleration ---------------- @@ -69,11 +92,13 @@ To enable hardware-assisted acceleration via KVM, append ``-accel kvm`` to the command line. While this speeds up performance significantly, be aware of the following limitations: =20 -* The ``imx8mp-evk`` machine is not included under the "virtualization use= case" - of :doc:`QEMU's security policy `. This means that you - should not trust that it can contain malicious guests, whether it is run - using TCG or KVM. If you don't trust your guests and you're relying on Q= EMU to - be the security boundary, you want to choose another machine such as ``v= irt``. +* The ``imx8mp-evk`` and ``imx8mm-evk`` machines are not included + under the "virtualization use case" of :doc:`QEMU's security + policy `. This means that you should not trust that + it can contain malicious guests, whether it is run using TCG or KVM. + If you don't trust your guests and you're relying on QEMU to be the + security boundary, you want to choose another machine such as + ``virt``. * Rather than Cortex-A53 CPUs, the same CPU type as the host's will be use= d. This is a limitation of KVM and may not work with guests with a tight dependency on Cortex-A53. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 89f7b77313..c57102a414 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -95,7 +95,7 @@ Board-specific documentation arm/imx25-pdk arm/mcimx6ul-evk arm/mcimx7d-sabre - arm/imx8mp-evk + arm/imx8m arm/orangepi arm/raspi arm/collie diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 41d5e968c8..86f4d9bc4d 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -617,6 +617,18 @@ config FSL_IMX8MP_EVK depends on TCG select FSL_IMX8MP =20 +config FSL_IMX8MM + bool + select ARM_GIC + select IMX + +config FSL_IMX8MM_EVK + bool + default y + depends on AARCH64 + depends on TCG + select FSL_IMX8MM + config ARM_SMMUV3_ACCEL bool depends on ARM_SMMUV3 diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c new file mode 100644 index 0000000000..23a82613d7 --- /dev/null +++ b/hw/arm/fsl-imx8mm.c @@ -0,0 +1,377 @@ +/* + * i.MX 8MM SoC Implementation + * + * Based on hw/arm/fsl-imx6.c + * + * Copyright (c) 2025, NXP Semiconductors + * Author: Gaurav Sharma + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * iMX8MM Reference Manual - https://www.nxp.com/products/i.MX8MMINI -> Do= cumentation + */ + +#include "qemu/osdep.h" +#include "system/address-spaces.h" +#include "hw/arm/bsa.h" +#include "hw/arm/fsl-imx8mm.h" +#include "hw/misc/unimp.h" +#include "hw/core/boards.h" +#include "system/kvm.h" +#include "system/system.h" +#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" +#include "target/arm/kvm_arm.h" +#include "qapi/error.h" +#include "qobject/qlist.h" + +static const struct { + hwaddr addr; + size_t size; + const char *name; +} fsl_imx8mm_memmap[] =3D { + [FSL_IMX8MM_RAM] =3D { FSL_IMX8MM_RAM_START, FSL_IMX8MM_RAM_SIZE_MAX, = "ram" }, + [FSL_IMX8MM_DDR_PHY_BROADCAST] =3D { 0x3dc00000, 4 * MiB, "ddr_phy_bro= adcast" }, + [FSL_IMX8MM_DDR_PERF_MON] =3D { 0x3d800000, 4 * MiB, "ddr_perf_mon" }, + [FSL_IMX8MM_DDR_CTL] =3D { 0x3d400000, 4 * MiB, "ddr_ctl" }, + [FSL_IMX8MM_DDR_PHY] =3D { 0x3c000000, 16 * MiB, "ddr_phy" }, + [FSL_IMX8MM_GIC_DIST] =3D { 0x38800000, 512 * KiB, "gic_dist" }, + [FSL_IMX8MM_GIC_REDIST] =3D { 0x38880000, 512 * KiB, "gic_redist" }, + [FSL_IMX8MM_VPU] =3D { 0x38340000, 2 * MiB, "vpu" }, + [FSL_IMX8MM_VPU_BLK_CTRL] =3D { 0x38330000, 2 * MiB, "vpu_blk_ctrl" }, + [FSL_IMX8MM_VPU_G2_DECODER] =3D { 0x38310000, 1 * MiB, "vpu_g2_decoder= " }, + [FSL_IMX8MM_VPU_G1_DECODER] =3D { 0x38300000, 1 * MiB, "vpu_g1_decoder= " }, + [FSL_IMX8MM_USB2_OTG] =3D { 0x32e50200, 0x200, "usb2_otg" }, + [FSL_IMX8MM_USB2] =3D { 0x32e50000, 0x200, "usb2" }, + [FSL_IMX8MM_USB1_OTG] =3D { 0x32e40200, 0x200, "usb1_otg" }, + [FSL_IMX8MM_USB1] =3D { 0x32e40000, 0x200, "usb1" }, + [FSL_IMX8MM_GPU2D] =3D { 0x38000000, 64 * KiB, "gpu2d" }, + [FSL_IMX8MM_QSPI1_RX_BUFFER] =3D { 0x34000000, 32 * MiB, "qspi1_rx_buf= fer" }, + [FSL_IMX8MM_PCIE1] =3D { 0x33800000, 4 * MiB, "pcie1" }, + [FSL_IMX8MM_QSPI1_TX_BUFFER] =3D { 0x33008000, 32 * KiB, "qspi1_tx_buf= fer" }, + [FSL_IMX8MM_APBH_DMA] =3D { 0x33000000, 32 * KiB, "apbh_dma" }, + + /* AIPS-4 Begin */ + [FSL_IMX8MM_TZASC] =3D { 0x32f80000, 64 * KiB, "tzasc" }, + [FSL_IMX8MM_PCIE_PHY1] =3D { 0x32f00000, 64 * KiB, "pcie_phy1" }, + [FSL_IMX8MM_MEDIA_BLK_CTL] =3D { 0x32e28000, 256, "media_blk_ctl" }, + [FSL_IMX8MM_LCDIF] =3D { 0x32e00000, 64 * KiB, "lcdif" }, + [FSL_IMX8MM_MIPI_DSI] =3D { 0x32e10000, 64 * KiB, "mipi_dsi" }, + [FSL_IMX8MM_MIPI_CSI] =3D { 0x32e30000, 64 * KiB, "mipi_csi" }, + [FSL_IMX8MM_AIPS4_CONFIGURATION] =3D { 0x32df0000, 64 * KiB, "aips4_co= nfiguration" }, + /* AIPS-4 End */ + + [FSL_IMX8MM_INTERCONNECT] =3D { 0x32700000, 1 * MiB, "interconnect" }, + + /* AIPS-3 Begin */ + [FSL_IMX8MM_ENET1] =3D { 0x30be0000, 64 * KiB, "enet1" }, + [FSL_IMX8MM_SDMA1] =3D { 0x30bd0000, 64 * KiB, "sdma1" }, + [FSL_IMX8MM_QSPI] =3D { 0x30bb0000, 64 * KiB, "qspi" }, + [FSL_IMX8MM_USDHC3] =3D { 0x30b60000, 64 * KiB, "usdhc3" }, + [FSL_IMX8MM_USDHC2] =3D { 0x30b50000, 64 * KiB, "usdhc2" }, + [FSL_IMX8MM_USDHC1] =3D { 0x30b40000, 64 * KiB, "usdhc1" }, + [FSL_IMX8MM_SEMAPHORE_HS] =3D { 0x30ac0000, 64 * KiB, "semaphore_hs" }, + [FSL_IMX8MM_MU_B] =3D { 0x30ab0000, 64 * KiB, "mu_b" }, + [FSL_IMX8MM_MU_A] =3D { 0x30aa0000, 64 * KiB, "mu_a" }, + [FSL_IMX8MM_UART4] =3D { 0x30a60000, 64 * KiB, "uart4" }, + [FSL_IMX8MM_I2C4] =3D { 0x30a50000, 64 * KiB, "i2c4" }, + [FSL_IMX8MM_I2C3] =3D { 0x30a40000, 64 * KiB, "i2c3" }, + [FSL_IMX8MM_I2C2] =3D { 0x30a30000, 64 * KiB, "i2c2" }, + [FSL_IMX8MM_I2C1] =3D { 0x30a20000, 64 * KiB, "i2c1" }, + [FSL_IMX8MM_AIPS3_CONFIGURATION] =3D { 0x309f0000, 64 * KiB, "aips3_co= nfiguration" }, + [FSL_IMX8MM_CAAM] =3D { 0x30900000, 256 * KiB, "caam" }, + [FSL_IMX8MM_SPBA1] =3D { 0x308f0000, 64 * KiB, "spba1" }, + [FSL_IMX8MM_UART2] =3D { 0x30890000, 64 * KiB, "uart2" }, + [FSL_IMX8MM_UART3] =3D { 0x30880000, 64 * KiB, "uart3" }, + [FSL_IMX8MM_UART1] =3D { 0x30860000, 64 * KiB, "uart1" }, + [FSL_IMX8MM_ECSPI3] =3D { 0x30840000, 64 * KiB, "ecspi3" }, + [FSL_IMX8MM_ECSPI2] =3D { 0x30830000, 64 * KiB, "ecspi2" }, + [FSL_IMX8MM_ECSPI1] =3D { 0x30820000, 64 * KiB, "ecspi1" }, + /* AIPS-3 End */ + + /* AIPS-2 Begin */ + [FSL_IMX8MM_QOSC] =3D { 0x307f0000, 64 * KiB, "qosc" }, + [FSL_IMX8MM_PERFMON2] =3D { 0x307d0000, 64 * KiB, "perfmon2" }, + [FSL_IMX8MM_PERFMON1] =3D { 0x307c0000, 64 * KiB, "perfmon1" }, + [FSL_IMX8MM_GPT4] =3D { 0x30700000, 64 * KiB, "gpt4" }, + [FSL_IMX8MM_GPT5] =3D { 0x306f0000, 64 * KiB, "gpt5" }, + [FSL_IMX8MM_GPT6] =3D { 0x306e0000, 64 * KiB, "gpt6" }, + [FSL_IMX8MM_SYSCNT_CTRL] =3D { 0x306c0000, 64 * KiB, "syscnt_ctrl" }, + [FSL_IMX8MM_SYSCNT_CMP] =3D { 0x306b0000, 64 * KiB, "syscnt_cmp" }, + [FSL_IMX8MM_SYSCNT_RD] =3D { 0x306a0000, 64 * KiB, "syscnt_rd" }, + [FSL_IMX8MM_PWM4] =3D { 0x30690000, 64 * KiB, "pwm4" }, + [FSL_IMX8MM_PWM3] =3D { 0x30680000, 64 * KiB, "pwm3" }, + [FSL_IMX8MM_PWM2] =3D { 0x30670000, 64 * KiB, "pwm2" }, + [FSL_IMX8MM_PWM1] =3D { 0x30660000, 64 * KiB, "pwm1" }, + [FSL_IMX8MM_AIPS2_CONFIGURATION] =3D { 0x305f0000, 64 * KiB, "aips2_co= nfiguration" }, + /* AIPS-2 End */ + + /* AIPS-1 Begin */ + [FSL_IMX8MM_CSU] =3D { 0x303e0000, 64 * KiB, "csu" }, + [FSL_IMX8MM_RDC] =3D { 0x303d0000, 64 * KiB, "rdc" }, + [FSL_IMX8MM_SEMAPHORE2] =3D { 0x303c0000, 64 * KiB, "semaphore2" }, + [FSL_IMX8MM_SEMAPHORE1] =3D { 0x303b0000, 64 * KiB, "semaphore1" }, + [FSL_IMX8MM_GPC] =3D { 0x303a0000, 64 * KiB, "gpc" }, + [FSL_IMX8MM_SRC] =3D { 0x30390000, 64 * KiB, "src" }, + [FSL_IMX8MM_CCM] =3D { 0x30380000, 64 * KiB, "ccm" }, + [FSL_IMX8MM_SNVS_HP] =3D { 0x30370000, 64 * KiB, "snvs_hp" }, + [FSL_IMX8MM_ANA_PLL] =3D { 0x30360000, 64 * KiB, "ana_pll" }, + [FSL_IMX8MM_OCOTP_CTRL] =3D { 0x30350000, 64 * KiB, "ocotp_ctrl" }, + [FSL_IMX8MM_IOMUXC_GPR] =3D { 0x30340000, 64 * KiB, "iomuxc_gpr" }, + [FSL_IMX8MM_IOMUXC] =3D { 0x30330000, 64 * KiB, "iomuxc" }, + [FSL_IMX8MM_GPT3] =3D { 0x302f0000, 64 * KiB, "gpt3" }, + [FSL_IMX8MM_GPT2] =3D { 0x302e0000, 64 * KiB, "gpt2" }, + [FSL_IMX8MM_GPT1] =3D { 0x302d0000, 64 * KiB, "gpt1" }, + [FSL_IMX8MM_SDMA2] =3D { 0x302c0000, 64 * KiB, "sdma2" }, + [FSL_IMX8MM_SDMA3] =3D { 0x302b0000, 64 * KiB, "sdma3" }, + [FSL_IMX8MM_WDOG3] =3D { 0x302a0000, 64 * KiB, "wdog3" }, + [FSL_IMX8MM_WDOG2] =3D { 0x30290000, 64 * KiB, "wdog2" }, + [FSL_IMX8MM_WDOG1] =3D { 0x30280000, 64 * KiB, "wdog1" }, + [FSL_IMX8MM_ANA_OSC] =3D { 0x30270000, 64 * KiB, "ana_osc" }, + [FSL_IMX8MM_ANA_TSENSOR] =3D { 0x30260000, 64 * KiB, "ana_tsensor" }, + [FSL_IMX8MM_GPIO5] =3D { 0x30240000, 64 * KiB, "gpio5" }, + [FSL_IMX8MM_GPIO4] =3D { 0x30230000, 64 * KiB, "gpio4" }, + [FSL_IMX8MM_GPIO3] =3D { 0x30220000, 64 * KiB, "gpio3" }, + [FSL_IMX8MM_GPIO2] =3D { 0x30210000, 64 * KiB, "gpio2" }, + [FSL_IMX8MM_GPIO1] =3D { 0x30200000, 64 * KiB, "gpio1" }, + [FSL_IMX8MM_AIPS1_CONFIGURATION] =3D { 0x301f0000, 64 * KiB, "aips1_co= nfiguration" }, + [FSL_IMX8MM_SAI6] =3D { 0x30060000, 64 * KiB, "sai6" }, + [FSL_IMX8MM_SAI5] =3D { 0x30050000, 64 * KiB, "sai5" }, + [FSL_IMX8MM_SAI3] =3D { 0x30030000, 64 * KiB, "sai3" }, + [FSL_IMX8MM_SAI2] =3D { 0x30020000, 64 * KiB, "sai2" }, + [FSL_IMX8MM_SAI1] =3D { 0x30010000, 64 * KiB, "sai1" }, + + /* AIPS-1 End */ + + [FSL_IMX8MM_A53_DAP] =3D { 0x28000000, 16 * MiB, "a53_dap" }, + [FSL_IMX8MM_PCIE1_MEM] =3D { 0x18000000, 128 * MiB, "pcie1_mem" }, + [FSL_IMX8MM_QSPI_MEM] =3D { 0x08000000, 256 * MiB, "qspi_mem" }, + [FSL_IMX8MM_OCRAM] =3D { 0x00900000, 256 * KiB, "ocram" }, + [FSL_IMX8MM_TCM_DTCM] =3D { 0x00800000, 128 * KiB, "tcm_dtcm" }, + [FSL_IMX8MM_TCM_ITCM] =3D { 0x007e0000, 128 * KiB, "tcm_itcm" }, + [FSL_IMX8MM_OCRAM_S] =3D { 0x00180000, 32 * KiB, "ocram_s" }, + [FSL_IMX8MM_CAAM_MEM] =3D { 0x00100000, 32 * KiB, "caam_mem" }, + [FSL_IMX8MM_BOOT_ROM_PROTECTED] =3D { 0x0003f000, 4 * KiB, "boot_rom_p= rotected" }, + [FSL_IMX8MM_BOOT_ROM] =3D { 0x00000000, 252 * KiB, "boot_rom" }, +}; + +static void fsl_imx8mm_init(Object *obj) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + FslImx8mmState *s =3D FSL_IMX8MM(obj); + const char *cpu_type =3D ms->cpu_type ?: ARM_CPU_TYPE_NAME("cortex-a53= "); + int i; + + for (i =3D 0; i < MIN(ms->smp.cpus, FSL_IMX8MM_NUM_CPUS); i++) { + g_autofree char *name =3D g_strdup_printf("cpu%d", i); + object_initialize_child(obj, name, &s->cpu[i], cpu_type); + } + + object_initialize_child(obj, "gic", &s->gic, gicv3_class_name()); + + for (i =3D 0; i < FSL_IMX8MM_NUM_UARTS; i++) { + g_autofree char *name =3D g_strdup_printf("uart%d", i + 1); + object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); + } + +} + +static void fsl_imx8mm_realize(DeviceState *dev, Error **errp) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + FslImx8mmState *s =3D FSL_IMX8MM(dev); + DeviceState *gicdev =3D DEVICE(&s->gic); + int i; + + if (ms->smp.cpus > FSL_IMX8MM_NUM_CPUS) { + error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", + TYPE_FSL_IMX8MM, FSL_IMX8MM_NUM_CPUS, ms->smp.cpus); + return; + } + + /* CPUs */ + for (i =3D 0; i < ms->smp.cpus; i++) { + /* On uniprocessor, the CBAR is set to 0 */ + if (ms->smp.cpus > 1 && + object_property_find(OBJECT(&s->cpu[i]), "reset-cbar")) { + object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", + fsl_imx8mm_memmap[FSL_IMX8MM_GIC_DIST]= .addr, + &error_abort); + } + + /* + * CNTFID0 base frequency in Hz of system counter + */ + object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000, + &error_abort); + + if (object_property_find(OBJECT(&s->cpu[i]), "has_el2")) { + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el2", + !kvm_enabled(), &error_abort); + } + + if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) { + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", + !kvm_enabled(), &error_abort); + } + + if (i) { + /* + * Secondary CPUs start in powered-down state (and can be + * powered up via the SRC system reset controller) + */ + object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-of= f", + true, &error_abort); + } + + if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { + return; + } + } + + /* GIC */ + { + SysBusDevice *gicsbd =3D SYS_BUS_DEVICE(&s->gic); + QList *redist_region_count; + bool pmu =3D object_property_get_bool(OBJECT(first_cpu), "pmu", NU= LL); + + qdev_prop_set_uint32(gicdev, "num-cpu", ms->smp.cpus); + qdev_prop_set_uint32(gicdev, "num-irq", + FSL_IMX8MM_NUM_IRQS + GIC_INTERNAL); + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, ms->smp.cpus); + qdev_prop_set_array(gicdev, "redist-region-count", redist_region_c= ount); + object_property_set_link(OBJECT(&s->gic), "sysmem", + OBJECT(get_system_memory()), &error_fatal= ); + if (!sysbus_realize(gicsbd, errp)) { + return; + } + sysbus_mmio_map(gicsbd, 0, fsl_imx8mm_memmap[FSL_IMX8MM_GIC_DIST].= addr); + sysbus_mmio_map(gicsbd, 1, fsl_imx8mm_memmap[FSL_IMX8MM_GIC_REDIST= ].addr); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs,= and + * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs. + */ + for (i =3D 0; i < ms->smp.cpus; i++) { + DeviceState *cpudev =3D DEVICE(&s->cpu[i]); + int intidbase =3D FSL_IMX8MM_NUM_IRQS + i * GIC_INTERNAL; + qemu_irq irq; + + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs. + */ + static const int timer_irqs[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + }; + + for (int j =3D 0; j < ARRAY_SIZE(timer_irqs); j++) { + irq =3D qdev_get_gpio_in(gicdev, intidbase + timer_irqs[j]= ); + qdev_connect_gpio_out(cpudev, j, irq); + } + + irq =3D qdev_get_gpio_in(gicdev, intidbase + ARCH_GIC_MAINT_IR= Q); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", + 0, irq); + + irq =3D qdev_get_gpio_in(gicdev, intidbase + VIRTUAL_PMU_IRQ); + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, irq); + + sysbus_connect_irq(gicsbd, i, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(gicsbd, i + ms->smp.cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicsbd, i + 2 * ms->smp.cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicsbd, i + 3 * ms->smp.cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + if (kvm_enabled()) { + if (pmu) { + assert(arm_feature(&s->cpu[i].env, ARM_FEATURE_PMU)); + if (kvm_irqchip_in_kernel()) { + kvm_arm_pmu_set_irq(&s->cpu[i], VIRTUAL_PMU_IRQ); + } + kvm_arm_pmu_init(&s->cpu[i]); + } + } + } + } + + /* UARTs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_UARTS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } serial_table[FSL_IMX8MM_NUM_UARTS] =3D { + { fsl_imx8mm_memmap[FSL_IMX8MM_UART1].addr, FSL_IMX8MM_UART1_I= RQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_UART2].addr, FSL_IMX8MM_UART2_I= RQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_UART3].addr, FSL_IMX8MM_UART3_I= RQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_UART4].addr, FSL_IMX8MM_UART4_I= RQ }, + }; + + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].ad= dr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + qdev_get_gpio_in(gicdev, serial_table[i].irq)); + } + + /* On-Chip RAM */ + if (!memory_region_init_ram(&s->ocram, OBJECT(dev), "imx8mm.ocram", + fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].size, + errp)) { + return; + } + memory_region_add_subregion(get_system_memory(), + fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr, + &s->ocram); + + /* Unimplemented devices */ + for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) { + switch (i) { + case FSL_IMX8MM_GIC_DIST: + case FSL_IMX8MM_GIC_REDIST: + case FSL_IMX8MM_RAM: + case FSL_IMX8MM_OCRAM: + case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4: + /* device implemented and treated above */ + break; + + default: + create_unimplemented_device(fsl_imx8mm_memmap[i].name, + fsl_imx8mm_memmap[i].addr, + fsl_imx8mm_memmap[i].size); + break; + } + } +} + +static void fsl_imx8mm_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D fsl_imx8mm_realize; + + dc->desc =3D "i.MX 8MM SoC"; +} + +static const TypeInfo fsl_imx8mm_types[] =3D { + { + .name =3D TYPE_FSL_IMX8MM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(FslImx8mmState), + .instance_init =3D fsl_imx8mm_init, + .class_init =3D fsl_imx8mm_class_init, + }, +}; + +DEFINE_TYPES(fsl_imx8mm_types) diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c new file mode 100644 index 0000000000..0a8cce8866 --- /dev/null +++ b/hw/arm/imx8mm-evk.c @@ -0,0 +1,112 @@ +/* + * NXP i.MX 8MM Evaluation Kit System Emulation + * + * Copyright (c) 2025, NXP Semiconductors + * Author: Gaurav Sharma + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "system/address-spaces.h" +#include "hw/arm/boot.h" +#include "hw/arm/fsl-imx8mm.h" +#include "hw/arm/machines-qom.h" +#include "hw/core/boards.h" +#include "hw/core/qdev-properties.h" +#include "system/kvm.h" +#include "system/qtest.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include + +static void imx8mm_evk_modify_dtb(const struct arm_boot_info *info, void *= fdt) +{ + int i, offset; + + /* Temporarily disable following nodes until they are implemented */ + const char *nodes_to_remove[] =3D { + "nxp,imx8mm-fspi", + "fsl,imx8mm-mipi-csi", + "fsl,imx8mm-mipi-dsim" + }; + + for (i =3D 0; i < ARRAY_SIZE(nodes_to_remove); i++) { + const char *dev_str =3D nodes_to_remove[i]; + + offset =3D fdt_node_offset_by_compatible(fdt, -1, dev_str); + while (offset >=3D 0) { + fdt_nop_node(fdt, offset); + offset =3D fdt_node_offset_by_compatible(fdt, offset, dev_str); + } + } + + /* Remove cpu-idle-states property from CPU nodes */ + offset =3D fdt_node_offset_by_compatible(fdt, -1, "arm,cortex-a53"); + while (offset >=3D 0) { + fdt_nop_property(fdt, offset, "cpu-idle-states"); + offset =3D fdt_node_offset_by_compatible(fdt, offset, "arm,cortex-= a53"); + } + + if (kvm_enabled()) { + /* Use system counter frequency from host CPU to fix time in guest= */ + offset =3D fdt_node_offset_by_compatible(fdt, -1, "arm,armv8-timer= "); + while (offset >=3D 0) { + fdt_nop_property(fdt, offset, "clock-frequency"); + offset =3D fdt_node_offset_by_compatible(fdt, offset, "arm,arm= v8-timer"); + } + } +} + +static void imx8mm_evk_init(MachineState *machine) +{ + static struct arm_boot_info boot_info; + FslImx8mmState *s; + + if (machine->ram_size > FSL_IMX8MM_RAM_SIZE_MAX) { + error_report("RAM size " RAM_ADDR_FMT " above max supported (%08" = PRIx64 ")", + machine->ram_size, FSL_IMX8MM_RAM_SIZE_MAX); + exit(1); + } + + boot_info =3D (struct arm_boot_info) { + .loader_start =3D FSL_IMX8MM_RAM_START, + .board_id =3D -1, + .ram_size =3D machine->ram_size, + .psci_conduit =3D QEMU_PSCI_CONDUIT_SMC, + .modify_dtb =3D imx8mm_evk_modify_dtb, + }; + + s =3D FSL_IMX8MM(object_new_with_props(TYPE_FSL_IMX8MM, OBJECT(machine= ), + "soc", &error_fatal, NULL)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); + + memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START, + machine->ram); + + if (!qtest_enabled()) { + arm_load_kernel(&s->cpu[0], machine, &boot_info); + } +} + +static const char *imx8mm_evk_get_default_cpu_type(const MachineState *ms) +{ + if (kvm_enabled()) { + return ARM_CPU_TYPE_NAME("host"); + } + + return ARM_CPU_TYPE_NAME("cortex-a53"); +} + +static void imx8mm_evk_machine_init(MachineClass *mc) +{ + mc->desc =3D "NXP i.MX 8MM EVK Board"; + mc->init =3D imx8mm_evk_init; + mc->max_cpus =3D FSL_IMX8MM_NUM_CPUS; + mc->default_cpus =3D FSL_IMX8MM_NUM_CPUS; + mc->default_ram_size =3D 2 * GiB; + mc->default_ram_id =3D "imx8mm-evk.ram"; + mc->get_default_cpu_type =3D imx8mm_evk_get_default_cpu_type; +} + +DEFINE_MACHINE_AARCH64("imx8mm-evk", imx8mm_evk_machine_init) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 3be1252c4f..84b8ec5fb5 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -84,6 +84,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('= armsse.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'm= cimx7d-sabre.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) +arm_common_ss.add(when: 'CONFIG_FSL_IMX8MM', if_true: files('fsl-imx8mm.c'= )) +arm_common_ss.add(when: 'CONFIG_FSL_IMX8MM_EVK', if_true: files('imx8mm-ev= k.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-= accel.c')) stub_ss.add(files('smmuv3-accel-stubs.c')) diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h new file mode 100644 index 0000000000..2811e809b9 --- /dev/null +++ b/include/hw/arm/fsl-imx8mm.h @@ -0,0 +1,158 @@ +/* + * i.MX 8MM SoC Definitions + * + * Copyright (c) 2025, NXP Semiconductors + * Author: Gaurav Sharma + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef FSL_IMX8MM_H +#define FSL_IMX8MM_H + +#include "cpu.h" +#include "hw/char/imx_serial.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qom/object.h" +#include "qemu/units.h" + +#define TYPE_FSL_IMX8MM "fsl-imx8mm" +OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM) + +#define FSL_IMX8MM_RAM_START 0x40000000 +#define FSL_IMX8MM_RAM_SIZE_MAX (4 * GiB) + +enum FslImx8mmConfiguration { + FSL_IMX8MM_NUM_CPUS =3D 4, + FSL_IMX8MM_NUM_IRQS =3D 128, + FSL_IMX8MM_NUM_UARTS =3D 4, +}; + +struct FslImx8mmState { + SysBusDevice parent_obj; + + ARMCPU cpu[FSL_IMX8MM_NUM_CPUS]; + GICv3State gic; + IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; + MemoryRegion ocram; +}; + +enum FslImx8mmMemoryRegions { + FSL_IMX8MM_A53_DAP, + FSL_IMX8MM_AIPS1_CONFIGURATION, + FSL_IMX8MM_AIPS2_CONFIGURATION, + FSL_IMX8MM_AIPS3_CONFIGURATION, + FSL_IMX8MM_AIPS4_CONFIGURATION, + FSL_IMX8MM_ANA_OSC, + FSL_IMX8MM_ANA_PLL, + FSL_IMX8MM_ANA_TSENSOR, + FSL_IMX8MM_APBH_DMA, + FSL_IMX8MM_BOOT_ROM, + FSL_IMX8MM_BOOT_ROM_PROTECTED, + FSL_IMX8MM_CAAM, + FSL_IMX8MM_CAAM_MEM, + FSL_IMX8MM_CCM, + FSL_IMX8MM_CSU, + FSL_IMX8MM_DDR_CTL, + FSL_IMX8MM_DDR_PERF_MON, + FSL_IMX8MM_DDR_PHY, + FSL_IMX8MM_DDR_PHY_BROADCAST, + FSL_IMX8MM_ECSPI1, + FSL_IMX8MM_ECSPI2, + FSL_IMX8MM_ECSPI3, + FSL_IMX8MM_ENET1, + FSL_IMX8MM_GIC_DIST, + FSL_IMX8MM_GIC_REDIST, + FSL_IMX8MM_GPC, + FSL_IMX8MM_GPIO1, + FSL_IMX8MM_GPIO2, + FSL_IMX8MM_GPIO3, + FSL_IMX8MM_GPIO4, + FSL_IMX8MM_GPIO5, + FSL_IMX8MM_GPT1, + FSL_IMX8MM_GPT2, + FSL_IMX8MM_GPT3, + FSL_IMX8MM_GPT4, + FSL_IMX8MM_GPT5, + FSL_IMX8MM_GPT6, + FSL_IMX8MM_GPU2D, + FSL_IMX8MM_I2C1, + FSL_IMX8MM_I2C2, + FSL_IMX8MM_I2C3, + FSL_IMX8MM_I2C4, + FSL_IMX8MM_INTERCONNECT, + FSL_IMX8MM_IOMUXC, + FSL_IMX8MM_IOMUXC_GPR, + FSL_IMX8MM_MEDIA_BLK_CTL, + FSL_IMX8MM_LCDIF, + FSL_IMX8MM_MIPI_CSI, + FSL_IMX8MM_MIPI_DSI, + FSL_IMX8MM_MU_A, + FSL_IMX8MM_MU_B, + FSL_IMX8MM_OCOTP_CTRL, + FSL_IMX8MM_OCRAM, + FSL_IMX8MM_OCRAM_S, + FSL_IMX8MM_PCIE1, + FSL_IMX8MM_PCIE1_MEM, + FSL_IMX8MM_PCIE_PHY1, + FSL_IMX8MM_PERFMON1, + FSL_IMX8MM_PERFMON2, + FSL_IMX8MM_PWM1, + FSL_IMX8MM_PWM2, + FSL_IMX8MM_PWM3, + FSL_IMX8MM_PWM4, + FSL_IMX8MM_QOSC, + FSL_IMX8MM_QSPI, + FSL_IMX8MM_QSPI1_RX_BUFFER, + FSL_IMX8MM_QSPI1_TX_BUFFER, + FSL_IMX8MM_QSPI_MEM, + FSL_IMX8MM_RAM, + FSL_IMX8MM_RDC, + FSL_IMX8MM_SAI1, + FSL_IMX8MM_SAI2, + FSL_IMX8MM_SAI3, + FSL_IMX8MM_SAI5, + FSL_IMX8MM_SAI6, + FSL_IMX8MM_SDMA1, + FSL_IMX8MM_SDMA2, + FSL_IMX8MM_SDMA3, + FSL_IMX8MM_SEMAPHORE1, + FSL_IMX8MM_SEMAPHORE2, + FSL_IMX8MM_SEMAPHORE_HS, + FSL_IMX8MM_SNVS_HP, + FSL_IMX8MM_SPBA1, + FSL_IMX8MM_SRC, + FSL_IMX8MM_SYSCNT_CMP, + FSL_IMX8MM_SYSCNT_CTRL, + FSL_IMX8MM_SYSCNT_RD, + FSL_IMX8MM_TCM_DTCM, + FSL_IMX8MM_TCM_ITCM, + FSL_IMX8MM_TZASC, + FSL_IMX8MM_UART1, + FSL_IMX8MM_UART2, + FSL_IMX8MM_UART3, + FSL_IMX8MM_UART4, + FSL_IMX8MM_USB1, + FSL_IMX8MM_USB2, + FSL_IMX8MM_USB1_OTG, + FSL_IMX8MM_USB2_OTG, + FSL_IMX8MM_USDHC1, + FSL_IMX8MM_USDHC2, + FSL_IMX8MM_USDHC3, + FSL_IMX8MM_VPU, + FSL_IMX8MM_VPU_BLK_CTRL, + FSL_IMX8MM_VPU_G1_DECODER, + FSL_IMX8MM_VPU_G2_DECODER, + FSL_IMX8MM_WDOG1, + FSL_IMX8MM_WDOG2, + FSL_IMX8MM_WDOG3, +}; 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This allows the same device implementation to be shared across multiple SoCs. Properties added: - arm-pll-fdiv-ctl0-reset: ARM PLL divider control reset value Default value is set to match i.MX 8MP reset value (0x000FA031). This can be overridden in the variant like iMX8MM with its own reset value. Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/misc/imx8mp_analog.c | 12 +++++++++++- include/hw/misc/imx8mp_analog.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/misc/imx8mp_analog.c b/hw/misc/imx8mp_analog.c index 23ffae84f8..592512071c 100644 --- a/hw/misc/imx8mp_analog.c +++ b/hw/misc/imx8mp_analog.c @@ -12,6 +12,7 @@ #include "qemu/log.h" =20 #include "hw/misc/imx8mp_analog.h" +#include "hw/core/qdev-properties.h" #include "migration/vmstate.h" =20 #define ANALOG_PLL_LOCK BIT(31) @@ -51,7 +52,10 @@ static void imx8mp_analog_reset(DeviceState *dev) s->analog[ANALOG_VPU_PLL_LOCKD_CTRL] =3D 0x0010003f; s->analog[ANALOG_VPU_PLL_MNIT_CTRL] =3D 0x00280081; s->analog[ANALOG_ARM_PLL_GEN_CTRL] =3D 0x00000810; - s->analog[ANALOG_ARM_PLL_FDIV_CTL0] =3D 0x000fa031; + + /* Use property value instead of hardcoded */ + s->analog[ANALOG_ARM_PLL_FDIV_CTL0] =3D s->arm_pll_fdiv_ctl0_reset; + s->analog[ANALOG_ARM_PLL_LOCKD_CTRL] =3D 0x0010003f; s->analog[ANALOG_ARM_PLL_MNIT_CTRL] =3D 0x00280081; s->analog[ANALOG_SYS_PLL1_GEN_CTRL] =3D 0x0aaaa810; @@ -138,11 +142,17 @@ static const VMStateDescription imx8mp_analog_vmstate= =3D { }, }; =20 +static const Property imx8mp_analog_properties[] =3D { + DEFINE_PROP_UINT32("arm-pll-fdiv-ctl0-reset", IMX8MPAnalogState, + arm_pll_fdiv_ctl0_reset, 0x000fa031), /* imx8mp def= ault */ +}; + static void imx8mp_analog_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 device_class_set_legacy_reset(dc, imx8mp_analog_reset); + device_class_set_props(dc, imx8mp_analog_properties); dc->vmsd =3D &imx8mp_analog_vmstate; dc->desc =3D "i.MX 8M Plus Analog Module"; } diff --git a/include/hw/misc/imx8mp_analog.h b/include/hw/misc/imx8mp_analo= g.h index 6996e53771..0765e607b9 100644 --- a/include/hw/misc/imx8mp_analog.h +++ b/include/hw/misc/imx8mp_analog.h @@ -76,6 +76,9 @@ struct IMX8MPAnalogState { } mmio; =20 uint32_t analog[ANALOG_MAX]; + + /* Property for variant-specific reset values */ + uint32_t arm_pll_fdiv_ctl0_reset; }; =20 #endif /* IMX8MP_ANALOG_H */ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294162; cv=none; d=zohomail.com; s=zohoarc; b=Qvke5ejUpOGc7/QilUDlyPsKbR46PmTQoBDyWS6crcXIEEoE9+pZou1nnG1YXKbYf26rdOXvDCmsfBvraNq/l+B0Kxy3lTkB+c0ShgjGgBIWeMcKt2p2O0Rszqc3ET94qFwz4Iw7Z3KJN1soOYQYZthHLsOy4SUXuHNf2u4uqbQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294162; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ghI8DYvTSL+/rSM2e8e78x9QvBfh+Z450FrfGt1c51A=; b=CjVlffMcYYaENTb2bRZIZ+E8kjRVGgqBWTzdVT2HTjM+ZoLoCfAFxd+/HWe8yZB7ymZeWZ1JaPz7581CAJn9MYRoHUEj2uMrlJf1b0RHy9mAX8hk7Pja4hJiVxvAIcGBylxbrZs4GYwJkAQNEbAYBu2PWcWifK8UEyTmVLZN7N4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177729416234084.98085396582735; Mon, 27 Apr 2026 05:49:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLOG-0008Mm-BN; Mon, 27 Apr 2026 08:48:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNL-0007lF-8C for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNI-0005RA-KM for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:46 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4896c22fcbaso74975685e9.0 for ; Mon, 27 Apr 2026 05:47:44 -0700 (PDT) Received: from lanath.. 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The ARM PLL divider control register (arm-pll-fdiv-ctl0) has a different reset value on i.MX8MM (0x000fa030) compared to i.MX8MP (0x000fa031). So iMX8MM will be overriding this property with its own reset-value. Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx8mm.c | 12 ++++++++++++ include/hw/arm/fsl-imx8mm.h | 2 ++ 3 files changed, 15 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 86f4d9bc4d..b3db2d6848 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -620,6 +620,7 @@ config FSL_IMX8MP_EVK config FSL_IMX8MM bool select ARM_GIC + select FSL_IMX8MP_ANALOG select IMX =20 config FSL_IMX8MM_EVK diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 23a82613d7..8218448074 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -169,6 +169,8 @@ static void fsl_imx8mm_init(Object *obj) =20 object_initialize_child(obj, "gic", &s->gic, gicv3_class_name()); =20 + object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG); + for (i =3D 0; i < FSL_IMX8MM_NUM_UARTS; i++) { g_autofree char *name =3D g_strdup_printf("uart%d", i + 1); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); @@ -303,6 +305,15 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) } } =20 + /* Analog */ + object_property_set_uint(OBJECT(&s->analog), "arm-pll-fdiv-ctl0-reset", + 0x000fa030, &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->analog), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, + fsl_imx8mm_memmap[FSL_IMX8MM_ANA_PLL].addr); + /* UARTs */ for (i =3D 0; i < FSL_IMX8MM_NUM_UARTS; i++) { static const struct { @@ -338,6 +349,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) { switch (i) { + case FSL_IMX8MM_ANA_PLL: case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: case FSL_IMX8MM_RAM: diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 2811e809b9..0a020c32a1 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -13,6 +13,7 @@ #include "cpu.h" #include "hw/char/imx_serial.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/misc/imx8mp_analog.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -33,6 +34,7 @@ struct FslImx8mmState { =20 ARMCPU cpu[FSL_IMX8MM_NUM_CPUS]; GICv3State gic; + IMX8MPAnalogState analog; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; }; --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294296; cv=none; d=zohomail.com; s=zohoarc; b=cybC5EAO3Ww9TCO229XzhqyRbl3ieiIncoZPrvSJ7aWRqcJy9p3e/TZ/yhDPW8sEqvDsEDsrG6hasWuaPwyFR5orKgePBBXcsTUFw+L0ojnBHZBeaeY1nLuIcsAM9qJZ+ZrVaeolJyY9szn/tGcoaHk2di5rHZh5lIbai06nhB0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294296; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=AQb5G+E5ajG0E+LBF57eBp4L/RpYLZ+IMh399SSPq7U=; b=EQVDfV3BrHHkUCENGFx5LMmeHbMqu9xTjMrCw2VFCW9FFx57LTG3OqxzvlbKodZj0V08Md7gxyQbtgpIR6Cgmddmc1yGRUb9M3UyzFvK/tXAqwrC6OYl96kpf/2vMHzP5jdDEyDgIEdg/3jGivELEFkvz7SJ8KyCP6sbiSRF4JY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294296966407.49376260892086; Mon, 27 Apr 2026 05:51:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLOp-0000Uo-43; Mon, 27 Apr 2026 08:49:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNN-0007lR-4k for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNK-0005Sg-Nh for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:48 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-488e1a8ac40so126639755e9.2 for ; Mon, 27 Apr 2026 05:47:44 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.47.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:47:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294064; x=1777898864; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AQb5G+E5ajG0E+LBF57eBp4L/RpYLZ+IMh399SSPq7U=; b=FrtjvHHet2yK1VlIrHw5TcB3TlMBqokaHwov1V81bWtqARvH2NCixoxZlsjvO9YH3q UOqKU7ua/6wMXYgZ3BRIb62XNIk06s3OJB1JJ+szjWJVa9ZpsisYbk/Lmo4l6IlxMZZ2 oYBP557bPibXYbSjFAwOzYFO26czCVEQUotZh6hz5PfCZwliTV3UPmQkiBH5B7I7wuat XiPy53gIbJrMRiU4zU5ER+vtX0V7fzVHmBnhzQET7oAOW+8r/zhjtOP0WKPl/Y9Do5z7 skNAD92d0/YxElsAgcq538K7FehwRPHgvDNgkhXK5ES6vsS5aI8eeuzDcJTovi+PVwqn Y1VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294064; x=1777898864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=AQb5G+E5ajG0E+LBF57eBp4L/RpYLZ+IMh399SSPq7U=; b=Z+WLtbOP7Yyu4xTCBPikIe/+lMFVO5dVfYdZ+esyEG+HpKIXVv1g0GM7rLASgzOSCp GNG6p2zHOE5B8V4cwzceBD4eBaVMElnkWuobe7n2gMEi1H7yFK1l92zXMMrGEv6vw/OJ NnwLodI5jtEfAZqA0QxYNGb69Y3kKKc9/bmAXv0a7NV10gV0EXWvQeXbxds81J5hkjSw TkitpAnZp85A5vOfR4uKrWqZa1pJcRYyePosAUg/0yMC9TKy8LxlTMuZIJTOdcKdh3U1 DjUEUnJh/1K3eXxQUueHMDU6vlE5hy5DoqCKCRk+TEucErJ5q1zveKmZVYekc/mQaEcM +5Mw== X-Gm-Message-State: AOJu0Yy0o8Ex5gKD6SyYuC5og5Pr19cqi7ZimaEmU5WUb/aHxefqipR7 XxGzRQ5PdcKlixZCz38umKiz2FszNs03crZQLBzOTyw6jthCOR8Bq/z+kcFjZ56OpicGuQGvBc8 WopWB X-Gm-Gg: AeBDieuAkMJoYwZTVZWv7/Ib/GNvnO7hXaXXacTW3mCEPzEQ1reGljnAoywXTtwroye 5MAFvuOvNjZsbhgFFJjI+nxaUwLU4T79RIelVdeE5nY1C/d1W/N/bNueVO4NFxnk3aKrmC4V/06 /2P4iVf2Vr3QTxspn2/ppU0RoisnygsxBO1mnCYIIHesANvy3Ll3KaYNpww7WRyigOvVnfGXHOD 1fCK1+qI7u/bNEjaUPZrEg93yPPuug5qUP/u0vlX/5Wjg+MTsdhLHFxutYhY0jAwSuogoOZeM1j ZpNwkBxyk3wzMvHtdmCcFYiD6fcJBXoad6RETQ4Wy3S2X8RC484gEmpi71Cqa27S2jHNZFQW33d IcKehdCUIu9T7QBHzyJAM/JcI+IUa617lpYOlAbzgja4PcpLeM2Aafvn6vGkzmlNuEdwqAo4gkV o2hlowukRk73ebhjfWCtdWMM+pheeBPWLN5hshZqSV3ccT9ddnCkr/VWto0o76uRC0O/Cpr3Oef xq7rnnnUdjs3imoFaQxu6wn8oteBpA994dDwasLkQ== X-Received: by 2002:a05:600d:b:b0:48a:563c:c8e2 with SMTP id 5b1f17b1804b1-48a563cd137mr310097505e9.3.1777294063765; Mon, 27 Apr 2026 05:47:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/63] hw/arm/fsl-imx8mm: Add Clock Control Module IP to iMX8MM Date: Mon, 27 Apr 2026 13:46:39 +0100 Message-ID: <20260427124738.966578-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294297766154100 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma Add the Clock Control Module (CCM) device to i.MX8MM SoC. The CCM implementation is shared with i.MX8MP as the register layout is identical between the two variants.Hence iMX8MM will be using the source of iMX8MP CCM. Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx8mm.c | 10 ++++++++++ include/hw/arm/fsl-imx8mm.h | 2 ++ 3 files changed, 13 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index b3db2d6848..26dc3e6ed1 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -621,6 +621,7 @@ config FSL_IMX8MM bool select ARM_GIC select FSL_IMX8MP_ANALOG + select FSL_IMX8MP_CCM select IMX =20 config FSL_IMX8MM_EVK diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 8218448074..053434412c 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -169,6 +169,8 @@ static void fsl_imx8mm_init(Object *obj) =20 object_initialize_child(obj, "gic", &s->gic, gicv3_class_name()); =20 + object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX8MP_CCM); + object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG); =20 for (i =3D 0; i < FSL_IMX8MM_NUM_UARTS; i++) { @@ -305,6 +307,13 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) } } =20 + /* CCM */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, + fsl_imx8mm_memmap[FSL_IMX8MM_CCM].addr); + /* Analog */ object_property_set_uint(OBJECT(&s->analog), "arm-pll-fdiv-ctl0-reset", 0x000fa030, &error_abort); @@ -350,6 +359,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) { switch (i) { case FSL_IMX8MM_ANA_PLL: + case FSL_IMX8MM_CCM: case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: case FSL_IMX8MM_RAM: diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 0a020c32a1..df35f0f5ac 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -14,6 +14,7 @@ #include "hw/char/imx_serial.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/misc/imx8mp_analog.h" +#include "hw/misc/imx8mp_ccm.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -34,6 +35,7 @@ struct FslImx8mmState { =20 ARMCPU cpu[FSL_IMX8MM_NUM_CPUS]; GICv3State gic; + IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294141; cv=none; d=zohomail.com; s=zohoarc; b=RBXsC5KvsO9/cM97hjFyEHZvMEKaX8ryFH52Zw7eCJ2ed3mkzUCS+uN0GRWFYro7dmBpHAAsqeEm/qm0AaUePD7xU6q6A3AE/hc3Zvsn+6ozepocWXsmRWnqBupWLpKA/0ZbfIVywDxPPI/XFUZizG1CnZKubE2SrBXTCCPcNmE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294141; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=OaA4SrpRYNI755AyNOvMWIZPb6FG92odJC0438gwgBQ=; b=V96e00DzrkjmUIBl8TlF/E4Oa8qoLRRaXsQ+83lgS7zuKwv6diR6smPsUQfAWDG/OtTOeajGS93V4M1XDmYrJlFR+fAaxhuYR5KK2ZhrMmBdgxphy+8NhkABD4izViLh2rkGkWkSSoxppZHouN/+3gXxLTSBCQuupJmlHZO3EXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294141220458.320097779776; Mon, 27 Apr 2026 05:49:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLOG-0008ND-TJ; Mon, 27 Apr 2026 08:48:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNO-0007m1-BJ for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNL-0005TP-04 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:50 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4891e5b9c1fso86366585e9.2 for ; Mon, 27 Apr 2026 05:47:45 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:47:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/63] hw/arm/fsl-imx8mm: Implemented support for SNVS Date: Mon, 27 Apr 2026 13:46:40 +0100 Message-ID: <20260427124738.966578-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294142854158501 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma SNVS contains an RTC which allows Linux to deal correctly with time Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/fsl-imx8mm.c | 10 ++++++++++ include/hw/arm/fsl-imx8mm.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 053434412c..8999bc701e 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -173,6 +173,8 @@ static void fsl_imx8mm_init(Object *obj) =20 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MP_ANALOG); =20 + object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); + for (i =3D 0; i < FSL_IMX8MM_NUM_UARTS; i++) { g_autofree char *name =3D g_strdup_printf("uart%d", i + 1); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); @@ -355,6 +357,13 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr, &s->ocram); =20 + /* SNVS */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, + fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr); + /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) { switch (i) { @@ -364,6 +373,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_GIC_REDIST: case FSL_IMX8MM_RAM: case FSL_IMX8MM_OCRAM: + case FSL_IMX8MM_SNVS_HP: case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4: /* device implemented and treated above */ break; diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index df35f0f5ac..8a172b89e0 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -13,6 +13,7 @@ #include "cpu.h" #include "hw/char/imx_serial.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" #include "qom/object.h" @@ -37,6 +38,7 @@ struct FslImx8mmState { GICv3State gic; IMX8MPCCMState ccm; IMX8MPAnalogState analog; + IMX7SNVSState snvs; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; }; --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294728; cv=none; d=zohomail.com; s=zohoarc; b=Vv6lAof0vexamOxgtfJEEvOwBr2TFE0NlKS6nTdUkX7MRocVoDa8p2CLhcLrdhW9DnjO9rWY7FZbxcoAm7r3aZgKYR3Ktu0uzykZEZ8ZawlCIk0T+9URXavOMUjmMqsZnRYAdsQYTi0ChjO9OBWrMSDO5/5V5ltTPWG2jxH7t8c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294728; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=A7tGHyLb32WspsEMndxPwKXjqKNvzmk7fqExwgmp0k8=; b=mA56pDjYamD1Ri7roZTa3uWExg1MuFCTtk/e70Iy0EVH2/bWA4bvY9pQ9azUQzyyZDAOCJ7dLocjcejT05K30t26iuNlKqXCtXTR6apPoFyaKs2wCOkueWhgqB3dv7sK8MnuJsyuC6KjeimtVO7uWVOTZjOEQDrBh5kONGrjl3o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294728801449.62219870333297; Mon, 27 Apr 2026 05:58:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUZ-0008CB-NT; Mon, 27 Apr 2026 08:55:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNO-0007m2-N0 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNL-0005TY-2Q for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:50 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4891c00e7aeso75993055e9.2 for ; Mon, 27 Apr 2026 05:47:46 -0700 (PDT) Received: from lanath.. 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This will allow running the images such as those generated by Buildroot. Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx8mm.c | 25 +++++++++++++++++++++++++ hw/arm/imx8mm-evk.c | 17 +++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 7 +++++++ 4 files changed, 50 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 26dc3e6ed1..74e8c431a2 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -623,6 +623,7 @@ config FSL_IMX8MM select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select SDHCI =20 config FSL_IMX8MM_EVK bool diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 8999bc701e..2a4d4d5e6d 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -180,6 +180,10 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_USDHCS; i++) { + g_autofree char *name =3D g_strdup_printf("usdhc%d", i + 1); + object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); + } } =20 static void fsl_imx8mm_realize(DeviceState *dev, Error **errp) @@ -357,6 +361,26 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr, &s->ocram); =20 + /* USDHCs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_USDHCS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } usdhc_table[FSL_IMX8MM_NUM_USDHCS] =3D { + { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC1].addr, FSL_IMX8MM_USDHC1= _IRQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC2].addr, FSL_IMX8MM_USDHC2= _IRQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_USDHC3].addr, FSL_IMX8MM_USDHC3= _IRQ }, + }; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, usdhc_table[i].ad= dr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, + qdev_get_gpio_in(gicdev, usdhc_table[i].irq)); + } + /* SNVS */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { return; @@ -375,6 +399,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_OCRAM: case FSL_IMX8MM_SNVS_HP: case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4: + case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3: /* device implemented and treated above */ break; =20 diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c index 0a8cce8866..dfdf3cd4f8 100644 --- a/hw/arm/imx8mm-evk.c +++ b/hw/arm/imx8mm-evk.c @@ -84,6 +84,23 @@ static void imx8mm_evk_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START, machine->ram); =20 + for (int i =3D 0; i < FSL_IMX8MM_NUM_USDHCS; i++) { + BusState *bus; + DeviceState *carddev; + BlockBackend *blk; + DriveInfo *di =3D drive_get(IF_SD, i, 0); + + if (!di) { + continue; + } + + blk =3D blk_by_legacy_dinfo(di); + bus =3D qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); + carddev =3D qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); + qdev_realize_and_unref(carddev, bus, &error_fatal); + } + if (!qtest_enabled()) { arm_load_kernel(&s->cpu[0], machine, &boot_info); } diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 8a172b89e0..93a30a2f55 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -16,6 +16,7 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" +#include "hw/sd/sdhci.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -29,6 +30,7 @@ enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_CPUS =3D 4, FSL_IMX8MM_NUM_IRQS =3D 128, FSL_IMX8MM_NUM_UARTS =3D 4, + FSL_IMX8MM_NUM_USDHCS =3D 3, }; =20 struct FslImx8mmState { @@ -41,6 +43,7 @@ struct FslImx8mmState { IMX7SNVSState snvs; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; + SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS]; }; =20 enum FslImx8mmMemoryRegions { @@ -155,6 +158,10 @@ enum FslImx8mmMemoryRegions { }; =20 enum FslImx8mmIrqs { + FSL_IMX8MM_USDHC1_IRQ =3D 22, + FSL_IMX8MM_USDHC2_IRQ =3D 23, + FSL_IMX8MM_USDHC3_IRQ =3D 24, + FSL_IMX8MM_UART1_IRQ =3D 26, FSL_IMX8MM_UART2_IRQ =3D 27, FSL_IMX8MM_UART3_IRQ =3D 28, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294232; cv=none; d=zohomail.com; s=zohoarc; b=jZPvDmUkBRzoLjECE2mZ/U/eA3vLaHFtImZPxb5q/PElrLTpVvAVDXAq4NzeWaozihiPJ8OyyLKp3EzceEUGR4ASGFrxIcXoVG2005XBpxy8+ghIVjiaCDpvl0J6sjttZ5bhxxTecGgDjJ9TuDdoTYoBEWx5Jd6LWypD4J5Q1IA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294232; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ncA954+/b3LBw7J5Pq2tPoyKl97Mh8cz0m0mv1bmSPo=; b=LPu8IB/2hbZMU+NRkqTIGW+hhOHd8n37BAV0+GVz6B+JkE4ELSb6UM7Y3zKZxUTtzQ47sQsgT+VaOs2PTCBVGKewkGxyqPhqWfujFhGoEk2Ns06EMozDzksx2kF2+Qz930VTGYA/DnCXBa0/cdLUSlwCWOwwu9Np135h/jJ23OI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294232206897.5771286535106; Mon, 27 Apr 2026 05:50:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLP4-0000qZ-5f; Mon, 27 Apr 2026 08:49:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNP-0007nT-Tk for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:53 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNM-0005Te-LH for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4891e5b9c1fso86366965e9.2 for ; Mon, 27 Apr 2026 05:47:47 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:47:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/63] hw/arm/fsl-imx8mm: Add PCIe support Date: Mon, 27 Apr 2026 13:46:42 +0100 Message-ID: <20260427124738.966578-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294234540154100 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma This enables support for Designware PCI Express Controller emulation It provides a controlled environment to debug the linux pci subsystem Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 3 +++ hw/arm/fsl-imx8mm.c | 30 ++++++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 10 ++++++++++ 3 files changed, 43 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 74e8c431a2..59d5aba2db 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -619,11 +619,14 @@ config FSL_IMX8MP_EVK =20 config FSL_IMX8MM bool + imply PCI_DEVICES select ARM_GIC select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX select SDHCI + select PCI_EXPRESS_DESIGNWARE + select PCI_EXPRESS_FSL_IMX8M_PHY =20 config FSL_IMX8MM_EVK bool diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 2a4d4d5e6d..633b121630 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -184,6 +184,10 @@ static void fsl_imx8mm_init(Object *obj) g_autofree char *name =3D g_strdup_printf("usdhc%d", i + 1); object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); } + + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); + object_initialize_child(obj, "pcie_phy", &s->pcie_phy, + TYPE_FSL_IMX8M_PCIE_PHY); } =20 static void fsl_imx8mm_realize(DeviceState *dev, Error **errp) @@ -388,6 +392,30 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr); =20 + /* PCIe */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, + fsl_imx8mm_memmap[FSL_IMX8MM_PCIE1].addr); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, + qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTA_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, + qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTB_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, + qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTC_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, + qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_INTD_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 4, + qdev_get_gpio_in(gicdev, FSL_IMX8MM_PCI_MSI_IRQ)); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie_phy), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie_phy), 0, + fsl_imx8mm_memmap[FSL_IMX8MM_PCIE_PHY1].addr); + /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) { switch (i) { @@ -395,6 +423,8 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_CCM: case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: + case FSL_IMX8MM_PCIE1: + case FSL_IMX8MM_PCIE_PHY1: case FSL_IMX8MM_RAM: case FSL_IMX8MM_OCRAM: case FSL_IMX8MM_SNVS_HP: diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 93a30a2f55..3181c02574 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -16,6 +16,8 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" +#include "hw/pci-host/designware.h" +#include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" #include "qom/object.h" #include "qemu/units.h" @@ -44,6 +46,8 @@ struct FslImx8mmState { IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS]; + DesignwarePCIEHost pcie; + FslImx8mPciePhyState pcie_phy; }; =20 enum FslImx8mmMemoryRegions { @@ -166,6 +170,12 @@ enum FslImx8mmIrqs { FSL_IMX8MM_UART2_IRQ =3D 27, FSL_IMX8MM_UART3_IRQ =3D 28, FSL_IMX8MM_UART4_IRQ =3D 29, + + FSL_IMX8MM_PCI_INTA_IRQ =3D 122, + FSL_IMX8MM_PCI_INTB_IRQ =3D 123, + FSL_IMX8MM_PCI_INTC_IRQ =3D 124, + FSL_IMX8MM_PCI_INTD_IRQ =3D 125, + FSL_IMX8MM_PCI_MSI_IRQ =3D 127, }; =20 #endif /* FSL_IMX8MM_H */ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294245; cv=none; d=zohomail.com; s=zohoarc; b=d1aNNLe1XRVNlmbLDyInM2tabh0aC2m71HuMaVSveF7T6mvYUehS4r4jGDG9a4JKlZbApHaZ4f/vJffTmFotZo6t7cONwhyGAUirUzZXcKOkoYny4Li8qyxgy5E2fXV3k1f//dJ1MiX7YFzt/F3mctemJIqmmJVprixSWOuyGkU= ARC-Message-Signature: i=1; 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Mon, 27 Apr 2026 05:47:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/63] hw/arm/fsl-imx8mm: Add GPIO controllers Date: Mon, 27 Apr 2026 13:46:43 +0100 Message-ID: <20260427124738.966578-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294246795154100 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma Enabled GPIO controller emulation Also updated the GPIO IRQ lines of iMX8MM Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/fsl-imx8mm.c | 54 +++++++++++++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 14 ++++++++++ 2 files changed, 68 insertions(+) diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 633b121630..85bce5a788 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -180,6 +180,11 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_GPIOS; i++) { + g_autofree char *name =3D g_strdup_printf("gpio%d", i + 1); + object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); + } + for (i =3D 0; i < FSL_IMX8MM_NUM_USDHCS; i++) { g_autofree char *name =3D g_strdup_printf("usdhc%d", i + 1); object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); @@ -365,6 +370,54 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr, &s->ocram); =20 + /* GPIOs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_GPIOS; i++) { + static const struct { + hwaddr addr; + unsigned int irq_low; + unsigned int irq_high; + } gpio_table[FSL_IMX8MM_NUM_GPIOS] =3D { + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO1].addr, + FSL_IMX8MM_GPIO1_LOW_IRQ, + FSL_IMX8MM_GPIO1_HIGH_IRQ + }, + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO2].addr, + FSL_IMX8MM_GPIO2_LOW_IRQ, + FSL_IMX8MM_GPIO2_HIGH_IRQ + }, + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO3].addr, + FSL_IMX8MM_GPIO3_LOW_IRQ, + FSL_IMX8MM_GPIO3_HIGH_IRQ + }, + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO4].addr, + FSL_IMX8MM_GPIO4_LOW_IRQ, + FSL_IMX8MM_GPIO4_HIGH_IRQ + }, + { + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO5].addr, + FSL_IMX8MM_GPIO5_LOW_IRQ, + FSL_IMX8MM_GPIO5_HIGH_IRQ + }, + }; + object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, + &error_abort); + object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", + true, &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, + qdev_get_gpio_in(gicdev, gpio_table[i].irq_low)= ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, + qdev_get_gpio_in(gicdev, gpio_table[i].irq_high= )); + } + /* USDHCs */ for (i =3D 0; i < FSL_IMX8MM_NUM_USDHCS; i++) { static const struct { @@ -423,6 +476,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_CCM: case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: + case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5: case FSL_IMX8MM_PCIE1: case FSL_IMX8MM_PCIE_PHY1: case FSL_IMX8MM_RAM: diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 3181c02574..4fe27b9575 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -12,6 +12,7 @@ =20 #include "cpu.h" #include "hw/char/imx_serial.h" +#include "hw/gpio/imx_gpio.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" @@ -30,6 +31,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM) =20 enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_CPUS =3D 4, + FSL_IMX8MM_NUM_GPIOS =3D 5, FSL_IMX8MM_NUM_IRQS =3D 128, FSL_IMX8MM_NUM_UARTS =3D 4, FSL_IMX8MM_NUM_USDHCS =3D 3, @@ -40,6 +42,7 @@ struct FslImx8mmState { =20 ARMCPU cpu[FSL_IMX8MM_NUM_CPUS]; GICv3State gic; + IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS]; IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMX7SNVSState snvs; @@ -171,6 +174,17 @@ enum FslImx8mmIrqs { FSL_IMX8MM_UART3_IRQ =3D 28, FSL_IMX8MM_UART4_IRQ =3D 29, =20 + FSL_IMX8MM_GPIO1_LOW_IRQ =3D 64, + FSL_IMX8MM_GPIO1_HIGH_IRQ =3D 65, + FSL_IMX8MM_GPIO2_LOW_IRQ =3D 66, + FSL_IMX8MM_GPIO2_HIGH_IRQ =3D 67, + FSL_IMX8MM_GPIO3_LOW_IRQ =3D 68, + FSL_IMX8MM_GPIO3_HIGH_IRQ =3D 69, + FSL_IMX8MM_GPIO4_LOW_IRQ =3D 70, + FSL_IMX8MM_GPIO4_HIGH_IRQ =3D 71, + FSL_IMX8MM_GPIO5_LOW_IRQ =3D 72, + FSL_IMX8MM_GPIO5_HIGH_IRQ =3D 73, + FSL_IMX8MM_PCI_INTA_IRQ =3D 122, FSL_IMX8MM_PCI_INTB_IRQ =3D 123, FSL_IMX8MM_PCI_INTC_IRQ =3D 124, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294168; cv=none; d=zohomail.com; s=zohoarc; b=TxZZkgyl+tvcBiByqFkVzQLIMl7yI/EzgEEsyaMGyNjQ/dfxwfehRf/9lqeiCZXpEFNNOe25QHowZofXkFes/39LylVWLF50gQGZmxLm8GKa1NtOh3EvLLFk6n9fOBynIS0JRlmO+bD/CwJ50uWNTgFBTl9lEA7UWOxJd8Qfrjs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294168; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dWl2agwSOZcRjYpLQ3Cbs8b4kpJoVPljgBk5DCsC6g4=; b=DtJhvR1qIc0tWTe6iAi5VuG/2ISGlPiYfZGyrDueApz2mvqjdH8+TiXHsqRwKqeiYqQ72t3OwvayLp91WZ2dWszIXPGQCdiy4x73Ro7ndAWirAKlwhhu8dcI+DtQLOmiAnF5+j+f6v7SyK/hg8rHEnN/qXTB0cIp/j/pqidjWrg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294168764803.8796252845958; Mon, 27 Apr 2026 05:49:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLOZ-0000GB-Rw; Mon, 27 Apr 2026 08:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNQ-0007nV-0a for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:53 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNN-0005U3-Ip for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:51 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-488b150559bso81056025e9.1 for ; Mon, 27 Apr 2026 05:47:49 -0700 (PDT) Received: from lanath.. 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Added I2C interrupts Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 2 ++ hw/arm/fsl-imx8mm.c | 27 +++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 8 ++++++++ 3 files changed, 37 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 59d5aba2db..e8296f9a28 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -620,10 +620,12 @@ config FSL_IMX8MP_EVK config FSL_IMX8MM bool imply PCI_DEVICES + imply I2C_DEVICES select ARM_GIC select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select IMX_I2C select SDHCI select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_FSL_IMX8M_PHY diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 85bce5a788..3632d85197 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -180,6 +180,11 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_I2CS; i++) { + g_autofree char *name =3D g_strdup_printf("i2c%d", i + 1); + object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); + } + for (i =3D 0; i < FSL_IMX8MM_NUM_GPIOS; i++) { g_autofree char *name =3D g_strdup_printf("gpio%d", i + 1); object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); @@ -370,6 +375,27 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr, &s->ocram); =20 + /* I2Cs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_I2CS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } i2c_table[FSL_IMX8MM_NUM_I2CS] =3D { + { fsl_imx8mm_memmap[FSL_IMX8MM_I2C1].addr, FSL_IMX8MM_I2C1_IRQ= }, + { fsl_imx8mm_memmap[FSL_IMX8MM_I2C2].addr, FSL_IMX8MM_I2C2_IRQ= }, + { fsl_imx8mm_memmap[FSL_IMX8MM_I2C3].addr, FSL_IMX8MM_I2C3_IRQ= }, + { fsl_imx8mm_memmap[FSL_IMX8MM_I2C4].addr, FSL_IMX8MM_I2C4_IRQ= }, + }; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, + qdev_get_gpio_in(gicdev, i2c_table[i].irq)); + } + /* GPIOs */ for (i =3D 0; i < FSL_IMX8MM_NUM_GPIOS; i++) { static const struct { @@ -477,6 +503,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5: + case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4: case FSL_IMX8MM_PCIE1: case FSL_IMX8MM_PCIE_PHY1: case FSL_IMX8MM_RAM: diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 4fe27b9575..d6df16e9d4 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -13,6 +13,7 @@ #include "cpu.h" #include "hw/char/imx_serial.h" #include "hw/gpio/imx_gpio.h" +#include "hw/i2c/imx_i2c.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" @@ -32,6 +33,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM) enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_CPUS =3D 4, FSL_IMX8MM_NUM_GPIOS =3D 5, + FSL_IMX8MM_NUM_I2CS =3D 4, FSL_IMX8MM_NUM_IRQS =3D 128, FSL_IMX8MM_NUM_UARTS =3D 4, FSL_IMX8MM_NUM_USDHCS =3D 3, @@ -46,6 +48,7 @@ struct FslImx8mmState { IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMX7SNVSState snvs; + IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS]; @@ -174,6 +177,11 @@ enum FslImx8mmIrqs { FSL_IMX8MM_UART3_IRQ =3D 28, FSL_IMX8MM_UART4_IRQ =3D 29, =20 + FSL_IMX8MM_I2C1_IRQ =3D 35, + FSL_IMX8MM_I2C2_IRQ =3D 36, + FSL_IMX8MM_I2C3_IRQ =3D 37, + FSL_IMX8MM_I2C4_IRQ =3D 38, + FSL_IMX8MM_GPIO1_LOW_IRQ =3D 64, FSL_IMX8MM_GPIO1_HIGH_IRQ =3D 65, FSL_IMX8MM_GPIO2_LOW_IRQ =3D 66, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294744; cv=none; d=zohomail.com; s=zohoarc; b=OJUGBMa0j6NaC32VusMMaPJPLu3CSTbI5/u+V2AHVCqO9BbeF/oztBITimg3FaNql4AFbV4f7u0ogJNJt8hXv6+xgejaFQtwiUMK98myPvZ9YeXP/EvNvU/HSkAQW9LXopoh0p5aDhgcdtHheN4L/RX0C3vC4K4CSbOO2sjoJ4M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294744; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+f5ZGmX9oTLSaVcb3xFFj2b2ao74Al5SyMxc3YROTz0=; b=FuiBk1TY1+Rw7agNUWI1Hq+Pfa939JnrR7t5MDwKz0FKYDiYqrTQMqwqo8zkWJC3Vz7MOsQW9tA8zeZlJQvhNKajvp1Q30IyCneXjtwhyRh2BMX1nlCEqfpanwmMC97fVkXCVblM/Ks3Qh6kejJgp4QElAnmh49H4DmoLVo60D4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294744783809.2437355797359; Mon, 27 Apr 2026 05:59:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLU1-0005TB-3l; Mon, 27 Apr 2026 08:54:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNR-0007nc-D9 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:54 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNP-0005UX-M7 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:53 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so172740695e9.2 for ; Mon, 27 Apr 2026 05:47:51 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:47:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/63] hw/arm/fsl-imx8mm: Adding support for SPI controller Date: Mon, 27 Apr 2026 13:46:45 +0100 Message-ID: <20260427124738.966578-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294746188154100 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma It enables emulation of ECSPI in iMX8MM Added SPI IRQ lines Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/fsl-imx8mm.c | 26 ++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 7 +++++++ 2 files changed, 33 insertions(+) diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 3632d85197..f433beeaf2 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -195,6 +195,11 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) { + g_autofree char *name =3D g_strdup_printf("spi%d", i + 1); + object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); + } + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -464,6 +469,26 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, usdhc_table[i].irq)); } =20 + /* ECSPIs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } spi_table[FSL_IMX8MM_NUM_ECSPIS] =3D { + { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI1].addr, FSL_IMX8MM_ECSPI1= _IRQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI2].addr, FSL_IMX8MM_ECSPI2= _IRQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI3].addr, FSL_IMX8MM_ECSPI3= _IRQ }, + }; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + qdev_get_gpio_in(gicdev, spi_table[i].irq)); + } + /* SNVS */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { return; @@ -503,6 +528,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5: + case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3: case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4: case FSL_IMX8MM_PCIE1: case FSL_IMX8MM_PCIE_PHY1: diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index d6df16e9d4..13c044412a 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -21,6 +21,7 @@ #include "hw/pci-host/designware.h" #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" +#include "hw/ssi/imx_spi.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -32,6 +33,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM) =20 enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_CPUS =3D 4, + FSL_IMX8MM_NUM_ECSPIS =3D 3, FSL_IMX8MM_NUM_GPIOS =3D 5, FSL_IMX8MM_NUM_I2CS =3D 4, FSL_IMX8MM_NUM_IRQS =3D 128, @@ -48,6 +50,7 @@ struct FslImx8mmState { IMX8MPCCMState ccm; IMX8MPAnalogState analog; IMX7SNVSState snvs; + IMXSPIState spi[FSL_IMX8MM_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; @@ -177,6 +180,10 @@ enum FslImx8mmIrqs { FSL_IMX8MM_UART3_IRQ =3D 28, FSL_IMX8MM_UART4_IRQ =3D 29, =20 + FSL_IMX8MM_ECSPI1_IRQ =3D 31, + FSL_IMX8MM_ECSPI2_IRQ =3D 32, + FSL_IMX8MM_ECSPI3_IRQ =3D 33, + FSL_IMX8MM_I2C1_IRQ =3D 35, FSL_IMX8MM_I2C2_IRQ =3D 36, FSL_IMX8MM_I2C3_IRQ =3D 37, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294148; cv=none; d=zohomail.com; s=zohoarc; b=KF/e0qwH0NZqN+0U49Zv8yQNrqCoIHNom6w4DJte8yhq6aoaazi7BemKQUYlVk+YrBVS4X5BkM1HQmK3CvLGpordGI4DTWynb2QxL27yNRCEfaZTJWnuyxzzFOcV/qFOp4dwfXNSGDYswjE7xDB6qNWU+nQsigw5zCGpZL0gF2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294148; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3JNjfatGM7VZYxrKHW8ReU78B4hS86QJtHBIQ1CnwPI=; b=g1wASmthBTHC3sBp3BxCkBBW8gVPMXTC1uX0PW84thm16pfjy7u6VqGId0vR2VR15rLrgVjo+JhUwduRQJ0msDwLZ28fWDGcbEGAdYypW3ojJsm/KKk8h2LUn9JwxkVcJyXzz9hwz4GJc5Ce7oEtx3FxzizTsO/50+01GDx2igw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294148408837.3225912774212; Mon, 27 Apr 2026 05:49:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLOR-00005k-KY; Mon, 27 Apr 2026 08:48:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNR-0007nb-5k for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:53 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNP-0005UQ-9L for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:52 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-488b3f8fa2bso103390745e9.1 for ; Mon, 27 Apr 2026 05:47:50 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:47:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/63] hw/arm/fsl-imx8mm: Adding support for Watchdog Timers Date: Mon, 27 Apr 2026 13:46:46 +0100 Message-ID: <20260427124738.966578-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294148822158500 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma It enables emulation of WDT in iMX8MM Added WDT IRQ lines Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx8mm.c | 28 ++++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 7 +++++++ 3 files changed, 36 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e8296f9a28..42901c4383 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -629,6 +629,7 @@ config FSL_IMX8MM select SDHCI select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_FSL_IMX8M_PHY + select WDT_IMX2 =20 config FSL_IMX8MM_EVK bool diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index f433beeaf2..34645555d6 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -200,6 +200,11 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_WDTS; i++) { + g_autofree char *name =3D g_strdup_printf("wdt%d", i); + object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); + } + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -496,6 +501,28 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr); =20 + /* Watchdogs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_WDTS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } wdog_table[FSL_IMX8MM_NUM_WDTS] =3D { + { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG1].addr, FSL_IMX8MM_WDOG1_I= RQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG2].addr, FSL_IMX8MM_WDOG2_I= RQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG3].addr, FSL_IMX8MM_WDOG3_I= RQ }, + }; + + object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", + true, &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, wdog_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, + qdev_get_gpio_in(gicdev, wdog_table[i].irq)); + } + /* PCIe */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) { return; @@ -537,6 +564,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_SNVS_HP: case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4: case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3: + case FSL_IMX8MM_WDOG1 ... FSL_IMX8MM_WDOG3: /* device implemented and treated above */ break; =20 diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 13c044412a..fd62b19a87 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -22,6 +22,7 @@ #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" +#include "hw/watchdog/wdt_imx2.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -39,6 +40,7 @@ enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_IRQS =3D 128, FSL_IMX8MM_NUM_UARTS =3D 4, FSL_IMX8MM_NUM_USDHCS =3D 3, + FSL_IMX8MM_NUM_WDTS =3D 3, }; =20 struct FslImx8mmState { @@ -55,6 +57,7 @@ struct FslImx8mmState { IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS]; + IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; }; @@ -200,6 +203,10 @@ enum FslImx8mmIrqs { FSL_IMX8MM_GPIO5_LOW_IRQ =3D 72, FSL_IMX8MM_GPIO5_HIGH_IRQ =3D 73, =20 + FSL_IMX8MM_WDOG1_IRQ =3D 78, + FSL_IMX8MM_WDOG2_IRQ =3D 79, + FSL_IMX8MM_WDOG3_IRQ =3D 10, + FSL_IMX8MM_PCI_INTA_IRQ =3D 122, FSL_IMX8MM_PCI_INTB_IRQ =3D 123, FSL_IMX8MM_PCI_INTC_IRQ =3D 124, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294600; cv=none; d=zohomail.com; s=zohoarc; b=cd5ksid7m9VPPHuIltGoKAZIcT5lTjxmVkOZkVjHCxj180dDkNyxdV6gfvvvb2OQ7ZtNXhUZKPiC5rbxukQlDj4lccqLwoiGn12JHgakx0sa3pAotC8VsXJv8sZEQTRDbla+NYiiqL682JyHILnI3bGyUxg+LZmHQNxiavxHKog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294600; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+EHAWxwR5gtY8WCIFdHKUvBLUSjZ15ts5pSdgClXwsM=; b=SkxINkQOe6LcK1ry4WLMqmV4etj/A4mU9T2ApQHlYhdgkVBZxh2deBDosGkajI4jRLUbWyR9RgRXdPseKudGHXHMooLRcDyVWo03satFVeXFHx6GtvjPFanqPYlq3vAufA0cC7WTULOMDX+a3LIuH8NPaVCXDOv4qpPqpYLWp74= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294600176620.3879911848252; Mon, 27 Apr 2026 05:56:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUo-0001lQ-J6; Mon, 27 Apr 2026 08:55:30 -0400 Received: from eggs.gnu.org ([209.51.188.92]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLSi-0004Nc-TM for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:53:33 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNQ-0005Ug-Bt for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:47:54 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-488ad135063so93520065e9.0 for ; Mon, 27 Apr 2026 05:47:51 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:47:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/63] hw/arm/fsl-imx8mm: Adding support for General Purpose Timers Date: Mon, 27 Apr 2026 13:46:47 +0100 Message-ID: <20260427124738.966578-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294603431158500 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma It enables emulation of GPT in iMX8MM Added GPT IRQ lines Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx8mm.c | 54 +++++++++++++++++++++++++++++++++++++ hw/timer/imx_gpt.c | 26 ++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 11 ++++++++ include/hw/timer/imx_gpt.h | 2 ++ 5 files changed, 94 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 42901c4383..44dd401c8a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -626,6 +626,7 @@ config FSL_IMX8MM select FSL_IMX8MP_CCM select IMX select IMX_I2C + select OR_IRQ select SDHCI select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_FSL_IMX8M_PHY diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 34645555d6..3736191257 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -180,6 +180,13 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_GPTS; i++) { + g_autofree char *name =3D g_strdup_printf("gpt%d", i + 1); + object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX8MM_GPT); + } + object_initialize_child(obj, "gpt5-gpt6-irq", &s->gpt5_gpt6_irq, + TYPE_OR_IRQ); + for (i =3D 0; i < FSL_IMX8MM_NUM_I2CS; i++) { g_autofree char *name =3D g_strdup_printf("i2c%d", i + 1); object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); @@ -385,6 +392,52 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) fsl_imx8mm_memmap[FSL_IMX8MM_OCRAM].addr, &s->ocram); =20 + /* GPTs */ + object_property_set_int(OBJECT(&s->gpt5_gpt6_irq), "num-lines", 2, + &error_abort); + if (!qdev_realize(DEVICE(&s->gpt5_gpt6_irq), NULL, errp)) { + return; + } + + qdev_connect_gpio_out(DEVICE(&s->gpt5_gpt6_irq), 0, + qdev_get_gpio_in(gicdev, FSL_IMX8MM_GPT5_GPT6_IR= Q)); + + for (i =3D 0; i < FSL_IMX8MM_NUM_GPTS; i++) { + hwaddr gpt_addrs[FSL_IMX8MM_NUM_GPTS] =3D { + fsl_imx8mm_memmap[FSL_IMX8MM_GPT1].addr, + fsl_imx8mm_memmap[FSL_IMX8MM_GPT2].addr, + fsl_imx8mm_memmap[FSL_IMX8MM_GPT3].addr, + fsl_imx8mm_memmap[FSL_IMX8MM_GPT4].addr, + fsl_imx8mm_memmap[FSL_IMX8MM_GPT5].addr, + fsl_imx8mm_memmap[FSL_IMX8MM_GPT6].addr, + }; + + s->gpt[i].ccm =3D IMX_CCM(&s->ccm); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_addrs[i]); + + if (i < FSL_IMX8MM_NUM_GPTS - 2) { + static const unsigned int gpt_irqs[FSL_IMX8MM_NUM_GPTS - 2] = =3D { + FSL_IMX8MM_GPT1_IRQ, + FSL_IMX8MM_GPT2_IRQ, + FSL_IMX8MM_GPT3_IRQ, + FSL_IMX8MM_GPT4_IRQ, + }; + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, + qdev_get_gpio_in(gicdev, gpt_irqs[i])); + } else { + int irq =3D i - FSL_IMX8MM_NUM_GPTS + 2; + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, + qdev_get_gpio_in(DEVICE(&s->gpt5_gpt6_irq),= irq)); + } + } + /* I2Cs */ for (i =3D 0; i < FSL_IMX8MM_NUM_I2CS; i++) { static const struct { @@ -555,6 +608,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5: + case FSL_IMX8MM_GPT1 ... FSL_IMX8MM_GPT6: case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3: case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4: case FSL_IMX8MM_PCIE1: diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index 168cadcb3f..cdc0257126 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -6,6 +6,7 @@ * Originally written by Hans Jiang * Updated by Peter Chubb * Updated by Jean-Christophe Dubois + * Updated by Gaurav Sharma * * This code is licensed under GPL version 2 or later. See * the COPYING file in the top-level directory. @@ -137,6 +138,17 @@ static const IMXClk imx8mp_gpt_clocks[] =3D { CLK_NONE, /* 111 not defined */ }; =20 +static const IMXClk imx8mm_gpt_clocks[] =3D { + CLK_NONE, /* 000 No clock source */ + CLK_IPG, /* 001 ipg_clk, 532MHz */ + CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ + CLK_EXT, /* 011 External clock */ + CLK_32k, /* 100 ipg_clk_32k */ + CLK_HIGH, /* 101 ipg_clk_16M */ + CLK_NONE, /* 110 not defined */ + CLK_NONE, /* 111 not defined */ +}; + /* Must be called from within ptimer_transaction_begin/commit block */ static void imx_gpt_set_freq(IMXGPTState *s) { @@ -570,6 +582,13 @@ static void imx8mp_gpt_init(Object *obj) s->clocks =3D imx8mp_gpt_clocks; } =20 +static void imx8mm_gpt_init(Object *obj) +{ + IMXGPTState *s =3D IMX_GPT(obj); + + s->clocks =3D imx8mm_gpt_clocks; +} + static const TypeInfo imx25_gpt_info =3D { .name =3D TYPE_IMX25_GPT, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -608,6 +627,12 @@ static const TypeInfo imx8mp_gpt_info =3D { .instance_init =3D imx8mp_gpt_init, }; =20 +static const TypeInfo imx8mm_gpt_info =3D { + .name =3D TYPE_IMX8MM_GPT, + .parent =3D TYPE_IMX25_GPT, + .instance_init =3D imx8mm_gpt_init, +}; + static void imx_gpt_register_types(void) { type_register_static(&imx25_gpt_info); @@ -616,6 +641,7 @@ static void imx_gpt_register_types(void) type_register_static(&imx6ul_gpt_info); type_register_static(&imx7_gpt_info); type_register_static(&imx8mp_gpt_info); + type_register_static(&imx8mm_gpt_info); } =20 type_init(imx_gpt_register_types) diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index fd62b19a87..607ac86666 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -18,10 +18,12 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" +#include "hw/or-irq.h" #include "hw/pci-host/designware.h" #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" +#include "hw/timer/imx_gpt.h" #include "hw/watchdog/wdt_imx2.h" #include "qom/object.h" #include "qemu/units.h" @@ -36,6 +38,7 @@ enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_CPUS =3D 4, FSL_IMX8MM_NUM_ECSPIS =3D 3, FSL_IMX8MM_NUM_GPIOS =3D 5, + FSL_IMX8MM_NUM_GPTS =3D 6, FSL_IMX8MM_NUM_I2CS =3D 4, FSL_IMX8MM_NUM_IRQS =3D 128, FSL_IMX8MM_NUM_UARTS =3D 4, @@ -48,6 +51,7 @@ struct FslImx8mmState { =20 ARMCPU cpu[FSL_IMX8MM_NUM_CPUS]; GICv3State gic; + IMXGPTState gpt[FSL_IMX8MM_NUM_GPTS]; IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS]; IMX8MPCCMState ccm; IMX8MPAnalogState analog; @@ -60,6 +64,7 @@ struct FslImx8mmState { IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; + OrIRQState gpt5_gpt6_irq; }; =20 enum FslImx8mmMemoryRegions { @@ -192,6 +197,12 @@ enum FslImx8mmIrqs { FSL_IMX8MM_I2C3_IRQ =3D 37, FSL_IMX8MM_I2C4_IRQ =3D 38, =20 + FSL_IMX8MM_GPT1_IRQ =3D 55, + FSL_IMX8MM_GPT2_IRQ =3D 54, + FSL_IMX8MM_GPT3_IRQ =3D 53, + FSL_IMX8MM_GPT4_IRQ =3D 52, + FSL_IMX8MM_GPT5_GPT6_IRQ =3D 51, + FSL_IMX8MM_GPIO1_LOW_IRQ =3D 64, FSL_IMX8MM_GPIO1_HIGH_IRQ =3D 65, FSL_IMX8MM_GPIO2_LOW_IRQ =3D 66, diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h index 7f0d55b349..b5d73c5e4b 100644 --- a/include/hw/timer/imx_gpt.h +++ b/include/hw/timer/imx_gpt.h @@ -6,6 +6,7 @@ * Originally written by Hans Jiang * Updated by Peter Chubb * Updated by Jean-Christophe Dubois + * Updated by Gaurav Sharma * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -81,6 +82,7 @@ #define TYPE_IMX6UL_GPT "imx6ul.gpt" #define TYPE_IMX7_GPT "imx7.gpt" #define TYPE_IMX8MP_GPT "imx8mp.gpt" +#define TYPE_IMX8MM_GPT "imx8mm.gpt" =20 #define TYPE_IMX_GPT TYPE_IMX25_GPT =20 --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 27 Apr 2026 05:47:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/63] hw/arm/fsl-imx8mm: Adding support for ENET ethernet controller Date: Mon, 27 Apr 2026 13:46:48 +0100 Message-ID: <20260427124738.966578-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294838078154100 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma It enables emulation of ENET ethernet controller in iMX8MM Enables testing and debugging of network dependent drivers Added ENET MAC IRQ lines Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx8mm.c | 24 ++++++++++++++++++++++++ hw/arm/imx8mm-evk.c | 1 + include/hw/arm/fsl-imx8mm.h | 10 +++++++++- 4 files changed, 35 insertions(+), 1 deletion(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 44dd401c8a..104954d90d 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -625,6 +625,7 @@ config FSL_IMX8MM select FSL_IMX8MP_ANALOG select FSL_IMX8MP_CCM select IMX + select IMX_FEC select IMX_I2C select OR_IRQ select SDHCI diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 3736191257..f1c173dbec 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -212,6 +212,8 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); } =20 + object_initialize_child(obj, "eth0", &s->enet, TYPE_IMX_ENET); + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -547,6 +549,21 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, spi_table[i].irq)); } =20 + /* ENET1 */ + object_property_set_uint(OBJECT(&s->enet), "phy-num", s->phy_num, + &error_abort); + object_property_set_uint(OBJECT(&s->enet), "tx-ring-num", 3, &error_ab= ort); + qemu_configure_nic_device(DEVICE(&s->enet), true, NULL); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->enet), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->enet), 0, + fsl_imx8mm_memmap[FSL_IMX8MM_ENET1].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 0, + qdev_get_gpio_in(gicdev, FSL_IMX8MM_ENET1_MAC_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->enet), 1, + qdev_get_gpio_in(gicdev, FSL_IMX6_ENET1_MAC_1588_IR= Q)); + /* SNVS */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { return; @@ -610,6 +627,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5: case FSL_IMX8MM_GPT1 ... FSL_IMX8MM_GPT6: case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3: + case FSL_IMX8MM_ENET1: case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4: case FSL_IMX8MM_PCIE1: case FSL_IMX8MM_PCIE_PHY1: @@ -631,10 +649,16 @@ static void fsl_imx8mm_realize(DeviceState *dev, Erro= r **errp) } } =20 +static const Property fsl_imx8mm_properties[] =3D { + DEFINE_PROP_UINT32("fec1-phy-num", FslImx8mmState, phy_num, 0), + DEFINE_PROP_BOOL("fec1-phy-connected", FslImx8mmState, phy_connected, = true), +}; + static void fsl_imx8mm_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 + device_class_set_props(dc, fsl_imx8mm_properties); dc->realize =3D fsl_imx8mm_realize; =20 dc->desc =3D "i.MX 8MM SoC"; diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c index dfdf3cd4f8..6b7774d3e2 100644 --- a/hw/arm/imx8mm-evk.c +++ b/hw/arm/imx8mm-evk.c @@ -79,6 +79,7 @@ static void imx8mm_evk_init(MachineState *machine) =20 s =3D FSL_IMX8MM(object_new_with_props(TYPE_FSL_IMX8MM, OBJECT(machine= ), "soc", &error_fatal, NULL)); + object_property_set_uint(OBJECT(s), "fec1-phy-num", 1, &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); =20 memory_region_add_subregion(get_system_memory(), FSL_IMX8MM_RAM_START, diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 607ac86666..bc5a0922ad 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -18,7 +18,8 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mp_analog.h" #include "hw/misc/imx8mp_ccm.h" -#include "hw/or-irq.h" +#include "hw/net/imx_fec.h" +#include "hw/core/or-irq.h" #include "hw/pci-host/designware.h" #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" @@ -60,11 +61,15 @@ struct FslImx8mmState { IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; MemoryRegion ocram; + IMXFECState enet; SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS]; IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; OrIRQState gpt5_gpt6_irq; + + uint32_t phy_num; + bool phy_connected; }; =20 enum FslImx8mmMemoryRegions { @@ -218,6 +223,9 @@ enum FslImx8mmIrqs { FSL_IMX8MM_WDOG2_IRQ =3D 79, FSL_IMX8MM_WDOG3_IRQ =3D 10, =20 + FSL_IMX8MM_ENET1_MAC_IRQ =3D 118, + FSL_IMX6_ENET1_MAC_1588_IRQ =3D 121, + FSL_IMX8MM_PCI_INTA_IRQ =3D 122, FSL_IMX8MM_PCI_INTB_IRQ =3D 123, FSL_IMX8MM_PCI_INTC_IRQ =3D 124, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294531; cv=none; d=zohomail.com; s=zohoarc; b=bsAEwM/5jNIFnvjSDdwG+5Jjyd6qvKS0OExVSvcLzc6E7ifjOvgazuB1soxarabL6hV9rY50G4u9dh9f87utZ6gvWfpo36/iuLUnJWIRHkFHziP6NVpZLsgyxGHnEmI60km5LR5Oc2PtPaylGNAS+OiO7E/HqLh8vT9d1OeAeL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294531; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=9V9ypQhZMA6beD24MyNKWxp8/BYxr4ugvwVwFV1KVGM=; b=bMmmnnmAdS7Ap4wrVB6QN0Sf90gmOhNsHXbHXGndeoocbigHcKReDVmKirLwIWWfxTyGNQcsrfoSSTpOky3gzaBN2X49CrNDgc8RqjAbPDEfaOdTGAZAaEXKGBXVEqQ9ZJynTkkU9Ri4Q6YYaQZH9tsx9fKb/2SwuzfT/9AucVo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294531517409.74949219963764; Mon, 27 Apr 2026 05:55:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLOv-0000jS-MV; Mon, 27 Apr 2026 08:49:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNa-0007tW-Mb for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:12 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNR-0005VG-VV for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:00 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-48a3e9862f0so54014845e9.1 for ; Mon, 27 Apr 2026 05:47:53 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:47:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/63] hw/arm/fsl-imx8mm: Adding support for USB controller Date: Mon, 27 Apr 2026 13:46:49 +0100 Message-ID: <20260427124738.966578-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294533028154100 Content-Type: text/plain; charset="utf-8" From: Gaurav Sharma It enables emulation of USB on iMX8MM Enables testing and debugging of USB drivers Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Peter Maydell Reviewed-by: Bernhard Beschow Signed-off-by: Gaurav Sharma Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx8mm.c | 27 +++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 6 ++++++ 3 files changed, 34 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 104954d90d..b940af9345 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -631,6 +631,7 @@ config FSL_IMX8MM select SDHCI select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_FSL_IMX8M_PHY + select USB_DWC3 select WDT_IMX2 =20 config FSL_IMX8MM_EVK diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index f1c173dbec..97c3f8542c 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -202,6 +202,11 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_USBS; i++) { + g_autofree char *name =3D g_strdup_printf("usb%d", i); + object_initialize_child(obj, name, &s->usb[i], TYPE_USB_DWC3); + } + for (i =3D 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) { g_autofree char *name =3D g_strdup_printf("spi%d", i + 1); object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); @@ -529,6 +534,27 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, usdhc_table[i].irq)); } =20 + /* USBs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_USBS; i++) { + static const struct { + hwaddr addr; + unsigned int irq; + } usb_table[FSL_IMX8MM_NUM_USBS] =3D { + { fsl_imx8mm_memmap[FSL_IMX8MM_USB1].addr, FSL_IMX8MM_USB1_IRQ= }, + { fsl_imx8mm_memmap[FSL_IMX8MM_USB2].addr, FSL_IMX8MM_USB2_IRQ= }, + }; + + qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p2", 1); + qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "p3", 1); + qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0, + qdev_get_gpio_in(gicdev, usb_table[i].irq)); + } + /* ECSPIs */ for (i =3D 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) { static const struct { @@ -635,6 +661,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_OCRAM: case FSL_IMX8MM_SNVS_HP: case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4: + case FSL_IMX8MM_USB1 ... FSL_IMX8MM_USB2: case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3: case FSL_IMX8MM_WDOG1 ... FSL_IMX8MM_WDOG3: /* device implemented and treated above */ diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index bc5a0922ad..60d79a6e3c 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -25,6 +25,7 @@ #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/timer/imx_gpt.h" +#include "hw/usb/hcd-dwc3.h" #include "hw/watchdog/wdt_imx2.h" #include "qom/object.h" #include "qemu/units.h" @@ -43,6 +44,7 @@ enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_I2CS =3D 4, FSL_IMX8MM_NUM_IRQS =3D 128, FSL_IMX8MM_NUM_UARTS =3D 4, + FSL_IMX8MM_NUM_USBS =3D 2, FSL_IMX8MM_NUM_USDHCS =3D 3, FSL_IMX8MM_NUM_WDTS =3D 3, }; @@ -64,6 +66,7 @@ struct FslImx8mmState { IMXFECState enet; SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS]; IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS]; + USBDWC3 usb[FSL_IMX8MM_NUM_USBS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; OrIRQState gpt5_gpt6_irq; @@ -202,6 +205,9 @@ enum FslImx8mmIrqs { FSL_IMX8MM_I2C3_IRQ =3D 37, FSL_IMX8MM_I2C4_IRQ =3D 38, =20 + FSL_IMX8MM_USB1_IRQ =3D 40, + FSL_IMX8MM_USB2_IRQ =3D 41, + FSL_IMX8MM_GPT1_IRQ =3D 55, FSL_IMX8MM_GPT2_IRQ =3D 54, FSL_IMX8MM_GPT3_IRQ =3D 53, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294681; cv=none; d=zohomail.com; s=zohoarc; b=liyRqC+GNAV96zoNw70KGETagM1v/0SoG4mHimDiuhbYtJ0p5TarZNZLHuAfSBdYE/P6329CTs67/MLCh5RzEu3r3p0WLZsfqQCvMaZRzNNGPkFoE5ucrD7mD06YI5a3AfsebNHHIO7MNh0HZu2Oi6GhgNH8/pvv8rxaE+umdjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294681; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=lrmjgu0DENSyxUCVcnWjBPDdGhFkQDou3KySNjf2DPs=; b=aJanvj2GkOczMjhYGnU7u8wNXRChJTUfLNdsCOkvzTZrMyWtLG3AA5kD2mbNh8XIH2RM9RgXApFrpK/zaI9Tpxp0HMRA1kFu7iu4hu5qLjOpmPvaMk4qhjggufD43G5nP/pF0ETVVV3cwBdPwgGVXCgbiMJpIE227dm8YzrDztQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294681190445.9516740454975; Mon, 27 Apr 2026 05:58:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUI-0006nS-Bi; Mon, 27 Apr 2026 08:55:00 -0400 Received: from eggs.gnu.org ([209.51.188.92]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLSj-0004O0-Lh for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:53:29 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNV-0005VV-GM for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:00 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-48909558b3aso102132225e9.0 for ; Mon, 27 Apr 2026 05:47:54 -0700 (PDT) Received: from lanath.. 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If it succeeds, it will return:- ok 1 test_imx8mm_evk.Imx8mmEvkMachine.test_aarch64_imx8mm_evk_usdhc Signed-off-by: Gaurav Sharma Reviewed-by: Thomas Huth Reviewed-by: Bernhard Beschow [PMM: Add missing blank lines that flake8 wants] Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + tests/functional/aarch64/meson.build | 2 + tests/functional/aarch64/test_imx8mm_evk.py | 69 +++++++++++++++++++++ 3 files changed, 72 insertions(+) create mode 100755 tests/functional/aarch64/test_imx8mm_evk.py diff --git a/MAINTAINERS b/MAINTAINERS index 8167d42876..8d980d6c40 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -921,6 +921,7 @@ F: hw/arm/fsl-imx8mm.c F: hw/arm/imx8mm-evk.c F: include/hw/arm/fsl-imx8mm.h F: docs/system/arm/imx8m.rst +F: tests/functional/aarch64/test_imx8mm_evk.py =20 MCIMX8MP-EVK / i.MX8MP M: Bernhard Beschow diff --git a/tests/functional/aarch64/meson.build b/tests/functional/aarch6= 4/meson.build index 7ea8c22b04..1067f181f2 100644 --- a/tests/functional/aarch64/meson.build +++ b/tests/functional/aarch64/meson.build @@ -5,6 +5,7 @@ test_aarch64_timeouts =3D { 'aspeed_ast2700a2' : 600, 'aspeed_ast2700fc' : 600, 'device_passthrough' : 720, + 'imx8mm_evk' : 240, 'imx8mp_evk' : 240, 'raspi4' : 480, 'reverse_debug' : 180, @@ -29,6 +30,7 @@ tests_aarch64_system_thorough =3D [ 'aspeed_ast2700fc', 'device_passthrough', 'hotplug_pci', + 'imx8mm_evk', 'imx8mp_evk', 'kvm', 'multiprocess', diff --git a/tests/functional/aarch64/test_imx8mm_evk.py b/tests/functional= /aarch64/test_imx8mm_evk.py new file mode 100755 index 0000000000..86725991f1 --- /dev/null +++ b/tests/functional/aarch64/test_imx8mm_evk.py @@ -0,0 +1,69 @@ +#!/usr/bin/env python3 +# +# Functional test that boots a Linux kernel and checks the console +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest, Asset + + +class Imx8mmEvkMachine(LinuxKernelTest): + + ASSET_IMAGE =3D Asset( + ('https://cloud.debian.org/images/cloud/bookworm/20231210-1590/' + 'debian-12-generic-arm64-20231210-1590.tar.xz'), + '7ebf1577b32d5af6204df74b54ca2e4675de9b5a9fa14f3ff70b88eeb7b3b359') + + KERNEL_OFFSET =3D 0x51000000 + KERNEL_SIZE =3D 32622528 + INITRD_OFFSET =3D 0x76000000 + INITRD_SIZE =3D 30987766 + DTB_OFFSET =3D 0x64DB5000 + DTB_SIZE =3D 36812 + + def extract(self, in_path, out_path, offset, size): + try: + with open(in_path, "rb") as source: + source.seek(offset) + data =3D source.read(size) + with open(out_path, "wb") as target: + target.write(data) + except (IOError, ValueError) as e: + self.log.error(f"Failed to extract {out_path}: {e}") + raise + + def setUp(self): + super().setUp() + + self.image_path =3D self.scratch_file("disk.raw") + self.kernel_path =3D self.scratch_file("linux") + self.initrd_path =3D self.scratch_file("initrd.zstd") + self.dtb_path =3D self.scratch_file("imx8mm-evk.dtb") + + self.archive_extract(self.ASSET_IMAGE) + self.extract(self.image_path, self.kernel_path, + self.KERNEL_OFFSET, self.KERNEL_SIZE) + self.extract(self.image_path, self.initrd_path, + self.INITRD_OFFSET, self.INITRD_SIZE) + self.extract(self.image_path, self.dtb_path, + self.DTB_OFFSET, self.DTB_SIZE) + + def test_aarch64_imx8mm_evk_usdhc(self): + self.require_accelerator("tcg") + self.set_machine('imx8mm-evk') + self.vm.set_console(console_index=3D1) + self.vm.add_args('-m', '2G', + '-smp', '4', + '-kernel', self.kernel_path, + '-initrd', self.initrd_path, + '-dtb', self.dtb_path, + '-append', 'root=3D/dev/mmcblk2p1', + '-drive', f'file=3D{self.image_path},if=3Dsd,bus= =3D2,' + 'format=3Draw,id=3Dmmcblk2,snapshot=3D= on') + + self.vm.launch() + self.wait_for_console_pattern('Welcome to ') + + +if __name__ =3D=3D '__main__': + LinuxKernelTest.main() --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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So we could simply drop MO_TE. That would produce a store in host-endianness, which will be fractionally more efficient on some hosts. [*] https://lore.kernel.org/qemu-devel/d64d3576-9188-4e74-afdc-3492c9feb8e0= @linaro.org/ Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260414005348.4767-2-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/helper-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index a7372aa6bb..dd1f9c6dc6 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -1019,7 +1019,7 @@ static uint64_t set_step_tags(CPUARMState *env, uint6= 4_t toaddr, * the page dirty and will use the fast path. */ uint64_t repldata =3D data * 0x0101010101010101ULL; - MemOpIdx oi16 =3D make_memop_idx(MO_TE | MO_128, memidx); + MemOpIdx oi16 =3D make_memop_idx(MO_128, memidx); cpu_st16_mmu(env, toaddr, int128_make128(repldata, repldata), oi16= , ra); mte_mops_set_tags(env, toaddr, 16, *mtedesc); return 16; --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294923; cv=none; d=zohomail.com; s=zohoarc; b=SI15EtkOHKLQF1LgASoKe0N5NnWFPO6iEpVBh5V80soY0ojMqLsu6xnZ+Nt67fVSuS4b48gwr5BD0E5sW7rocFANt+xd9RNRU18yK3PAcfyR+JvS/7xG/GPdYmj2Nkc+22qh/HusaR1EZAwlQZgQnbgB/VniBk1J3A4UWYLIk28= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294923; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=HVojIB/7QdY0Ot24jw0NheQh8MehpPZMmEg2nTnK4fY=; b=QpNk3undUi2Mj5Q4I/qBNuO/QA6e8IILaIzeZCAJqVl+iNo14SCpIVV84fKjvVwCvlbW4MPE0X5bngJJ7mia8YTlc1exWwxUfmeL2jRpew97pmn3d8hlkbPLNi+RnMsR3SqY2J+9+5SQX4bkRtKFyRBarc6k3gtr8P6CIF5wRAQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294923956447.8832657698007; Mon, 27 Apr 2026 06:02:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLa9-0004Qt-HP; Mon, 27 Apr 2026 09:01:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLZy-0004Hk-U5 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 09:00:51 -0400 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLZw-0002Z2-42 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 09:00:50 -0400 Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-678adefbd26so4721243a12.3 for ; Mon, 27 Apr 2026 06:00:47 -0700 (PDT) Received: from lanath.. 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Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/arm); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260414005348.4767-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/m_helper.c | 6 +-- target/arm/tcg/mve_helper.c | 79 ++++++++++++++++++++----------------- 2 files changed, 45 insertions(+), 40 deletions(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index a0cb8cb021..f5954ce9bf 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -634,7 +634,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) =20 /* Note that these stores can throw exceptions on MPU faults */ ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); cpu_stl_mmu(env, sp, nextinst, oi, GETPC()); cpu_stl_mmu(env, sp + 4, saved_psr, oi, GETPC()); @@ -1055,7 +1055,7 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fpt= r) bool lspact =3D env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; uintptr_t ra =3D GETPC(); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); =20 assert(env->v7m.secure); @@ -1131,7 +1131,7 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) ARMCPU *cpu =3D env_archcpu(env); uintptr_t ra =3D GETPC(); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); =20 /* fptr is the value of Rn, the frame pointer we load the FP regs from= */ diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index a67d90d6c7..cc58e0502f 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -194,23 +194,23 @@ static void mve_advance_vpt(CPUARMState *env) } =20 DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t) -DO_VLDR(vldrh, MO_TEUW, 2, uint16_t, ldw, 2, uint16_t) -DO_VLDR(vldrw, MO_TEUL, 4, uint32_t, ldl, 4, uint32_t) +DO_VLDR(vldrh, MO_TE | MO_UW, 2, uint16_t, ldw, 2, uint16_t) +DO_VLDR(vldrw, MO_TE | MO_UL, 4, uint32_t, ldl, 4, uint32_t) =20 DO_VSTR(vstrb, MO_UB, 1, stb, 1, uint8_t) -DO_VSTR(vstrh, MO_TEUW, 2, stw, 2, uint16_t) -DO_VSTR(vstrw, MO_TEUL, 4, stl, 4, uint32_t) +DO_VSTR(vstrh, MO_TE | MO_UW, 2, stw, 2, uint16_t) +DO_VSTR(vstrw, MO_TE | MO_UL, 4, stl, 4, uint32_t) =20 DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t) DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t) DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t) DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t) -DO_VLDR(vldrh_sw, MO_TESW, 2, int16_t, ldw, 4, int32_t) -DO_VLDR(vldrh_uw, MO_TEUW, 2, uint16_t, ldw, 4, uint32_t) +DO_VLDR(vldrh_sw, MO_TE | MO_SW, 2, int16_t, ldw, 4, int32_t) +DO_VLDR(vldrh_uw, MO_TE | MO_UW, 2, uint16_t, ldw, 4, uint32_t) =20 DO_VSTR(vstrb_h, MO_UB, 1, stb, 2, int16_t) DO_VSTR(vstrb_w, MO_UB, 1, stb, 4, int32_t) -DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) +DO_VSTR(vstrh_w, MO_TE | MO_UW, 2, stw, 4, int32_t) =20 #undef DO_VLDR #undef DO_VSTR @@ -295,7 +295,7 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ if (!(eci_mask & 1)) { \ continue; \ @@ -321,7 +321,7 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ if (!(eci_mask & 1)) { \ continue; \ @@ -345,42 +345,47 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) =20 DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD= , false) DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD= , false) -DO_VLDR_SG(vldrh_sg_sw, MO_TESW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_= ADD, false) +DO_VLDR_SG(vldrh_sg_sw, MO_TE | MO_SW, int16_t, ldw, 4, + int32_t, uint32_t, ADDR_ADD, false) =20 DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD= , false) DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_A= DD, false) DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_A= DD, false) -DO_VLDR_SG(vldrh_sg_uh, MO_TEUW, uint16_t, ldw, 2, uint16_t, uint16_t, ADD= R_ADD, false) -DO_VLDR_SG(vldrh_sg_uw, MO_TEUW, uint16_t, ldw, 4, uint32_t, uint32_t, ADD= R_ADD, false) -DO_VLDR_SG(vldrw_sg_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADD= R_ADD, false) +DO_VLDR_SG(vldrh_sg_uh, MO_TE | MO_UW, uint16_t, ldw, 2, + uint16_t, uint16_t, ADDR_ADD, false) +DO_VLDR_SG(vldrh_sg_uw, MO_TE | MO_UW, uint16_t, ldw, 4, + uint32_t, uint32_t, ADDR_ADD, false) +DO_VLDR_SG(vldrw_sg_uw, MO_TE | MO_UL, uint32_t, ldl, 4, + uint32_t, uint32_t, ADDR_ADD, false) DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) =20 -DO_VLDR_SG(vldrh_sg_os_sw, MO_TESW, int16_t, ldw, 4, +DO_VLDR_SG(vldrh_sg_os_sw, MO_TE | MO_SW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrh_sg_os_uh, MO_TEUW, uint16_t, ldw, 2, +DO_VLDR_SG(vldrh_sg_os_uh, MO_TE | MO_UW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrh_sg_os_uw, MO_TEUW, uint16_t, ldw, 4, +DO_VLDR_SG(vldrh_sg_os_uw, MO_TE | MO_UW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrw_sg_os_uw, MO_TEUL, uint32_t, ldl, 4, +DO_VLDR_SG(vldrw_sg_os_uw, MO_TE | MO_UL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false) DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) =20 DO_VSTR_SG(vstrb_sg_ub, MO_UB, stb, 1, uint8_t, ADDR_ADD, false) DO_VSTR_SG(vstrb_sg_uh, MO_UB, stb, 2, uint16_t, ADDR_ADD, false) DO_VSTR_SG(vstrb_sg_uw, MO_UB, stb, 4, uint32_t, ADDR_ADD, false) -DO_VSTR_SG(vstrh_sg_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD, false) -DO_VSTR_SG(vstrh_sg_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD, false) -DO_VSTR_SG(vstrw_sg_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrw_sg_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, false) DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) =20 -DO_VSTR_SG(vstrh_sg_os_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD_OSH, false) -DO_VSTR_SG(vstrh_sg_os_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD_OSH, false) -DO_VSTR_SG(vstrw_sg_os_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD_OSW, false) +DO_VSTR_SG(vstrh_sg_os_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD_OSH, = false) +DO_VSTR_SG(vstrh_sg_os_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD_OSH, = false) +DO_VSTR_SG(vstrw_sg_os_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD_OSW, = false) DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) =20 -DO_VLDR_SG(vldrw_sg_wb_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, = ADDR_ADD, true) +DO_VLDR_SG(vldrw_sg_wb_uw, MO_TE | MO_UL, uint32_t, ldl, 4, + uint32_t, uint32_t, ADDR_ADD, true) DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) -DO_VSTR_SG(vstrw_sg_wb_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, true) +DO_VSTR_SG(vstrw_sg_wb_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, true) DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) =20 /* @@ -408,7 +413,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ uint32_t addr, data; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -434,7 +439,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) int y; /* y counts 0 2 0 2 */ \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -461,7 +466,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) uint32_t *qd; \ int y; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -500,7 +505,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) uint32_t addr, data; \ uint8_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -526,7 +531,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) int e; \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -551,7 +556,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) uint32_t addr, data; \ uint32_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -582,7 +587,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ uint32_t addr, data; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -609,7 +614,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) int y; /* y counts 0 2 0 2 */ \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -635,7 +640,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) uint32_t *qd; \ int y; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -674,7 +679,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) uint32_t addr, data; \ uint8_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -701,7 +706,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) int e; \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -727,7 +732,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) uint32_t addr, data; \ uint32_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Mon, 27 Apr 2026 05:47:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/63] target/arm: Hoist MO_TE into mve_advance_vpt() Date: Mon, 27 Apr 2026 13:46:53 +0100 Message-ID: <20260427124738.966578-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294528872154100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260414005348.4767-4-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/mve_helper.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index cc58e0502f..fbb64889bf 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -160,7 +160,8 @@ static void mve_advance_vpt(CPUARMState *env) uint16_t eci_mask =3D mve_eci_mask(env); \ unsigned b, e; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \ + mmu_idx); \ /* \ * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ * beats so we don't care if we update part of the dest and \ @@ -183,7 +184,8 @@ static void mve_advance_vpt(CPUARMState *env) uint16_t mask =3D mve_element_mask(env); \ unsigned b, e; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \ + mmu_idx); \ for (b =3D 0, e =3D 0; b < 16; b +=3D ESIZE, e++) { = \ if (mask & (1 << b)) { \ cpu_##STTYPE##_mmu(env, addr, d[H##ESIZE(e)], oi, GETPC())= ; \ @@ -194,23 +196,23 @@ static void mve_advance_vpt(CPUARMState *env) } =20 DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t) -DO_VLDR(vldrh, MO_TE | MO_UW, 2, uint16_t, ldw, 2, uint16_t) -DO_VLDR(vldrw, MO_TE | MO_UL, 4, uint32_t, ldl, 4, uint32_t) +DO_VLDR(vldrh, MO_UW, 2, uint16_t, ldw, 2, uint16_t) +DO_VLDR(vldrw, MO_UL, 4, uint32_t, ldl, 4, uint32_t) =20 DO_VSTR(vstrb, MO_UB, 1, stb, 1, uint8_t) -DO_VSTR(vstrh, MO_TE | MO_UW, 2, stw, 2, uint16_t) -DO_VSTR(vstrw, MO_TE | MO_UL, 4, stl, 4, uint32_t) +DO_VSTR(vstrh, MO_UW, 2, stw, 2, uint16_t) +DO_VSTR(vstrw, MO_UL, 4, stl, 4, uint32_t) =20 DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t) DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t) DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t) DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t) -DO_VLDR(vldrh_sw, MO_TE | MO_SW, 2, int16_t, ldw, 4, int32_t) -DO_VLDR(vldrh_uw, MO_TE | MO_UW, 2, uint16_t, ldw, 4, uint32_t) +DO_VLDR(vldrh_sw, MO_SW, 2, int16_t, ldw, 4, int32_t) +DO_VLDR(vldrh_uw, MO_UW, 2, uint16_t, ldw, 4, uint32_t) =20 DO_VSTR(vstrb_h, MO_UB, 1, stb, 2, int16_t) DO_VSTR(vstrb_w, MO_UB, 1, stb, 4, int32_t) -DO_VSTR(vstrh_w, MO_TE | MO_UW, 2, stw, 4, int32_t) +DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t) =20 #undef DO_VLDR #undef DO_VSTR --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 27 Apr 2026 05:47:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/63] target/arm: Hoist MO_TE into MVE DO_VSTR() macro Date: Mon, 27 Apr 2026 13:46:54 +0100 Message-ID: <20260427124738.966578-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294526786158500 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260414005348.4767-5-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/mve_helper.c | 43 +++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index fbb64889bf..4bea0991de 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -235,7 +235,8 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \ + mmu_idx); \ for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE, eci_mask >>= =3D ESIZE) { \ if (!(eci_mask & 1)) { \ continue; \ @@ -262,7 +263,8 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \ + mmu_idx); \ for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE, eci_mask >>= =3D ESIZE) { \ if (!(eci_mask & 1)) { \ continue; \ @@ -347,47 +349,42 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t) =20 DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD= , false) DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD= , false) -DO_VLDR_SG(vldrh_sg_sw, MO_TE | MO_SW, int16_t, ldw, 4, - int32_t, uint32_t, ADDR_ADD, false) +DO_VLDR_SG(vldrh_sg_sw, MO_SW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_AD= D, false) =20 DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD= , false) DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_A= DD, false) DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_A= DD, false) -DO_VLDR_SG(vldrh_sg_uh, MO_TE | MO_UW, uint16_t, ldw, 2, - uint16_t, uint16_t, ADDR_ADD, false) -DO_VLDR_SG(vldrh_sg_uw, MO_TE | MO_UW, uint16_t, ldw, 4, - uint32_t, uint32_t, ADDR_ADD, false) -DO_VLDR_SG(vldrw_sg_uw, MO_TE | MO_UL, uint32_t, ldl, 4, - uint32_t, uint32_t, ADDR_ADD, false) +DO_VLDR_SG(vldrh_sg_uh, MO_UW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_= ADD, false) +DO_VLDR_SG(vldrh_sg_uw, MO_UW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_= ADD, false) +DO_VLDR_SG(vldrw_sg_uw, MO_UL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_= ADD, false) DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) =20 -DO_VLDR_SG(vldrh_sg_os_sw, MO_TE | MO_SW, int16_t, ldw, 4, +DO_VLDR_SG(vldrh_sg_os_sw, MO_SW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrh_sg_os_uh, MO_TE | MO_UW, uint16_t, ldw, 2, +DO_VLDR_SG(vldrh_sg_os_uh, MO_UW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrh_sg_os_uw, MO_TE | MO_UW, uint16_t, ldw, 4, +DO_VLDR_SG(vldrh_sg_os_uw, MO_UW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrw_sg_os_uw, MO_TE | MO_UL, uint32_t, ldl, 4, +DO_VLDR_SG(vldrw_sg_os_uw, MO_UL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false) DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) =20 DO_VSTR_SG(vstrb_sg_ub, MO_UB, stb, 1, uint8_t, ADDR_ADD, false) DO_VSTR_SG(vstrb_sg_uh, MO_UB, stb, 2, uint16_t, ADDR_ADD, false) DO_VSTR_SG(vstrb_sg_uw, MO_UB, stb, 4, uint32_t, ADDR_ADD, false) -DO_VSTR_SG(vstrh_sg_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD, false) -DO_VSTR_SG(vstrh_sg_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD, false) -DO_VSTR_SG(vstrw_sg_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uh, MO_UW, stw, 2, uint16_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uw, MO_UW, stw, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrw_sg_uw, MO_UL, stl, 4, uint32_t, ADDR_ADD, false) DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) =20 -DO_VSTR_SG(vstrh_sg_os_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD_OSH, = false) -DO_VSTR_SG(vstrh_sg_os_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD_OSH, = false) -DO_VSTR_SG(vstrw_sg_os_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD_OSW, = false) +DO_VSTR_SG(vstrh_sg_os_uh, MO_UW, stw, 2, uint16_t, ADDR_ADD_OSH, false) +DO_VSTR_SG(vstrh_sg_os_uw, MO_UW, stw, 4, uint32_t, ADDR_ADD_OSH, false) +DO_VSTR_SG(vstrw_sg_os_uw, MO_UL, stl, 4, uint32_t, ADDR_ADD_OSW, false) DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) =20 -DO_VLDR_SG(vldrw_sg_wb_uw, MO_TE | MO_UL, uint32_t, ldl, 4, - uint32_t, uint32_t, ADDR_ADD, true) +DO_VLDR_SG(vldrw_sg_wb_uw, MO_UL, uint32_t, ldl, 4, uint32_t, uint32_t, AD= DR_ADD, true) DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) -DO_VSTR_SG(vstrw_sg_wb_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, true) +DO_VSTR_SG(vstrw_sg_wb_uw, MO_UL, stl, 4, uint32_t, ADDR_ADD, true) DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) =20 /* --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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MO_BE : MO_LE; +} + static inline int arm_env_mmu_index(CPUARMState *env) { return EX_TBFLAG_ANY(env->hflags, MMUIDX); diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 4bea0991de..a5a23c9705 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -299,7 +299,8 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ if (!(eci_mask & 1)) { \ continue; \ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294905; cv=none; d=zohomail.com; s=zohoarc; b=C/6QZL4ikByBK/gmQwOmcS1queaAJoyfDpihKaihfvSFx+EootHPR3BwK2z2+T7rq0ySU/4qKzkL61WO0FRMG/PcGyY4PXv77EXc6kWD0I3nwfjZnNAqB2uj7Sr6D6wcG9VJpy5DNN9WbX0MWvgMHG0npHPsAz8Aam2hrat8PLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294905; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=QHjElnEbH83AeQYXqjknRBF7S35lhCc1cC2LPJvmubE=; b=KkPDSx231h/xujoZ1hI+E+li5Ftk/prwsBUMXLsq5zcwScak6wbEExv+Izmcl0ADLsXCc/lKRK1lt6F7rIFazOQoirluRRddv1OasQcB8m1+nQ2A1XnnxyYoXsNdJKbqFybzbZGyeypl+TIAKBGfsY58PTyBB5Hwsv+O8Qm1pAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294905533658.7951654825549; Mon, 27 Apr 2026 06:01:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLRO-0003qx-ON; Mon, 27 Apr 2026 08:52:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNc-00080l-Rb for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:16 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNZ-0005eC-D6 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:04 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-48984d29fe3so122375705e9.0 for ; Mon, 27 Apr 2026 05:47:59 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:47:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/63] target/arm: Replace MO_TE -> mo_endian() for MVE helpers Date: Mon, 27 Apr 2026 13:46:56 +0100 Message-ID: <20260427124738.966578-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294907510158500 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260414005348.4767-7-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/mve_helper.c | 47 +++++++++++++++++++++++-------------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index a5a23c9705..64ab804abc 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -160,7 +160,7 @@ static void mve_advance_vpt(CPUARMState *env) uint16_t eci_mask =3D mve_eci_mask(env); \ unsigned b, e; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MFLAG | MO_ALIGN, \ mmu_idx); \ /* \ * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ @@ -184,7 +184,7 @@ static void mve_advance_vpt(CPUARMState *env) uint16_t mask =3D mve_element_mask(env); \ unsigned b, e; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MFLAG | MO_ALIGN, \ mmu_idx); \ for (b =3D 0, e =3D 0; b < 16; b +=3D ESIZE, e++) { = \ if (mask & (1 << b)) { \ @@ -235,7 +235,7 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MFLAG | MO_ALIGN, \ mmu_idx); \ for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE, eci_mask >>= =3D ESIZE) { \ if (!(eci_mask & 1)) { \ @@ -263,7 +263,7 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MFLAG | MO_ALIGN, \ mmu_idx); \ for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE, eci_mask >>= =3D ESIZE) { \ if (!(eci_mask & 1)) { \ @@ -326,7 +326,8 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ if (!(eci_mask & 1)) { \ continue; \ @@ -413,7 +414,8 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ uint32_t addr, data; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -439,7 +441,8 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) int y; /* y counts 0 2 0 2 */ \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -466,7 +469,8 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) uint32_t *qd; \ int y; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -505,7 +509,8 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) uint32_t addr, data; \ uint8_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -531,7 +536,8 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) int e; \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -556,7 +562,8 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) uint32_t addr, data; \ uint32_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -587,7 +594,8 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ uint32_t addr, data; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -614,7 +622,8 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) int y; /* y counts 0 2 0 2 */ \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -640,7 +649,8 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) uint32_t *qd; \ int y; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -679,7 +689,8 @@ DO_VST4W(vst43w, 6, 7, 8, 9) uint32_t addr, data; \ uint8_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -706,7 +717,8 @@ DO_VST4W(vst43w, 6, 7, 8, 9) int e; \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -732,7 +744,8 @@ DO_VST4W(vst43w, 6, 7, 8, 9) uint32_t addr, data; \ uint32_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, \ + mmu_idx); \ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 27 Apr 2026 05:47:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/63] target/arm: Compile mve_helper.c once Date: Mon, 27 Apr 2026 13:46:57 +0100 Message-ID: <20260427124738.966578-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294625390158500 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260414005348.4767-8-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/meson.build | 3 ++- target/arm/tcg/mve_helper.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 506f031f1a..95e9da151e 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -33,7 +33,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs= 32.c')) arm_ss.add(files( 'cpu32.c', 'm_helper.c', - 'mve_helper.c', )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( @@ -71,6 +70,7 @@ arm_common_system_ss.add( 'debug.c', 'hflags.c', 'gengvec.c', + 'mve_helper.c', 'neon_helper.c', 'op_helper.c', 'psci.c', @@ -94,6 +94,7 @@ arm_user_ss.add( 'debug.c', 'gengvec.c', 'hflags.c', + 'mve_helper.c', 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 64ab804abc..09ae233416 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -23,7 +23,7 @@ #include "helper-mve.h" #include "internals.h" #include "vec_internal.h" -#include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ldst-common.h" #include "tcg/tcg.h" #include "fpu/softfloat.h" #include "crypto/clmul.h" --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 27 Apr 2026 05:48:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/63] target/arm: Replace MO_TE -> mo_endian() for Cortex-M helpers Date: Mon, 27 Apr 2026 13:46:58 +0100 Message-ID: <20260427124738.966578-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294307565158500 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260414005348.4767-9-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/m_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index f5954ce9bf..1bec8e9aea 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -634,7 +634,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) =20 /* Note that these stores can throw exceptions on MPU faults */ ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); cpu_stl_mmu(env, sp, nextinst, oi, GETPC()); cpu_stl_mmu(env, sp + 4, saved_psr, oi, GETPC()); @@ -1055,7 +1055,7 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fpt= r) bool lspact =3D env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; uintptr_t ra =3D GETPC(); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); =20 assert(env->v7m.secure); @@ -1131,7 +1131,7 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) ARMCPU *cpu =3D env_archcpu(env); uintptr_t ra =3D GETPC(); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); =20 /* fptr is the value of Rn, the frame pointer we load the FP regs from= */ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 27 Apr 2026 05:48:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/63] target/arm: Compile m_helper.c once Date: Mon, 27 Apr 2026 13:46:59 +0100 Message-ID: <20260427124738.966578-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294496636154100 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260414005348.4767-10-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/meson.build | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 1bec8e9aea..f2059ed8b0 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -17,7 +17,7 @@ #include "qemu/log.h" #include "exec/page-protection.h" #ifdef CONFIG_TCG -#include "accel/tcg/cpu-ldst.h" +#include "accel/tcg/cpu-ldst-common.h" #include "semihosting/common-semi.h" #endif #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 95e9da151e..02774409e5 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -32,7 +32,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs= 32.c')) =20 arm_ss.add(files( 'cpu32.c', - 'm_helper.c', )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( @@ -70,6 +69,7 @@ arm_common_system_ss.add( 'debug.c', 'hflags.c', 'gengvec.c', + 'm_helper.c', 'mve_helper.c', 'neon_helper.c', 'op_helper.c', @@ -94,6 +94,7 @@ arm_user_ss.add( 'debug.c', 'gengvec.c', 'hflags.c', + 'm_helper.c', 'mve_helper.c', 'neon_helper.c', 'op_helper.c', --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294084; x=1777898884; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WDavdCu+Xke+C7HS6Rur5ErMcRioXqigfD2Cj7+MUEs=; b=b9m6uQNwlK9iMEXk/NLxJW5LKyjwJAZr64+J6/L3gIUZSa2xj5/EwSgw9c9oQjs1iG 7knzdxr085b0NMBnRODLaOP1RFF52awkeh+n3y2zgOvcmQxdu5VC6sfTeUSrAcmHE3xa /bUI8EEHLhF/BiLskxFmEMv9CtzA//WbnRDsACQMqY1B25ToFUX7fuvmeyy6f7BQ8w4d iFAE8EIfD765bN4/B7fJIBRYnMniJdbbPiX+ZiIqMFQEyn6LMcPf4zRCa+7xiKnO0iZQ 8GSVbeMaZmS/iVfiW+D0S46ucWn1ZOIqSdG1bHOsVlj4ZRcDI0NFdrt02qGDuDZr5nbm 5kzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294084; x=1777898884; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=WDavdCu+Xke+C7HS6Rur5ErMcRioXqigfD2Cj7+MUEs=; b=MuErwJojgtm6GiLURIbyznFXCI5ngY1qg2TEVpAuY4qjO3IRg8g/8gBqLQIire9lX5 oaHE+0wDxeVvzNDVmqXwStdunsXAeF5Mk/idfq9K7zGXRiSl3+Y/uur2zV7WgB1CRKxx ut9UZYFe31KIbkoqDJPsfu4urP7rl/4aYk1qSkasyt1F5wIveEzsXIySY5FDJt52XOr2 /tXxNbsYoFmxA5bSSZpxglCucFhNjOgkNuDYB+LTIE7EE0vjEQ3ibk3Z1ZMH8BDGWwqM dWrtveADIscgic/lAeQkeTy2SaMCOr6soqGF2vd1yJR5HkZZO3qLqI4ELOtyWsc1nJ+g 5yww== X-Gm-Message-State: AOJu0YwYrJnGo2wfJICHISbJRTKVyCJ7N/8Y3GIyaFHwbBQBAB87DOnW Ee0D1r5NcmfKFmzwv5b4O3p8YwHI5S2k0zuOvUJZwk2OKE1hDsv0SUP04dBRhkfBxtEvYpEHv3m hREwG X-Gm-Gg: AeBDiesHHnyAB+aFeh+JUQV9lncT+3iMAocpjddvlRsHYHPsq+ZexBFo6vq4fz25r/I 2/jsvkZt24OEOXPduLnHgc0/Uq8wowqjY0p0aJuBcebPNE7hsHUWvS/Xsx8yMqeBvqkSWXD7s+I ozDlcm7wpo+eRQJ0j95YDF48srb9MmvyuIp21NvkcKaKn1Xki9OALe37kq9AsCsRNud+3Zx+bqp atuNthDMwMwJELFjGS4GNurtFbCYlgZldvLzUYQXWz8ueRHo73I44ff3UbaqaA9yxxsvjZ1ExUG Gq7Xcapm2Oz+sgeR5IVxUmg+aRbj12ELQ84uZYJXgY8guJGM6HjNfwKvN9cExyfpYf3iXgO/XfK DAtnQvwgPTQqQaxgE4PHRwlixQNgQ+MvafIclw/3+d2NgFzgyrJs3n9DCw4cKBBkCvZkbisXLsX hd/+fMbLRRSpAiimSTI+hJS4brjDd4XBXMUAeI4UuzLQYi0varLXeAt8XHdUrv2jj/BaVZP/fO+ Xk77Y+15z5O/Sks7N7Duxgzjaq4hcGS8Sn+nziEXA== X-Received: by 2002:a05:600c:c4ab:b0:487:1fb4:7e1 with SMTP id 5b1f17b1804b1-488fb7864c3mr616732525e9.22.1777294083600; Mon, 27 Apr 2026 05:48:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/63] hw/arm: Remove hw_error() for the unimplemented CM_LMBUSCNT register Date: Mon, 27 Apr 2026 13:47:00 +0100 Message-ID: <20260427124738.966578-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294736003154100 From: Thomas Huth When writing to this register, QEMU currently aborts: $ echo "readl 0x10000018" | ./qemu-system-arm -audiodev none,id=3Dsnd0 \ -M integratorcp,accel=3Dqtest,audiodev=3Dsnd0 -display none -qtest stdio [I 0.000000] OPENED [R +0.001907] readl 0x10000018 qemu: hardware error: integratorcm_read: CM_LMBUSCNT [...] Aborted (core dumped) This is bad, a guest should ideally never be able to kill QEMU like this. Now, according to the "Intergrator/CP User Guide" from: https://developer.arm.com/documentation/dui0159/b/porting-integrator-ap-an= d-im-pd1/registers "The Integrator/AP CM_LMBUSCNT has been removed." That means this register does not seem to be implemented on real CP boards at all, only for older AP boards. Thus it should be fine if we simply ignore this register in QEMU and handle it like all other unimplemented registers in the "default" handler of the case statement. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3407 Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260420064933.64765-1-thuth@redhat.com Signed-off-by: Peter Maydell --- hw/arm/integratorcp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 03633f3d4f..164af03f7b 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -106,9 +106,6 @@ static uint64_t integratorcm_read(void *opaque, hwaddr = offset, } else { return s->cm_lock; } - case 6: /* CM_LMBUSCNT */ - /* ??? High frequency timer. */ - hw_error("integratorcm_read: CM_LMBUSCNT"); case 7: /* CM_AUXOSC */ return s->cm_auxosc; case 8: /* CM_SDRAM */ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294730; cv=none; d=zohomail.com; s=zohoarc; b=Vw7kZFV7/STyTr+B/kUAL5C0VI2SPHXuQHobfk/gl76JonWAKYufcRQ6K+cbH0FGORrFgW4NeIr4fHyFH+1w6qFQWaMKSu9lgWJcybd/JB8CMsWYB3xRU0fHe3DRqj0fw+FCQL69FZxC1ILcUDxwMe7WPMN5+dobHoVihehqH8w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294730; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7ZMrAR860LVLLbEn3nTo+Jz2p6zIzurqX1lJh5uQLiY=; b=iq/oNZRuIr6x1ZODMwqLTgq9mGdvd5Q2qVx+L/rfj83T1TOym7mXlqzdaazfYhr/Fn7kLYIfyAMFggfqn30Ft7+3SqXao5T8VFKSGaLDx3DRrWsPQjs+4r7OG3lNsgU5TdtoD38Rc67LbJIYVNYUkTKi5FK38Toyr/3aNs3TupU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294730085403.0646157992161; Mon, 27 Apr 2026 05:58:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLU8-0006Sh-6f; Mon, 27 Apr 2026 08:54:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNq-00084k-9q for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:25 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNi-0005fU-Qk for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:13 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-488a88aeec9so127020295e9.2 for ; Mon, 27 Apr 2026 05:48:05 -0700 (PDT) Received: from lanath.. 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Replace it with a header file specific to that device. virt.c and vmapple.c included primecell.h despite not using the constants it defined; there we can simply drop the include entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260416172627.690396-1-peter.maydell@linaro.org --- MAINTAINERS | 2 +- hw/arm/realview.c | 2 +- hw/arm/vexpress.c | 2 +- hw/arm/virt.c | 1 - hw/misc/arm_sysctl.c | 2 +- hw/vmapple/vmapple.c | 1 - include/hw/arm/primecell.h | 12 ------------ include/hw/misc/arm_sysctl.h | 16 ++++++++++++++++ 8 files changed, 20 insertions(+), 18 deletions(-) delete mode 100644 include/hw/arm/primecell.h create mode 100644 include/hw/misc/arm_sysctl.h diff --git a/MAINTAINERS b/MAINTAINERS index 8d980d6c40..50a8e161c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -759,7 +759,6 @@ F: hw/ssi/pl022.c F: include/hw/ssi/pl022.h F: hw/rtc/pl031.c F: include/hw/rtc/pl031.h -F: include/hw/arm/primecell.h F: hw/timer/cmsdk-apb-timer.c F: include/hw/timer/cmsdk-apb-timer.h F: tests/qtest/cmsdk-apb-timer-test.c @@ -1113,6 +1112,7 @@ F: hw/*/versatile* F: hw/i2c/arm_sbcon_i2c.c F: include/hw/i2c/arm_sbcon_i2c.h F: hw/misc/arm_sysctl.c +F: include/hw/misc/arm_sysctl.h F: docs/system/arm/versatile.rst =20 Virt diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 7c49995c80..2b9f3271d6 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -12,9 +12,9 @@ #include "target/arm/cpu.h" #include "hw/core/sysbus.h" #include "hw/arm/boot.h" -#include "hw/arm/primecell.h" #include "hw/arm/machines-qom.h" #include "hw/core/split-irq.h" +#include "hw/misc/arm_sysctl.h" #include "hw/net/lan9118.h" #include "hw/net/smc91c111.h" #include "hw/pci/pci.h" diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index b178798085..f26d8c6f8d 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -26,8 +26,8 @@ #include "qemu/datadir.h" #include "hw/core/sysbus.h" #include "hw/arm/boot.h" -#include "hw/arm/primecell.h" #include "hw/arm/machines-qom.h" +#include "hw/misc/arm_sysctl.h" #include "hw/net/lan9118.h" #include "hw/i2c/i2c.h" #include "net/net.h" diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f62253e1ab..77891f0820 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -36,7 +36,6 @@ #include "monitor/qdev.h" #include "hw/core/sysbus.h" #include "hw/arm/boot.h" -#include "hw/arm/primecell.h" #include "hw/arm/virt.h" #include "hw/arm/machines-qom.h" #include "hw/block/flash.h" diff --git a/hw/misc/arm_sysctl.c b/hw/misc/arm_sysctl.c index 7b320f89c1..ebc95b9bb5 100644 --- a/hw/misc/arm_sysctl.c +++ b/hw/misc/arm_sysctl.c @@ -14,8 +14,8 @@ #include "system/runstate.h" #include "qemu/bitops.h" #include "hw/core/sysbus.h" +#include "hw/misc/arm_sysctl.h" #include "migration/vmstate.h" -#include "hw/arm/primecell.h" #include "qemu/log.h" #include "qemu/module.h" #include "qom/object.h" diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c index b1379eafef..607181f517 100644 --- a/hw/vmapple/vmapple.c +++ b/hw/vmapple/vmapple.c @@ -32,7 +32,6 @@ #include "hw/core/sysbus.h" #include "hw/usb/usb.h" #include "hw/arm/boot.h" -#include "hw/arm/primecell.h" #include "hw/char/pl011.h" #include "hw/intc/arm_gic.h" #include "hw/intc/arm_gicv3_common.h" diff --git a/include/hw/arm/primecell.h b/include/hw/arm/primecell.h deleted file mode 100644 index 7337c3b3ca..0000000000 --- a/include/hw/arm/primecell.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef PRIMECELL_H -#define PRIMECELL_H - -/* Declarations for ARM PrimeCell based periperals. */ -/* Also includes some devices that are currently only used by the - ARM boards. */ - -/* arm_sysctl GPIO lines */ -#define ARM_SYSCTL_GPIO_MMC_WPROT 0 -#define ARM_SYSCTL_GPIO_MMC_CARDIN 1 - -#endif diff --git a/include/hw/misc/arm_sysctl.h b/include/hw/misc/arm_sysctl.h new file mode 100644 index 0000000000..424069cd6e --- /dev/null +++ b/include/hw/misc/arm_sysctl.h @@ -0,0 +1,16 @@ +/* + * Status and system control registers for ARM RealView/Versatile boards. + * + * Copyright (c) Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_ARM_SYSCTL_H +#define HW_MISC_ARM_SYSCTL_H + +/* arm_sysctl inbound GPIO lines */ +#define ARM_SYSCTL_GPIO_MMC_WPROT 0 +#define ARM_SYSCTL_GPIO_MMC_CARDIN 1 + +#endif --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That in turn means that tests of cpu_isar_feature(aa64_something, cpu) will return true. Until now we have had a design policy that you shouldn't check an aa64_ feature unless you know that the CPU has AArch64; but this is quite fragile as it's easy to forget and only causes a problem in the corner case where AArch64 was turned off. In particular, when we extend the ability to disable AArch64 from only KVM to also TCG there are many more aa64 feature check points which we would otherwise have to audit for whether they needed to be guarded with a check on ARM_FEATURE_AARCH64. Instead, make the CPU realize function zero out all the 64-bit ID registers if a TCG CPU doesn't have AArch64; this will make aa64_ feature tests generally return false. We only do this for TCG because only TCG really needs it, and for KVM it might be confusing to have QEMU's idea of the ID registers be different from KVM's. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260416165353.589569-2-peter.maydell@linaro.org --- target/arm/cpu.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 3 ++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b62de8addf..6705ee9db7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1606,6 +1606,27 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) } } =20 +static void arm_clear_aarch64_idregs(ARMCPU *cpu) +{ + /* Zero out all the AArch64 ID registers in ARMISARegisters */ + SET_IDREG(&cpu->isar, ID_AA64ISAR0, 0); + SET_IDREG(&cpu->isar, ID_AA64ISAR1, 0); + SET_IDREG(&cpu->isar, ID_AA64ISAR2, 0); + SET_IDREG(&cpu->isar, ID_AA64PFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64PFR1, 0); + SET_IDREG(&cpu->isar, ID_AA64PFR2, 0); + SET_IDREG(&cpu->isar, ID_AA64MMFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64MMFR1, 0); + SET_IDREG(&cpu->isar, ID_AA64MMFR2, 0); + SET_IDREG(&cpu->isar, ID_AA64MMFR3, 0); + SET_IDREG(&cpu->isar, ID_AA64DFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64DFR1, 0); + SET_IDREG(&cpu->isar, ID_AA64AFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64AFR1, 0); + SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); +} + static void arm_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1733,6 +1754,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) } #endif =20 + /* + * A TCG aarch64=3Doff CPU has no AArch64 at all, so we clear out the + * ID registers to avoid cpu_isar_feature(aa64_something, cpu) tests + * incorrectly returning true. We don't do this for other accelerators + * (which in practice means "for KVM", since no others have AArch32 + * guest support) because from KVM's point of view the AArch64 ID + * registers still exist and must have their correct values. So we + * avoid clearing them out so that we don't have QEMU and KVM with + * different ideas of the ID registers. + */ + if (tcg_enabled() && !arm_feature(env, ARM_FEATURE_AARCH64)) { + arm_clear_aarch64_idregs(cpu); + } + #ifdef CONFIG_USER_ONLY /* * User mode relies on IC IVAU instructions to catch modification of diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 657ff4ab20..ab6bacf4aa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1080,7 +1080,8 @@ struct ArchCPU { * Note that if you add an ID register to the ARMISARegisters struct * you need to also update the 32-bit and 64-bit versions of the * kvm_arm_get_host_cpu_features() function to correctly populate the - * field by reading the value from the KVM vCPU. + * field by reading the value from the KVM vCPU. If it is an AArch64 + * ID register then you also must update arm_clear_aarch64_idregs(). */ struct ARMISARegisters { uint32_t mvfr0; --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294479; cv=none; d=zohomail.com; s=zohoarc; b=JY5yLgHgyJVbH/AZec/zbeyaEP3ccVYxg1MwJGPfxjCLXRL3q1OIigJwIVRTQXsrkgkua9Oh/D/7BpiDx1gZRQW6NBN3SY+fhzW3cpkC5hJA/6n5RYPhFBaRKSit8h1jDI0BF7SG0Nx7cZdbo+AOVMKDUcC6PXsr2ElXU5pWtsY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294479; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xZm/AVvBxSU6qXvUjvzkb0G4oWQvQlYJBh6wWu9idMI=; b=NRNDmIy9Jq3ZPRTgVVrAaKa+8AeILxm7XZAi+oq6zCCQVT8AJcBaMSoHeiPGQEU6UsceFmFvEi0KPAPOOB7vD9ptoyoJkeUxl/m8vQP+To/P8OVq4yOAO3MN6MRWa64tSUeQj6CYXWJvHY2NHe+Vf0eg2YScK0iewWcqHnt2M/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294479634668.5306811101125; Mon, 27 Apr 2026 05:54:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLQR-0002I4-PZ; Mon, 27 Apr 2026 08:51:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNq-00084l-9z for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:25 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNi-0005fk-Pc for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:12 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4891b0786beso72841525e9.1 for ; Mon, 27 Apr 2026 05:48:07 -0700 (PDT) Received: from lanath.. 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Note that we don't permit it on the qemu-aarch64 user-mode binary: this makes no sense as that executable can only handle AArch64 syscalls (and it would also assert at startup since it doesn't compile in the A32-specific GDB xml files like arm-neon.xml). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Cl=C3=A9ment Chigot Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260416165353.589569-3-peter.maydell@linaro.org --- docs/system/arm/cpu-features.rst | 10 +++++---- target/arm/cpu-features.h | 5 +++++ target/arm/cpu.c | 36 ++++++++++++++++++++++++++++---- tests/qtest/arm-cpu-features.c | 8 ++----- 4 files changed, 45 insertions(+), 14 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index ce19ae6a04..10b0eff27e 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -23,10 +23,12 @@ not implement ARMv8-A, will not have the ``aarch64`` CP= U property. QEMU's support may be limited for some CPU features, only partially supporting the feature or only supporting the feature under certain configurations. For example, the ``aarch64`` CPU feature, which, when -disabled, enables the optional AArch32 CPU feature, is only supported -when using the KVM accelerator and when running on a host CPU type that -supports the feature. While ``aarch64`` currently only works with KVM, -it could work with TCG. CPU features that are specific to KVM are +disabled, enables the optional AArch32 CPU feature, can only be set to +``off`` on the TCG and KVM accelerators, and it cannot be set to +``off`` under KVM unless running on a host CPU type that supports +running guests in AArch32. + +CPU features that are inherently specific to KVM are prefixed with "kvm-" and are described in "KVM VCPU Features". =20 CPU Feature Probing diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index b683c9551a..6e5212ff6c 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1071,6 +1071,11 @@ static inline bool isar_feature_aa64_aa32_el2(const = ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >=3D 2; } =20 +static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >=3D 2; +} + static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6705ee9db7..9b80dda140 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1244,10 +1244,38 @@ static void aarch64_cpu_set_aarch64(Object *obj, bo= ol value, Error **errp) * uniform execution state like do_interrupt. */ if (value =3D=3D false) { - if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { - error_setg(errp, "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported"); + if (kvm_enabled()) { + if (!kvm_arm_aarch32_supported()) { + error_setg(errp, "'aarch64' feature cannot be disabled for= KVM " + "because this host does not support 32-bit EL1"= ); + return; + } + } else if (tcg_enabled()) { +#ifdef CONFIG_USER_ONLY + error_setg(errp, "'aarch64' feature cannot be disabled for " + "usermode emulator qemu-aarch64; use qemu-arm inste= ad"); + return; +#else + bool aa32_at_highest_el; + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { + aa32_at_highest_el =3D cpu_isar_feature(aa64_aa32_el3, cpu= ); + } else if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { + aa32_at_highest_el =3D cpu_isar_feature(aa64_aa32_el2, cpu= ); + } else { + aa32_at_highest_el =3D cpu_isar_feature(aa64_aa32_el1, cpu= ); + } + + if (!aa32_at_highest_el) { + error_setg(errp, "'aarch64' feature cannot be disabled for= " + "this TCG CPU because it does not support 32-bi= t " + "execution at its highest implemented exception= " + "level"); + return; + } +#endif + } else { + error_setg(errp, "'aarch64' feature cannot be disabled for " + "this accelerator"); return; } unset_feature(&cpu->env, ARM_FEATURE_AARCH64); diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index bbdd89a81d..cb4d01fd46 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -493,12 +493,8 @@ static void test_query_cpu_model_expansion(const void = *data) sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); =20 - /* Test that features that depend on KVM generate errors without. = */ - assert_error(qts, "max", - "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported", - "{ 'aarch64': false }"); + /* TCG allows us to turn off AArch64 on the 'max' CPU type */ + assert_set_feature(qts, "max", "aarch64", false); } =20 qtest_quit(qts); --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294660; cv=none; d=zohomail.com; s=zohoarc; b=nFL8sTZSg7jmcNQyHX909A3dqOF/01hkCd36vkwKS3WZe4C68I1uKpI6M59ErNOm2m0kCG8GgLIDk4FwQ5bGsiqmfiVYFC809VcBhGsRn/J3BdWLCLMdPWdk89O1QVXE8I0X7/usX4mhvChUh2hmAOuaK2DpqMe6rXE53Ra/9wU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294660; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260416165353.589569-4-peter.maydell@linaro.org --- tests/functional/aarch64/meson.build | 1 + .../aarch64/test_virt_aarch64_off.py | 37 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100755 tests/functional/aarch64/test_virt_aarch64_off.py diff --git a/tests/functional/aarch64/meson.build b/tests/functional/aarch6= 4/meson.build index 1067f181f2..9803f66299 100644 --- a/tests/functional/aarch64/meson.build +++ b/tests/functional/aarch64/meson.build @@ -47,6 +47,7 @@ tests_aarch64_system_thorough =3D [ 'tcg_plugins', 'tuxrun', 'virt', + 'virt_aarch64_off', 'virt_gpu', 'virt_vbsa', 'xen', diff --git a/tests/functional/aarch64/test_virt_aarch64_off.py b/tests/func= tional/aarch64/test_virt_aarch64_off.py new file mode 100755 index 0000000000..13d8b73b0d --- /dev/null +++ b/tests/functional/aarch64/test_virt_aarch64_off.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# +# Functional test that boots an AArch32 Linux kernel and checks the console +# on a TCG aarch64 CPU with aarch64=3Doff. This is the same image etc +# as we use in tests/functional/arm/test_virt.py. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest, Asset + +class ArmVirtMachine(LinuxKernelTest): + + ASSET_KERNEL =3D Asset( + ('https://archives.fedoraproject.org/pub/archive/fedora/linux/' + 'releases/29/Everything/armhfp/os/images/pxeboot/vmlinuz'), + '18dd5f1a9a28bd539f9d047f7c0677211bae528e8712b40ca5a229a4ad8e2591') + + def test_arm_virt(self): + self.set_machine('virt') + # KVM aarch64=3Doff requires a host CPU that supports it, so + # restrict the test to TCG only + self.require_accelerator('tcg') + self.vm.add_args('-cpu', 'max,aarch64=3Doff') + + kernel_path =3D self.ASSET_KERNEL.fetch() + + self.vm.set_console() + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + + 'console=3DttyAMA0') + self.vm.add_args('-kernel', kernel_path, + '-append', kernel_command_line) + self.vm.launch() + console_pattern =3D 'Kernel command line: %s' % kernel_command_line + self.wait_for_console_pattern(console_pattern) + +if __name__ =3D=3D '__main__': + LinuxKernelTest.main() --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294656; cv=none; d=zohomail.com; s=zohoarc; b=SO1r6O5S4qegCrhkqIhMxubKrgvIYgKBGNJqIAAx8fDF/fHdXf2aMgOXU7lVt1YcymjukAK9IMmAThQbKiWKYe2U8qadFp8kPa80SQVhzJbJLCq97nKwVsysp9SSX/MZYey0+89fxcrCLf677YoBY9yQHXVH+cKXzrCzTvmW+W8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294656; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+Royy9UKz2653bp7UiRhq7eGlbKNi2zJHhkuwnIFZio=; b=GRb7hh8EVdtLTQ7xviUFwVs1teSzN3iUsFPT7D+tOlIjgWlOtxxOoOvWajxeCLpUrDdplPi2oDhts71DV+WhzPWNPYl3GZM27JowPiSzw0Y4G30GkmQq9UfCBgtb8cIOxHbQJcwkPTb4tUL5XJDC9bgYc4QP2ikzdPSQtw3Dwcc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294656852425.5340104417986; Mon, 27 Apr 2026 05:57:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLQy-0002hg-Sr; Mon, 27 Apr 2026 08:51:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNq-00084j-9w for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:25 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNi-0005fy-Q3 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:13 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-488e1a8ac40so126645365e9.2 for ; Mon, 27 Apr 2026 05:48:09 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294088; x=1777898888; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+Royy9UKz2653bp7UiRhq7eGlbKNi2zJHhkuwnIFZio=; b=AQFuz+SmNbEWEFw45qaXp6YPmleUO+5sdYskAeU0peOSr7qOEonEW5TPGqCYXLqtGe sxyLz9WsOJB7eLM6WcjpI60D8q7Jyo2qqn/7DfKK8MYaNaLASUJVV4OnMzknmC9TLBh5 Mryz3XQI1Ot1kqjkbE/oZ/Wp3/qjiPT21ZyxaXt2cHghbKGQIX5uHnMW6B0MU2aYpvEa /0ZbOnyzXi6XVabY28VwfgjKVaa0ibThkP5F5rUKtgSkEKrNNmhAWHJbUQz1UhLphQLC Umunxmes0r9i6ewr85QAoxjWsd3tCYURAGKOJ2BzRhCqcFperIgrHfFR4DFAd3bFmAoP GE0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294088; x=1777898888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+Royy9UKz2653bp7UiRhq7eGlbKNi2zJHhkuwnIFZio=; b=GVnARqA6z1WHtTFG0bBk3JKo5zvZjyu2G/9PtdoBTxoY5EDlkuUO0cvVRAYmleVhQO 3wVCh6WgK+5SSW10Q3vMI/oiWwTiB9KcqbQzxB9xovlMDPWx/awAMvv00LRODFycDQv4 YCYxmv3b1cKxmUPOgrwsmvKrmvm8PyetHBT4WYvkqMIjy31ZQy1cmavokQgQkEWrH0CP mnpZPpS9ty+smiBfnsXZtzj19kJu3QAjQ/DFfKqvN/jmpaUmgeun3zt3aZaER/burgoq 6EPKVE1FbVyc0gOQrOboSB68IHhcUw/QLhkFWYDmqITYd55f2XFh3a4toc4ZBL7TwkVo 7+7A== X-Gm-Message-State: AOJu0Yx734w8H+67bYYkYEaUtyNVqwvdshV6Gdwwdv4W3EbKCfCBYO7H pUQNhElJDj/uAIzYRM5DF+M4wUkzgnmHSNItK7TGWsRAL/l0MJeWF+GMsr0e2eUQvKfyuZlfosD ObE8G X-Gm-Gg: AeBDiesIeOfDn6dNyttBGTKvvHcs8gurMS8viljiZm9rgoQC4L+16PqIpETkj3Mt9LJ OX4XC48QD14s7v/5sVd9wwww1WtYzBWOZmG2EC7yYJE5X/e+EDENsUtoe20PEZEIrC7JoPxd5F4 A077LdG7FQCD6nMCFSaZjzil8xCh9LLW7RyTUL86ArLa2Mx5AlexQ4MT0clWWwQx1iNVsPtmgGa Z4TjiyU1/+Qo68LoJtUmekMjc0dSDZOsfU1sVrIaDKr96DC9UyFD72/xhUYoJPY7zeTgnkSVWeo J9V+DX7TJGB+p1DTe+cfTxp6uxel+IONsxRUUsazwXj3lwwCMC8EhKbSE5sxh+hQ/ltqONyuhkz LRZcAEX7niwqZgMxgiTBVMr6eJDUyz6Fb2r0mHE9NkLwlJCQx7NasElhj0Jy2a5rj4200Uuz1W4 vjCVXRzxqwmt3atnZPaNSVvLwc2Y6Lezz5FFU1F4j/rSikJbNO4yJbjS55DtRBnR7CxZPLyN3ZZ GLnS6NeNwSIZ0X/Y82N8Q5e4RHo95G+Znvc82uK+8DAiHEffoTz X-Received: by 2002:a05:600c:899:b0:489:1a63:509c with SMTP id 5b1f17b1804b1-4891a635125mr302497985e9.0.1777294088318; Mon, 27 Apr 2026 05:48:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/63] target/arm/cpu: Introduce the infrastructure for cpreg migration tolerances Date: Mon, 27 Apr 2026 13:47:05 +0100 Message-ID: <20260427124738.966578-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294658933154100 Content-Type: text/plain; charset="utf-8" From: Eric Auger We introduce a datatype for a tolerance with respect to a given cpreg migration issue. The tolerance applies to a given cpreg kvm index, and can be of different types: a) mismatch in cpreg indexes - ToleranceNotOnBothEnds (cpreg index is allowed to be only present on one end) - ToleranceOnlySrcTestValue (cpreg index is allowed to be only present in source if its value @mask field matches @value) b) mismatch in cpreg values - ToleranceDiffInMask (value differences are allowed only within a mask) - ToleranceFieldLT (incoming field value must be less than a given value) - ToleranceFieldGT (incoming field value must be greater than a given value) A QLIST of such tolerances can be populated using a new helper: arm_register_cpreg_mig_tolerance() and arm_cpu_match_cpreg_mig_tolerance() allows to check whether a tolerance exists for a given kvm index and its criterion is matched. callers for those helpers will be introduced in subsequent patches. Only registration of migration tolerances related to cpreg index mismatch is currently allowed. Signed-off-by: Eric Auger Message-id: 20260420140552.104369-2-eric.auger@redhat.com Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- target/arm/cpu.c | 82 ++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 1 + target/arm/internals.h | 54 ++++++++++++++++++++++++++++ 3 files changed, 137 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b80dda140..10feb639c4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -181,6 +181,82 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELCha= ngeHookFn *hook, QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); } =20 +static ARMCPRegMigTolerance *find_mig_tolerance(ARMCPU *cpu, uint64_t kvmi= dx) +{ + ARMCPRegMigTolerance *t; + QLIST_FOREACH(t, &cpu->cpreg_mig_tolerances, node) { + if (t->kvmidx =3D=3D kvmidx) { + return t; + } + } + return NULL; +} + +void arm_register_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, + uint64_t mask, uint64_t value, + ARMCPRegMigToleranceType type) +{ + ARMCPRegMigTolerance *entry; + + /* make sure the kvmidx has not tolerance already registered */ + assert(!find_mig_tolerance(cpu, kvmidx)); + + assert(type =3D=3D ToleranceNotOnBothEnds || + type =3D=3D ToleranceOnlySrcTestValue); + + entry =3D g_new0(ARMCPRegMigTolerance, 1); + + entry->kvmidx =3D kvmidx; + entry->mask =3D mask; + entry->value =3D value; + entry->type =3D type; + + QLIST_INSERT_HEAD(&cpu->cpreg_mig_tolerances, entry, node); +} + +bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, + uint64_t vmstate_value, uint64_t lo= cal_value, + ARMCPRegMigToleranceType type) +{ + ARMCPRegMigTolerance *t =3D find_mig_tolerance(cpu, kvmidx); + uint64_t diff, diff_outside_mask, field; + + if (!t || t->type !=3D type) { + return false; + } + + if (type =3D=3D ToleranceNotOnBothEnds) { + return true; + } + + if (type =3D=3D ToleranceOnlySrcTestValue && + ((vmstate_value & t->mask) =3D=3D t->value)) { + return true; + } + + /* Need to check the mask */ + diff =3D vmstate_value ^ local_value; + diff_outside_mask =3D diff & ~t->mask; + + if (diff_outside_mask) { + /* there are differences outside of the mask */ + return false; + } + if (type =3D=3D ToleranceDiffInMask) { + /* differences only in the field, tolerance matched */ + return true; + } + /* need to compare field value against authorized ones */ + field =3D vmstate_value & t->mask; + if (type =3D=3D ToleranceFieldLT && (field < t->value)) { + return true; + } + if (type =3D=3D ToleranceFieldGT && (field > t->value)) { + return true; + } + return false; +} + static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) { /* Reset a single ARMCPRegInfo register */ @@ -1102,6 +1178,7 @@ static void arm_cpu_initfn(Object *obj) =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); + QLIST_INIT(&cpu->cpreg_mig_tolerances); =20 #ifdef CONFIG_USER_ONLY # ifdef TARGET_AARCH64 @@ -1574,6 +1651,7 @@ static void arm_cpu_finalizefn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMELChangeHook *hook, *next; + ARMCPRegMigTolerance *t, *n; =20 g_hash_table_destroy(cpu->cp_regs); =20 @@ -1585,6 +1663,10 @@ static void arm_cpu_finalizefn(Object *obj) QLIST_REMOVE(hook, node); g_free(hook); } + QLIST_FOREACH_SAFE(t, &cpu->cpreg_mig_tolerances, node, n) { + QLIST_REMOVE(t, node); + g_free(t); + } #ifndef CONFIG_USER_ONLY if (cpu->pmu_timer) { timer_free(cpu->pmu_timer); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ab6bacf4aa..be14a47c35 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1140,6 +1140,7 @@ struct ArchCPU { =20 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks; + QLIST_HEAD(, ARMCPRegMigTolerance) cpreg_mig_tolerances; =20 int32_t node_id; /* NUMA node this CPU belongs to */ =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 06655409e5..a632584a4e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1943,4 +1943,58 @@ int compare_u64(const void *a, const void *b); /* Used in FEAT_MEC to set the MECIDWidthm1 field in the MECIDR_EL2 regist= er. */ #define MECID_WIDTH 16 =20 +typedef enum { + ToleranceNotOnBothEnds, + ToleranceOnlySrcTestValue, + ToleranceDiffInMask, + ToleranceFieldLT, + ToleranceFieldGT, +} ARMCPRegMigToleranceType; + +typedef struct ARMCPRegMigTolerance { + uint64_t kvmidx; + uint64_t mask; + uint64_t value; + ARMCPRegMigToleranceType type; + QLIST_ENTRY(ARMCPRegMigTolerance) node; +} ARMCPRegMigTolerance; + +/** + * arm_register_cpreg_mig_tolerance: + * Register a migration tolerance wrt one given cpreg identified by its + * @kvmidx. Calling this function twice for the same @kvmidx is a + * programming error and will cause an assertion failure. + * + * @cpu: vcpu to apply the migration tolerance on + * @kvmidx: kvm index of the cpreg the tolerance applies to + * @mask: bitmask where a difference is tolerated + * (relevant with ToleranceDiffInMask) + * @value: value the bitmask field is compared with + * (relevant with ToleranceFieldLT and ToleranceFieldGT) + * @type: type of the migration tolerance: + * - ToleranceNotOnBothEnds (cpreg index is allowed to be only present + * on one end) + * - ToleranceOnlySrcTestValue (cpreg index is allowed to be only + * present in source if its value @mask field matches @value) + * - ToleranceDiffInMask (mismatch in cpreg values are only tolerated + * if differences are within @mask) + * - ToleranceFieldLT (mismatch in cpreg values are only tolerated + * if incoming @bitmask field value is less than @value) + * - ToleranceFieldGT (mismatch in cpreg values are only tolerated + * if incoming @bitmask field value is greater than @value) + */ +void arm_register_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, + uint64_t mask, uint64_t value, + ARMCPRegMigToleranceType type); + +/** + * arm_cpu_match_cpreg_mig_tolerance: + * Check whether a tolerance of type @type exists for a given @kvmidx + * and the tolerance criterion is satisfied + */ +bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, + uint64_t vmstate_value, uint64_t lo= cal_value, + ARMCPRegMigToleranceType type); + + #endif --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294531; cv=none; d=zohomail.com; s=zohoarc; b=G5BKW1zYklVXDIaxLB1skT4vDkVBsF7N2xZViZH/dVcndAfuYX3FYhDSpYGn/xTWfcKrszuQ6QO2PzKKlRf+mtepg8zcanxLCpIHz4q6dDsH42+4L+YjgzQcv8Aky0HpU7pJH+xydoEYOE4o5Fu9UfN0H1SCWEihtxqgT7Ueax4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294531; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=YY1tm1vPSzbBUTbdxWQFuXKrfsrK/NMFeG62EkzTKa8=; b=Ni0DZlvaOd0CXG5HpiBFhZ4sgcIacZNkZjHWl6L8G+gskKuAn4WGWz6/gSBqjQetL9CHEPc4rvLCawn1r81UVNKXI638Nq5VAWVXJbPFU8Gy14mR+9LFjLWa0VclwIJhFjgN6Kb6EkS5AFu7Qi6nmJXwdZ+Yk14LnM7DRBMOox0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177729453154938.64634595244024; Mon, 27 Apr 2026 05:55:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUH-0006nB-EF; Mon, 27 Apr 2026 08:54:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNq-00086E-O0 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:26 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNj-0005g4-43 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:14 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-488a9033b2cso109080205e9.2 for ; Mon, 27 Apr 2026 05:48:10 -0700 (PDT) Received: from lanath.. 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If any, silence warning/errors. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20260420140552.104369-3-eric.auger@redhat.com Signed-off-by: Peter Maydell --- target/arm/machine.c | 21 +++++++++++++++------ target/arm/trace-events | 2 ++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 50d80ffb68..b2bf129334 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -1063,25 +1063,34 @@ static void handle_cpreg_missing_in_incoming_stream= (ARMCPU *cpu, uint64_t kvmidx { g_autofree gchar *name =3D print_register_name(kvmidx); =20 + if (arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, + 0, 0, ToleranceNotOnBothEnds)) { + trace_tolerate_cpreg_missing_in_incoming_stream(name); + return; + } warn_report("%s: %s " "expected by the destination but not in the incoming strea= m: " "skip it", __func__, name); } =20 /* - * Handle the situation where @kvmidx is in the incoming stream - * but not on destination. This currently fails the migration but - * we plan to accomodate some exceptions, hence the boolean returned value. + * Handle the situation where @kvmidx is in the incoming + * stream but not on destination. This fails the migration if + * no cpreg mig tolerance is matched for this @kvmidx + * Return true if the migration should eventually fail */ static bool handle_cpreg_only_in_incoming_stream(ARMCPU *cpu, uint64_t kvm= idx) { g_autofree gchar *name =3D print_register_name(kvmidx); - bool fail =3D true; =20 + if (arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, + 0, 0, ToleranceNotOnBothEnds)) { + trace_tolerate_cpreg_only_in_incoming_stream(name); + return false; + } error_report("%s: %s in the incoming stream but unknown on the " "destination: fail migration", __func__, name); - - return fail; + return true; } =20 static int cpu_post_load(void *opaque, int version_id) diff --git a/target/arm/trace-events b/target/arm/trace-events index 2de0406f78..8502fb3265 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -29,3 +29,5 @@ arm_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint= 64_t x3, uint32_t cpuid =20 # machine.c cpu_post_load(uint32_t cpreg_vmstate_array_len, uint32_t cpreg_array_len) = "cpreg_vmstate_array_len=3D%d cpreg_array_len=3D%d" +tolerate_cpreg_missing_in_incoming_stream(char *name) "%s is missing in in= coming stream but this is explicitly tolerated" +tolerate_cpreg_only_in_incoming_stream(char *name) "%s is in incoming stre= am but not on destination but this is explicitly tolerated" --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294248; cv=none; d=zohomail.com; s=zohoarc; b=OXDp+V6n3E4ZTufvCXpYbrYvgJe47EEVdREsUVHLXzOxeaWywLJmXYe8ZeYqSoUgGyFP/Ag/xHGj/gx90e1xDLkuAirF6nSMAwUW+MWJL/01i2AO87cFzW6aCvYSausUeXch0P97ktQHM5RBk39Xg0l7IcCuu4DbMk+sqXmnX8Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294248; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3Ad8L4DaKuABGGpSrYonhMaeLrwN0x/B0x2CwuHI6n8=; b=AXUkjEny50NCc6lg1+9X26ym6RCjxt1qrrrwZEEtjPvZCRNJvGIn2NfrTSW3+pLd7X0rSfMez03sbmi1/9melN/2nK+SBOhg/n+zwm2sy5g7H9sVKOupP3i63pEslPnbUWTSxEcxVxLsArR9wXoyvh4oRYvZPF6SpQ2BcOHyyeI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294248495631.4751823886359; Mon, 27 Apr 2026 05:50:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLOM-0008RI-AO; Mon, 27 Apr 2026 08:48:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNq-00086D-NN for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:26 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNk-0005g9-Gv for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:15 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-483487335c2so99993805e9.2 for ; Mon, 27 Apr 2026 05:48:11 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294090; x=1777898890; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3Ad8L4DaKuABGGpSrYonhMaeLrwN0x/B0x2CwuHI6n8=; b=ZKGycC0+UiKiT5WGZ5nOcnZ2kxt0h0zV6eppkYmi5VFRCKy/iOxoLMKkLM64vxY8mW cC6ryXRs+rca3CJEUUkALSzLFM8jQC/ac64G8yvxfTaD8Bwxsosj5S+55Hyc+r1WNxVH qQODasctDGPEDv0owWIjarGtj70iVmGMczH/qQsSaxhTbyx8bNRWntG5sGMbG70WjUec 50d2Ks5j6QQV3jHniu+tHkuw4HEW8yur4bvB3rjXReybizPweTOGgPTDON4vOYuPaDra T3N+PIs7gOUdK9Z6fBWoo9F6UpFE5gzpEBaY0IGcUnN2NnOuAJ95MODUivDALb0Ji2iM Tfyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294090; x=1777898890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=3Ad8L4DaKuABGGpSrYonhMaeLrwN0x/B0x2CwuHI6n8=; b=ceaZhvBJQi/oDJeCs7rHGyT6d0NKxpgymCXn5Wo+47RUUIzgP00BK6S60JEs5QQ4oz PAgobc7yc5R/JiemjfgH0+c1RZ6eVCr31EP31rMmK3F46Do9eNRSinBldL4e0arFtq2/ AOHJMWWa3xtVXkIv2wi3K4uwqBx0u0pB2Zj0Yabj5UMKJHOzQvUJJO/p4miVvLBXmgb5 LTnXmWPC9DnXcCtgBGKTor7cg31+a79uftE7qBmt5hdoBuvMrcecdE82X7lhnQVQ9U+U P9tQXQGYWuoLGA2PMQ17GGI4vmLqd7T49+c3RQeuxdO2dtO+9BgU5WiGwlyztfKmU0i/ FmaQ== X-Gm-Message-State: AOJu0YxOUf/PqYWsN0f2OnuK8Hk6vIUCkhrv5QqSmx1EB9L/Vue2cYc3 7BRoSiBIZQ5Of1FXBSFhzSxOri0DasW+KbKUtw9MUT7itgRbB9o0nv/6Q1I0ABFSG/zG/kUs3LK lrgmy X-Gm-Gg: AeBDietTs39YykfPSyeJke4Ug0MGkdRDEjWBo4n+zs+EJfKKkv+6AckPWaS1vGNFLWI MjpWKWYlYDSG3fRkQksRecpSOfvzAa0lfB7bUVoP8bD9Ax+PYFnyvrfPWmxusanUpAukSJzvUNB LVRUTvq5kem7sDCkfWeCZ/Pmo9ZgejMUCdc881sCQFvIC8EB8V3wvhOnmI/7wnvwgx2CsCR1bUi ux4AXGCzGG9lnyJP/WLCgVdZWV3gI9FTr6VJrpLSKT/NDK4ftxpG2nVFKHveVh6mexG38WKtUcD QK43usLbn+vd0jDjMXM6dfK9Rqv8mi1qlwhnpGtSYps/bMZGCW8OYjIBpmKT5KbbkARsz6pNs2T E5FrPB07bQCwpDTvPmf3RYFFmqm1qqMkLb30In1oVaYJxWktxARMsPQOMdaPTpvboGXPlgQkWx3 eRk9reMdH00cfrUeJ1F2zoXuz+ykKOWAA40CIU+SLw9FNUncizEuXTcSVjV2mXeZtAChjGVO/8m PUTlTPg5uG/RzSq7EoBrpDii0oWaPWfMmu25kyh4Q== X-Received: by 2002:a05:600c:2e56:b0:488:d243:8da9 with SMTP id 5b1f17b1804b1-488fb73b2d3mr370322475e9.1.1777294090074; Mon, 27 Apr 2026 05:48:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/63] target/arm/machine: Handle ToleranceOnlySrcTestValue migration tolerance Date: Mon, 27 Apr 2026 13:47:07 +0100 Message-ID: <20260427124738.966578-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294249324158500 Content-Type: text/plain; charset="utf-8" From: Eric Auger Pass the value of the incoming register to handle_cpreg_only_in_incoming_stream and check whether there is a matching ToleranceOnlySrcTestValue tolerance. Signed-off-by: Eric Auger Message-id: 20260420140552.104369-4-eric.auger@redhat.com Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- target/arm/machine.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index b2bf129334..8dc766d322 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -1079,12 +1079,15 @@ static void handle_cpreg_missing_in_incoming_stream= (ARMCPU *cpu, uint64_t kvmidx * no cpreg mig tolerance is matched for this @kvmidx * Return true if the migration should eventually fail */ -static bool handle_cpreg_only_in_incoming_stream(ARMCPU *cpu, uint64_t kvm= idx) +static bool +handle_cpreg_only_in_incoming_stream(ARMCPU *cpu, uint64_t kvmidx, uint64_= t value) { g_autofree gchar *name =3D print_register_name(kvmidx); =20 if (arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, - 0, 0, ToleranceNotOnBothEnds)) { + 0, 0, ToleranceNotOnBothEnds) || + arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, + value, 0, ToleranceOnlySrcTestVa= lue)) { trace_tolerate_cpreg_only_in_incoming_stream(name); return false; } @@ -1137,7 +1140,9 @@ static int cpu_post_load(void *opaque, int version_id) } if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { fail =3D handle_cpreg_only_in_incoming_stream(cpu, - cpu->cpreg_vmstate= _indexes[v++]); + cpu->cpreg_vmstate= _indexes[v], + cpu->cpreg_vmstate= _values[v]); + v++; continue; } /* matching register, copy the value over */ @@ -1160,7 +1165,8 @@ static int cpu_post_load(void *opaque, int version_id) */ for ( ; v < cpu->cpreg_vmstate_array_len; v++) { fail =3D handle_cpreg_only_in_incoming_stream(cpu, - cpu->cpreg_vmstate_ind= exes[v]); + cpu->cpreg_vmstate_ind= exes[v], + cpu->cpreg_vmstate_val= ues[v]); } if (fail) { return -1; --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294574; cv=none; d=zohomail.com; s=zohoarc; b=IiM2gkHnH3zfclRfCjxbpWKcp9+zAs/dcyOWlvnvRxpjSBUepMTgI4YlUc6ju8b8HKwwYEOLcPRdvDRAjWMPSVpvX4peMjRAVDlRZEJwP5fMWiGIxtHKGrr4g0uEB65SfGonlGlaXfBRU5xvwZIlOuZSeAgY2kBYLPpzhS7B+AE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294574; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=0v/Sp1N38U1xnn6NTkNVlcM8HldzbtGaI2x8xgpzJPE=; b=GUDSF+ALcmUopPpvtDOTRz7R2zplcw1VD+/8gR6R4jtLt2NPr/UulhBL124bU08MzhrKwIRquwKqtCyibwOuZmJrkS3xq6P223IB0dJ0z/OkAhY8EARFm3wfx7XvOu7ED8s/BDfzJEomD5g7r8VLGS/eMfVbp76rveKs0l+6Ptc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294574074605.4467971501489; Mon, 27 Apr 2026 05:56:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLPv-00019e-Uw; Mon, 27 Apr 2026 08:50:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNw-00087E-QS for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:31 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNp-0005ga-24 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:19 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-488a9033b2cso109080595e9.2 for ; Mon, 27 Apr 2026 05:48:12 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294091; x=1777898891; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0v/Sp1N38U1xnn6NTkNVlcM8HldzbtGaI2x8xgpzJPE=; b=q58AQbzBUCJff8HgLzSujIxRSMNwLrnxauYuYbeY1R9Uj/dKz1wgnvj3Bjd9cuDO8X OtG8Gtfmdd1IvyvG9DvOd/Bp+INziMtcZJZuR4dgZvzgg8/wuhggDz6wayq65qcRSmis lnV8O76/F1UG5KxYTzKj8gMgz0GJsuqOTAP4tTxC+2jM8ndt1kNMznmE79HOcow98fLz KkOkmMJb25RIv2RDcK+9cK+4fPU2Yw5fDomeeLe5MmLz3V+NR/64OPre0SlHNrJfYcUZ 8oboE/GqQgo7Sb0GRKVx0PgtOQ0kZbTyOE5ctsQy/+8CIE6jHbZFtdsspsMLKcUYOD4Z 168g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294091; x=1777898891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=0v/Sp1N38U1xnn6NTkNVlcM8HldzbtGaI2x8xgpzJPE=; b=nOTHl9RIkPQVFQRk2x1mtVeDRgXUM7G+zSnKtbE5X+ToNteZx+I/10fGS0NNcGfHu2 fMbzJF29MHn9wkRAsToBZOnTREE0LtUzGFDNQi2g5ME4UHPZ7+RMZ7Vm9qFPm1o7jmI6 ECGA2OgJ3BMncBCrXrrihl7id0qRQbCaNo45iB6X5GW52YM8Ec/XrjA6gK9eGGA5ijck G7iJbQfwlnDkUIK8UZ4WnjSAsNnaD1VrHlLeCtAmZXln1mXH7nrTq1cWLPPkqPn5cOdh 7Nd6BgRCMftpgPPIrAtpKOlhR+JZO7TgAkIDzBAxgewHEueDBac/RdawkMn0Z0ifLsFk DY/Q== X-Gm-Message-State: AOJu0YzwtUJFInI6Md0poZEZ9Nk3UB2kdF3uzGEtOy0zzijTlK5crT1t h6FqSz0+syEIgV9duRE6lydNDUHa6rkTnnt1fpY9kHjL0fmOMsiQCW2BLrhOn7KrcNQrQLhhszz OqZ4N X-Gm-Gg: AeBDieufoDs+Gcikl9jQBMR3a5yoNzTHxOAx4vf1hx/J/+jUQufGOADEdV9MJSMt8bC R8lL781NGPJ2Kwvl0it64tm3reI9fCG9e0sWbOXy4/Gz+ErhjoNXKszDNggl0aidlyQrh8uRtVI WQ6L4trrPvAj7pQYjeoIxLKXL3fOSVDD6ThGVCjQhus0a+GDVqdezjclBub+GQSBM+EaWYedyAz fAlUiTRkkI4URxqeoiqSFES5OAXDIlPoYgxTrpPe7o51dtABcJLefU2LIpthGJJvRgl45nqRsnP KuvnHmqrwemgHzGFr8X+quDxwRpoSe53TFEZ/iSlENPSfUdQMni10qWttg3cEORkNH3aiwwIl24 stxN5du/+AzZzbW4bG6Gp2LBbF5zrSuJZn2sw0HAe/ZzFZjvBGnZC8GnIn3wotr2KT5MrD+RFVB eAZkIaXVPBivT+uxFBY+QKK9LpUr/GznKItUJGZJesDBJEsv1iDMKC4w5Oo4IPv1E9x/u7Jrqk/ lci7cyKpXqmWWnpRO7yt5TJzzT6xTpvyhplQz6wKg== X-Received: by 2002:a05:600c:4f49:b0:489:1ff1:74df with SMTP id 5b1f17b1804b1-4891ff176bamr504250925e9.1.1777294091145; Mon, 27 Apr 2026 05:48:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/63] target/arm/cpu64: Mitigate migration failures due to spurious TCR_EL1, PIRE0_EL1 and PIR_EL1 Date: Mon, 27 Apr 2026 13:47:08 +0100 Message-ID: <20260427124738.966578-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294575586154100 From: Eric Auger Before linux v6.13 those registers were erroneously unconditionally exposed and this was fixed by commits: - 0fcb4eea5345 ("KVM: arm64: Hide TCR2_EL1 from userspace when disabled for guests") - a68cddbe47ef=C2=A0("KVM: arm64: Hide S1PIE registers from userspace when disabled for guests") in v6.13. This means if we migrate from an old kernel host to a >=3D 6.13 kernel host, migration currently fails. Declare cpreg migration tolerance for those registers. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott Reviewed-by: Peter Maydell Message-id: 20260420140552.104369-5-eric.auger@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d6feba220e..e7014022df 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -810,6 +810,33 @@ static void aarch64_a53_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 +#if defined(CONFIG_KVM) +static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu) +{ + /* + * Registers that may be in the incoming stream and not exposed + * on the destination + */ + + /* + * TCR_EL1 was erroneously unconditionnally exposed before linux v6.13. + * See commit 0fcb4eea5345 ("KVM: arm64: Hide TCR2_EL1 from userspace + * when disabled for guests") + */ + arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 2, 0, 3), + 0, 0, ToleranceNotOnBothEnds); + /* + * PIRE0_EL1 and PIR_EL1 were erroneously unconditionnally exposed + * before linux v6.13. See commit a68cddbe47ef=C2=A0("KVM: arm64: Hide + * S1PIE registers from userspace when disabled for guests") + */ + arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 2), + 0, 0, ToleranceNotOnBothEnds); + arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 3), + 0, 0, ToleranceNotOnBothEnds); +} +#endif + static void aarch64_host_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -822,6 +849,7 @@ static void aarch64_host_initfn(Object *obj) #endif =20 #if defined(CONFIG_KVM) + kvm_arm_set_cpreg_mig_tolerances(cpu); kvm_arm_set_cpu_features_from_host(cpu); aarch64_add_sve_properties(obj); #elif defined(CONFIG_HVF) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294645; cv=none; d=zohomail.com; s=zohoarc; b=GkViYDMWxDk409F2PLBYbBLGu5PRgO8kuAAnyXlNO87M2e5/Onp/vdMzVkhi1NHLQbafrkvybaM0zjnW7iQwdKQtB0K6sCg8CAah00+jDI+V5GQV6pqBiE+WUVyUk4iNCV/l1OIrOKBSJZ0vUjbtBB+IgAjXE2Hov7Vxeyr5Nj0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294645; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=U6+LMwBwSx9z5uRa0bJxch1nnS9wZaiUEFSDL/4DmaI=; b=kOAYFe9QU5hWkFL6GCYYp0pURLjDq80s1vgcuxSDrkU6Skl8me1v5FMfalAkJ0L63oEBPh9utW+H4u4iRTsfUO3KVkMlWg4ynbVi9Q7snYtRFq7jhouOtK9vkurP29k9Izmv2Sqkhtz3ZpyXdUExA1vKAcHPEWhyiWSzoAgYraw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294645847772.7320830724117; Mon, 27 Apr 2026 05:57:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLOt-0000Vg-7s; Mon, 27 Apr 2026 08:49:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNr-00086X-Vc for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:26 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNn-0005gi-Kj for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:18 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4891d7164ddso50193405e9.3 for ; Mon, 27 Apr 2026 05:48:13 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294092; x=1777898892; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=U6+LMwBwSx9z5uRa0bJxch1nnS9wZaiUEFSDL/4DmaI=; b=qBAeMCCubKzAMrmLM2RsCjqwKFrWzvujqZSmK91i6BR1rtJAelsrH8oHMljXxJQRId NpLY/26c2TqEUsmGTIS1YRKipt2Pb5z7pYGJGSZqvaTq686avIo0kdCo9xJQ/HmKWKfT GZ93nYRNdv11LmV9jBw3MR2hWIO6IiD3V3NBLX3ZKCQnHqD0MD2kdXasU8EKEJALP/jZ C/yd6tdOTEfExi3gowncSVvJXkmgPMfXbydirZ9Alf3B3FQtsJLfGaC0CDkxInpYvdn0 /fnwW85nOaOKC0MsMIYjBO77ZB9vpPcIVBs6xbECyiv2QrOcVDD5KI8TwdwWDGcyMo8f ZeXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294092; x=1777898892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=U6+LMwBwSx9z5uRa0bJxch1nnS9wZaiUEFSDL/4DmaI=; b=oWawovx2q1H03r8Lh4AoFN1rLju4fDaMyelwSW1uyTosAvLbxwxfp9ryaPYq67S814 Sx/OOoFJ5GplOmCdeEXLOLHgjrfpVO6eLx0F+8dGYrzsnlKePa0ZFIrLk/eIJt9HySO+ Rvr0yb5omA0G9W0bptF4DmABi7MobDAH3h08AL8FO7B0a5XwGGXA9jjHW8ljJCbPXfdi yL2oa7Hbmf2Ot9+WRCpdMsnVFJHOd+A8b4N8V2wqh0HXyYYbxZDcRfwHc90xwxDUZIwX 5vBJ1ocVIlJCJGCXCb8BomZucZqPk03IBXkd4dSFml/w/FK/pBJnkOmVJDpGjXi4+HLv tzjA== X-Gm-Message-State: AOJu0YwzECF6EQpviWFOs0zC3GRZffywk9l49XBrR+9b0C5spoWNLXUd 5xYGN07ywnwLWeAjg5dd8ZUIT9As4NbuWfl9nw9IuSl6lC1f7OoNcSNuIAhb4tQLYGAnIoEo/pb s8SRc X-Gm-Gg: AeBDievsB+CGG0aoANoIZ9YFP/QZLDQu2QtbQKD57dPphkflGACLXmex/5/RRpYXmOr 9vZVa+K1J8mXq5gInvT92UyXvhL1przOBuNe/A0iNkPxaku9vjcOZKwYg+bm9JWKmU7siUnx5Fx A0c6i8ciuc67iPv2aqThHPCvBRCWW4QzmnWYDPIyFvfNLRWw+x1sK5Frj3cQiic3K2TFBY+SstI hf7/mIqQcRbkIyAjSe0aRbhRMM7bNKwr2IpZ2oY0tCOX3Cq0wXpwCybtY2qZxKD4qHbASaHY0NX Buo6+vGERfmP8S+OXeef64uHHg3R/0Tno7K2wvobtRuSzQzJLzdkb3xHrqqTCs9s1LJZB1EYAkz jKd4ehjrerNaEQCimLiXVT3+EHJ6dwh1Ui6eQKRuOkZ0onA9oxL3HZ3o4G6ic/Lf29C7gE09W+d OTPwIpcZa0iGzRxOR9Ln8Bt0G2zYaZGIHgm8IScFlHACmOrE68nbYOpbQfDMRcOFtunXqPpHTMW gqHJyVrWArhyA547r1jnTNvd//u/U0qwaWgabUCxw== X-Received: by 2002:a05:600c:8a08:b0:488:a82f:bb9b with SMTP id 5b1f17b1804b1-488ff369a1cmr479913435e9.30.1777294092081; Mon, 27 Apr 2026 05:48:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/63] target/arm/cpu64: Define cpreg migration tolerance for KVM_REG_ARM_VENDOR_HYP_BMAP_2 Date: Mon, 27 Apr 2026 13:47:09 +0100 Message-ID: <20260427124738.966578-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294647556158500 Content-Type: text/plain; charset="utf-8" From: Eric Auger KVM_REG_ARM_VENDOR_HYP_BMAP_2 pseudo FW register is exposed from v6.15 onwards. Backward migration from a >=3D v6.15 to an older kernel would fail without cpreg migration tolerance definition for this register. If the register is present on source but not on destination, its value must be checked to make sure it matches the reset value, ie. 0, meaning no service is exposed to the guest, hence the choice of a ToleranceOnlySrcTestValue migration tolerance. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell Message-id: 20260420140552.104369-6-eric.auger@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e7014022df..a93ad2da5a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -834,6 +834,17 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *c= pu) 0, 0, ToleranceNotOnBothEnds); arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 3), 0, 0, ToleranceNotOnBothEnds); + + /* + * KVM_REG_ARM_VENDOR_HYP_BMAP_2 pseudo FW register is exposed + * from v6.15 onwards. Backward migration from a >=3D v6.15 to an older + * kernel would fail without cpreg migration tolerance definition. + * If the register is present on source but not on destination, make + * sure it has its reset value, ie. 0, meaning no service is exposed + * to the guest. + */ + arm_register_cpreg_mig_tolerance(cpu, KVM_REG_ARM_FW_FEAT_BMAP_REG(3), + UINT64_MAX, 0, ToleranceOnlySrcTestVa= lue); } #endif =20 --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294717; cv=none; d=zohomail.com; s=zohoarc; b=aLDuvbxOK+kjKDQyCx4eDdG7Tkt3xwtGScRIIypUzdSq4a3uKBlBrCBFhY3Yy6XashZLef31Kj8sHOoQ2Qv296ZRDuHU72G3FMb+BwofSOy7eGgGddnHnXgn8Cb01FkE/tbIU4SPv5VfW9BGluphtkE3IEvznn6eHrUV7fgI7GM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294717; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=mCeEgVnnw2NoZfiNYPPKxzrAmF2FxXpUQF4UmPnKyWU=; b=Ycr65kPRAUPVc0ohYj4S0hq5IDJcmeIJ2eg/pP7PxZ3B0ADh3nsQpZvmo16CXUYb0o8euT03nz505U2o7CeKrIQXQgRSH49Wzyr9DUCWUhgV3YZQPnDxeIFOH4FfqUpgZrL6of4IF/eOJq6Ulp3df8q+/PcVRl9rWLRUoCkFdDo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177729471732616.115111398839304; Mon, 27 Apr 2026 05:58:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUR-0007Ua-J0; Mon, 27 Apr 2026 08:55:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNw-00087D-QD for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:31 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNp-0005gv-KS for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:20 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-488ad135063so93525355e9.0 for ; Mon, 27 Apr 2026 05:48:14 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294093; x=1777898893; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mCeEgVnnw2NoZfiNYPPKxzrAmF2FxXpUQF4UmPnKyWU=; b=GdSubmyJuBpGlKDsynr7THtmRIZB/ERVOTihBXEHh3JWzjCSK5g5f7trU5viPs0VV3 PpjkX42CvS6wE3/v+eY8l0/TKUz2qKzbLr1hL/x6n3QRzZg9H3xt6Z89OxKe/ceE9nEa QydOp3sOjeIMaTrD1ToDPtYWHZ2SGbT6no5Vp1xUR0VwyZ43ufJhRwL3dh/vILDkdwK/ vxSRZEG7mwxLzC1qGT3Yp03dIHzx2HlShmKLMeyye5sgzHAJqK1NusfbTjpArcriwJkU jM+/uJ2Kmq6NTCfRoMA2uB3HPgDp7YOFZBoz2L1i0kKWhUrpIs9TEjhDr7+OlAA4Wvpk LGZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294093; x=1777898893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mCeEgVnnw2NoZfiNYPPKxzrAmF2FxXpUQF4UmPnKyWU=; b=Xl3aQCCk0ycp/VSmsQcjNbz6DbInzXyeuuznaFpSU9MwwyZ8oAvcXM3+N+BhnFO37+ GM1h9KTG4iakH5AW4CFFeSxboxt//oX8OOIG5QA4NMPB8d+8XDPKX/QhMMd8Nd/uT+JC Wwb+csnegy/6u/UdXFeLV7YvnisIGItDxdZR0SMPMDNN59HLmnnONKcy+rzGoUW0aziz QHqsY4X2I+8n8gqRv6Rsi5w/KodXG1TMTVfGUKDVmeII8B9tyP81Wc7442WoZb26xMuz arKEMYyU9xk3sxt0MCr2VF6KbMO/rtO0gZ7Z9NSrHDKaTodalrq6ENh5YlnO/BXw6bRm cOnA== X-Gm-Message-State: AOJu0Yy1TsWEbXpIMm7nrbfJEnJSgcqmg0L+YII/i8HHTNrBbyawzQZj S9cAo7CvpdFuMSv0O73jO7JvLQpsjsyDJ3JtMxulBecsMzpXYL+IRtl09sdA11/JLLEhlHNyBlB FKkzL X-Gm-Gg: AeBDiettLSp+2wxPtoGg2sl1SbeKupUp4z/xHpzpah8gZcHHBpOFWBTD19BCASE9lZ9 uTFdnuA987jTWgvDXq3DZ0r1BBV8TjfXuHDJqHGhFKelJls/UIsgyO8loKb/iCY123gZmTumcCv U6Pysrg3vaD5QoA0haC+VPYnCVTGVENHi3OMTtw5eGEhiGOPkA/WYRLGVqXu4ZRO3iaxCt8D7o0 /TA0XBXGHxv/M/IrkkEQCPXwKgiFWIvhLYvRL/zCXDOTTrWw1WKVxBJ85sFIgZGZEOA5DzrmD8s BLjf04iyvsJCkTOdJr81pneyOOYMS5SGsxmrjCplfwFaL+skQx2BrSCGH/Jhpp6VYllJVIx8x3z 5a1AvRc6L03goyJy6k7tGyysRNQ2A91ZEjuhUB96CCQ5Uy2eoq/9GlGW5q+OUJPIA6xHoa98hOA IhOyWnJzxk9hz8+4+NnYaKtq7n+FZpYByhQTMb4415aeLfcHrkICjVpZn6sm5FzsX5OuCqu3yh8 4isMGO09QFCYwxP4ygH6Na6ZG3k95CbIunllM8tCQ== X-Received: by 2002:a05:600c:4f0c:b0:489:1c1f:35e6 with SMTP id 5b1f17b1804b1-4891c1f38c8mr512857775e9.6.1777294093277; Mon, 27 Apr 2026 05:48:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/63] target/arm/helper: Define cpreg migration tolerance for DGBDTR_EL0 Date: Mon, 27 Apr 2026 13:47:10 +0100 Message-ID: <20260427124738.966578-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294717907158500 Content-Type: text/plain; charset="utf-8" From: Eric Auger We want to remove AArch32 DBGDTRTX which was erroneously exposed. This was attempted by 655659a74a36b ("target/arm: Correct encoding of Debug Communications Channel registers") but it was discovered that the removal of this debug register broke forward migration on TCG. Now we have the cpreg migration tolerance infrastructure, we can declare one for the DBGDTRTX. This allow to revert the reinstate patch. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott Reviewed-by: Peter Maydell Message-id: 20260420140552.104369-7-eric.auger@redhat.com [PMM: revised comment, included note about when we can drop the workaround] Signed-off-by: Peter Maydell --- target/arm/helper.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3ac88078aa..ccd6353190 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6349,9 +6349,32 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fgt =3D FGT_CLIDR_EL1, .resetvalue =3D GET_IDREG(isar, CLIDR) }; + uint64_t dbgtr_el0_kvmidx =3D + cpreg_to_kvm_id(ENCODE_CP_REG(14, 0, 1, 0, 5, 3, 0)); + define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); define_debug_regs(cpu); + /* + * We used to incorrectly expose a non-existent AArch32 "DBGDTRTX" + * register with this encoding. This has been fixed by commit + * 655659a74a36 ("target/arm: Correct encoding of Debug + * Communications Channel registers") by the introduction of corre= ct + * separate cpreg definitions for AA64 and AA32 versions. However, + * the old cpreg definition couldn't be removed without breaking + * migration, so commit 4f2b82f604 reinstated the bogus encoding + * for migration data only. + * + * Now that we have migration tolerance infrastructure, we can use + * this to allow forward migration from the buggy QEMU versions, + * accepting and ignoring the bogus register if it is in the + * source data. QEMU 11.0 was the last version that sent the + * bogus encoding, so this workaround can be removed at the point + * where we no longer care about migration from that version + * (i.e. when we remove the "virt-11.0" machine type). + */ + arm_register_cpreg_mig_tolerance(cpu, dbgtr_el0_kvmidx, + 0, 0, ToleranceNotOnBothEnds); } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294532; cv=none; d=zohomail.com; s=zohoarc; b=OSJaWv6bp877Vz56HjSThPT+CxjXVejFBpVzPAFwlXoNyEqG5cw5TXe6/8H4GAhZDNyBwlnmNwrXDjMFi+9vAC+mSRddrzz8H2D83W5+LDy9KYl0U+H3HSG8DZbLi677CyJ/EFJslEMHQ61i/yIjk+nSyb4HLgFvSPX4hUvjJt8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294532; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=EoqVhLGhx4yCMUlMBNquuLKcWQ2+z8TbZ+uuLLh8Iag=; b=Fk87lv/SVq6cH+t3EgK3BcYJfU2u/h4/XWmcoBij40njgXh0djp9LUt7ad3URgJvjWKawc95qvdXkhAra6x67XU5TM+u+9yZ3Op8D+Wc2cKHF+nReOsZg5JOmMdrezGcytUo9wnMIL4Fw4wwoHmjDaBe+fNxxdGeDqakI8GV8t4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294532169846.0802575379635; Mon, 27 Apr 2026 05:55:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLQz-0002sh-OP; Mon, 27 Apr 2026 08:51:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNy-00087g-WC for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:31 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNr-0005hI-Up for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:25 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-488af96f6b2so134257745e9.0 for ; Mon, 27 Apr 2026 05:48:15 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294094; x=1777898894; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EoqVhLGhx4yCMUlMBNquuLKcWQ2+z8TbZ+uuLLh8Iag=; b=XhAaqXETDXRjknmsL3MLmjQIjjxvkxuRQBNdylLUXbZ02VhMsLl39zDbmn3OQNNf1N Q0wHSO0zYrmq7+eskWLNekeEmYtF8n0LLa3vQIJEM2DNcVeRjSmT3h6y+sTLQrAO2vTz zh7DB277WTjV5lKdOGatJ7hc729P1Kps7GCWKloeeFw5rZDtOu2NGy6CCE17ESBwSBFQ hB+4csreLLgLe3mNiXx3vIDqiUaAeTH8bxz92LNq28SvJOr0UAVBNFxmjvGnGOZj1hov YTbN6Ok2FpQwMNByms7EK7Im7OHhiWmA8m5UttrMv1W0sjRvMBzZrJ0+khRjfefs3zPh h+rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294094; x=1777898894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=EoqVhLGhx4yCMUlMBNquuLKcWQ2+z8TbZ+uuLLh8Iag=; b=Xyu70JGigjEK2W+QCMR3kSpXA8hjpvthoEhz7z6JRjXlA4HTiNUk9T/Ze1E3cb4+Mn t/Xw7rdO2eEv6/g4mNzwwesfK59saVIZ5l6MUAqQokMjGxKsXY8YT0xYVRRw/e2Ggm0/ 9vxE8x2cIbURnQd8bbzdbrx4IZiG4xdvc4l/mnN8e+rKHqiWXkp9W50i7gF0GnB89Gl9 JaVX/rC8pjhwoujXiZpD6i0ucyZqry+6cNhyy94/FG5+j8E6RHuyJPghS0vjCWr886cq p9h7o5zxOtQiru7mOpxG9S9V+NQ7TfZXejA6vU2vlY3B4PpmsyRVS6CUaxqNyp1Dj0eM p1+Q== X-Gm-Message-State: AOJu0Yw2aC6omu0LY6IzNlt1UVFwMSzZ20E0cqOOvJJYO2u29LkPE8qE 8uD1DyA8tXOmngyJ0WwwI+wcxcs5EEb4Hj/YHXTXI5+0DkMgVF645NR0idV9J2lKPO5ArMyIEVe hvXTS X-Gm-Gg: AeBDiesWswc7kTXI8DnrYgTsZgyIoLQG/M2DZhwB4TBc/obQk22BekFcficAiPOevT+ 2Zl5/QEr9yhhy1xqFjYXSbuos48GtuH2zhGejubFWF3N9eQ4OYSqJ4R6+AkiS8eZOLi+npToVq/ WINEzrjzY2/UQC4BYhBLjdeF3et6UHys3TwpHMYKBn5TrtDwoUu8q/voxZN6Ld7g9CIPJAmZR9H 5Q60aOOlvMU8+3orJA6P9dhbbnJaTDkmtMgyd/OJO8B0IAM3qdKDDckoylS5IHwLeoFQsbUF4ei T2eCS9aOcAZIqZUlOx1tJUVhaz3b3toFkeIhr69++bT/WQc2QeGtGXYv8WLeiPotFhu4pCEVbx8 BV8FGdseWk171ZeTtTykTswxiuftoqTxgnMSDpmx7mIW4pbqAund49IlrPAbKXRVwcOiCNTCnOg PaALWwr5Wz09gC6aB02K8pUvKGhJzZ/bGs9sU6xK8aaZRq5Sg/8f+ha0rXXjyxnDevn25ECJ+ur 0kA6gFqTqaYHVZmJmgDwMy3CCpPgIzZdlEETDpKMw== X-Received: by 2002:a05:600c:190f:b0:48a:6315:da26 with SMTP id 5b1f17b1804b1-48a6315da72mr207675615e9.26.1777294094151; Mon, 27 Apr 2026 05:48:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/63] Revert "target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat" Date: Mon, 27 Apr 2026 13:47:11 +0100 Message-ID: <20260427124738.966578-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294532860158500 Content-Type: text/plain; charset="utf-8" From: Eric Auger This reverts commit 4f2b82f60431 ("target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat). We don't need that commit anymore as the AArch32 DBGDTRTX register is declared to be safe to ignore in the incoming migration stream. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott Reviewed-by: Peter Maydell Message-id: 20260420140552.104369-8-eric.auger@redhat.com Signed-off-by: Peter Maydell --- target/arm/debug_helper.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 352c8e5c8e..8477ca5def 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -171,13 +171,6 @@ static void dbgclaimclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, env->cp15.dbgclaim &=3D ~(value & 0xFF); } =20 -static CPAccessResult access_bogus(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* Always UNDEF, as if this cpreg didn't exist */ - return CP_ACCESS_UNDEFINED; -} - static const ARMCPRegInfo debug_cp_reginfo[] =3D { /* * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped @@ -240,28 +233,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 4, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * This is not a real AArch32 register. We used to incorrectly expose - * this due to a QEMU bug; to avoid breaking migration compatibility we - * need to continue to provide it so that we don't fail the inbound - * migration when it tells us about a sysreg that we don't have. - * We set an always-fails .accessfn, which means that the guest doesn't - * actually see this register (it will always UNDEF, identically to if - * there were no cpreg definition for it other than that we won't print - * a LOG_UNIMP message about it), and we set the ARM_CP_NO_GDB flag so= the - * gdbstub won't see it either. - * (We can't just set .access =3D 0, because add_cpreg_to_hashtable() - * helpfully ignores cpregs which aren't accessible to the highest - * implemented EL.) - * - * TODO: implement a system for being able to describe "this register - * can be ignored if it appears in the inbound stream"; then we can - * remove this temporary hack. - */ - { .name =3D "BOGUS_DBGDTR_EL0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 14, .opc1 =3D 3, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D access_bogus, - .type =3D ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue =3D 0 }, /* * OSECCR_EL1 provides a mechanism for an operating system * to access the contents of EDECCR. EDECCR is not implemented though, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294651; cv=none; d=zohomail.com; s=zohoarc; b=MdAvfefTvJnpYlPcXDLLClSLUeO78dTaZs91iAnn1AFHY0Xd6W0tV48F1Q+CcIpb5Af3eNBorAuRiISLO6LTLW8a9Va4UOu6g3bg4io/TZkU0TTG7zzSZTIyYoxLsjlPI9sG8Z0lvBCAj2ViTwZ1GOIzB0PsJPOTkFwVneuuDl8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294651; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=A6daU2nmrlZ4Sa/74iSVs+RucwjBTPr7uTOaBH+QKpw=; b=QzMqx1mzMWzdogBjf5KXGmHOOew6gJcfR1B+ATTuOHbwhy1/0pfDffms+cdDkZEuBFxthIq5r9Le1crYy8yXtQWPYtTxDVBaMHOWKqdXvuSdOlC2of1nUbV3Gi/gFH8F9HrNM1V8OHKtgu1ufGqA4S1iQ7AG1zxjPptjW/fQE10= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294651992317.7518299163446; Mon, 27 Apr 2026 05:57:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUP-0007IM-P0; Mon, 27 Apr 2026 08:55:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNw-00087F-QZ for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:31 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNq-0005hZ-NP for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:21 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-48334ee0aeaso107050295e9.1 for ; Mon, 27 Apr 2026 05:48:16 -0700 (PDT) Received: from lanath.. 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If the blob has more than one node with the same compatible string, extra nodes will remain active. Remove all the matching nodes, using the same loop as imx8mp-evk.c does for this purpose. Signed-off-by: Osama Abdelkader Message-id: 20260420162114.308519-1-osama.abdelkader@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/raspi4b.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c index 3eeb8f447e..06aeb8db01 100644 --- a/hw/arm/raspi4b.c +++ b/hw/arm/raspi4b.c @@ -72,12 +72,14 @@ static void raspi4_modify_dtb(const struct arm_boot_inf= o *info, void *fdt) =20 for (int i =3D 0; i < ARRAY_SIZE(nodes_to_remove); i++) { const char *dev_str =3D nodes_to_remove[i]; + int offset; =20 - int offset =3D fdt_node_offset_by_compatible(fdt, -1, dev_str); - if (offset >=3D 0) { - if (!fdt_nop_node(fdt, offset)) { - warn_report("bcm2711 dtc: %s has been disabled!", dev_str); + offset =3D fdt_node_offset_by_compatible(fdt, -1, dev_str); + while (offset >=3D 0) { + if (fdt_nop_node(fdt, offset) =3D=3D 0) { + warn_report("bcm2711 dtb: %s has been disabled!", dev_str); } + offset =3D fdt_node_offset_by_compatible(fdt, offset, dev_str); } } =20 --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294836; cv=none; d=zohomail.com; s=zohoarc; b=cAwc1IsfjNL0XyW8OewQ/c/A92PG+IdzDN0NmlVAaszpjs3RQkBPR+VyAkeW77ozVMFcycp3RTUDDM0ZVvn58DuMoWD4za/Y97Nv3H2rMBvjkGltNMpWpx+3GIsybJCo5ksCI7XWyyeq1ep/sS24IUgL+DGKtSMKEJlTxP/2eec= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294836; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xLiDu/iz5AsiqDXEjMsCtuoCWzBBhHTKjCH3+u/R2jY=; b=YP8k0dUMcjUbEOUfJOJkyRZd8oyHrZ5sNALj6UzZT/ydktZYQkp00nKbysXm90tb2ZVuNrLkYlpzZClOPYEOSfmqOIh+YLXdMnVjeR54gYGdAm/yZm3WwhOn/p27dntdafbOHXJpnfpQt7sEwZvhUw+Cme0Kmnt3wbjUwwgkRZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177729483642579.54481580693152; Mon, 27 Apr 2026 06:00:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUa-0008HR-3D; Mon, 27 Apr 2026 08:55:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLNw-00087G-R2 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:31 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNq-0005hk-Nl for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:22 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-48896199cbaso101474605e9.1 for ; Mon, 27 Apr 2026 05:48:17 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294096; x=1777898896; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xLiDu/iz5AsiqDXEjMsCtuoCWzBBhHTKjCH3+u/R2jY=; b=J5siPrjKN43LRkWd+ubuzJ413Fl4Z2hJ6VuS1n0u6U56GUR16DOWISMCVKPPv2BkGq I1TOvwAl7QsSNWVLxMKM8BF4dmEAuqCl5J6RIqZVO47l8NK5nmNp2F1Ozr0pwuhovHzI UlwhfPIGDH9yIFFZaMh1Or5i5C8A/EjLPfKv5CGjk924nfqX58ksf3u6/spSvus41qmd d0m0czGXYK1XG3fOmdL0CJdbS2QOpfl7k8wGmWlp/uwo7XNoFza6uwwCGseapZGSmchM isPUTtr+eH6iZmvdrMMRQ01TdnsqTw3RK3jIdCzVILQIIgGFhAQ9nuXxFbC0tiL4OEai 2ylw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294096; x=1777898896; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=xLiDu/iz5AsiqDXEjMsCtuoCWzBBhHTKjCH3+u/R2jY=; b=UxUtuI6RSWeA92lk17wNaVz18MaIGc8qJU2DBw/ndawT1fb/Jm3Ch7T4FLMoKRlyEz aqIC6Mj9lp5xPxKdFPgVdD1djP1mLSw+Fhc2yFGKm1CUENx1TMGloiPzzqWELxpmq+oV FK6wh7/kheHdw55W3iE4w1b6p99Wmlay1q3Qi8sO3hOcdJTI3XRQctoEGm0JKyOTGXN6 OQObpcJiXZE8lUn3ZxBPSDiw2riT0raIa9warqhtt6Oh+K9GuVJXzoN9QOAnKCaXp7WD wY3N7LRuv/i4wn54A3WTCWA3Pf7KfcQElhsfo9NcNdcsEEQfBmar+aZVHR9a9VVOHf1j 2jVw== X-Gm-Message-State: AOJu0YwvqrJdk3RlmsoL4pRkWbm335FAFOFp1O3dcYhmXUpmlYZ6v8fz rcGLHwFjl0E8y338cQnyeEG9bU7dZ4rzubtabyxE7wIEW98THCve2ia27HstPbDLe/mVAtiIprs gzwqA X-Gm-Gg: AeBDieskSek9DxD2qDbIl9W8ePHTGKtM20S+YYXBDCgmqYPyrlbD+GDsJC7CzO18uXy Hgm85cAALNMVkKAhrC3lfaS0YcRYpLxkMPjFOgBDquYhs/ToXvMmMpEKIfxSO/1Y+MgYGln3XjJ LP/hneK6JdLn1rKqRG1BOMCvZd9gAVGjXwBRG1K8wOCf7Z51euCUeRRH5oGBeQK7AtqnB4M1gwR rZY16eaMbpl2b13kbMAEtYarvtbbhy/DewOx6kF56rCUlLMCKP0bt+69RXB84YBjFqRnEFCSsT9 3NHHgJFZHWzmh3bn7nNOwj6YBBE8Ykguu6fYZU/3fwHQ/BIL6xprQcrnnCpzUWgGsiv4tRL+vV6 q3GjLYvLSHi3gkkL9tNfuvLguD27tWdikJrWHY45QAsRXQXi2dKFh/xYm64b7laleLcr2EQFqeI zcElSBdaqh7v/IPg8sIflAI69GtdbTSraR1loHgjomXALBcIJl+3dO3LFG2Cplf4WhFfACi+gTd Lzzf4Gm9BSZB4mOefU8BW71MWo1ubhZqchfqcfZPlTPq+LIqHt2 X-Received: by 2002:a05:600c:859a:b0:48a:53ea:13df with SMTP id 5b1f17b1804b1-48a53ea1500mr320879035e9.2.1777294095819; Mon, 27 Apr 2026 05:48:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/63] hw/display: Add i.MX6UL LCDIF device model Date: Mon, 27 Apr 2026 13:47:13 +0100 Message-ID: <20260427124738.966578-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294837107158500 Content-Type: text/plain; charset="utf-8" From: Yucai Liu <1486344514@qq.com> Implement a basic i.MX6UL LCDIF controller model with MMIO registers, frame-done interrupt behavior, and framebuffer-backed display updates for RGB565 and XRGB8888 input formats. Place the LCDIF device under hw/display and build it via a dedicated CONFIG_IMX6UL_LCDIF symbol. Model register fields with registerfields.h helpers and provide migration support via vmstate. Signed-off-by: Yucai Liu <1486344514@qq.com> Message-id: 20260412110240.93116-2-yangyanglan718@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- MAINTAINERS | 2 + hw/display/Kconfig | 4 + hw/display/imx6ul_lcdif.c | 453 ++++++++++++++++++++++++++++++ hw/display/meson.build | 1 + include/hw/display/imx6ul_lcdif.h | 37 +++ 5 files changed, 497 insertions(+) create mode 100644 hw/display/imx6ul_lcdif.c create mode 100644 include/hw/display/imx6ul_lcdif.h diff --git a/MAINTAINERS b/MAINTAINERS index 50a8e161c6..a23ff5279e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -894,8 +894,10 @@ L: qemu-arm@nongnu.org S: Odd Fixes F: hw/arm/mcimx6ul-evk.c F: hw/arm/fsl-imx6ul.c +F: hw/display/imx6ul_lcdif.c F: hw/misc/imx6ul_ccm.c F: include/hw/arm/fsl-imx6ul.h +F: include/hw/display/imx6ul_lcdif.h F: include/hw/misc/imx6ul_ccm.h F: docs/system/arm/mcimx6ul-evk.rst =20 diff --git a/hw/display/Kconfig b/hw/display/Kconfig index 1e95ab28ef..b3593fe981 100644 --- a/hw/display/Kconfig +++ b/hw/display/Kconfig @@ -25,6 +25,10 @@ config PL110 bool select FRAMEBUFFER =20 +config IMX6UL_LCDIF + bool + select FRAMEBUFFER + config SII9022 bool depends on I2C diff --git a/hw/display/imx6ul_lcdif.c b/hw/display/imx6ul_lcdif.c new file mode 100644 index 0000000000..33cd00fbe1 --- /dev/null +++ b/hw/display/imx6ul_lcdif.c @@ -0,0 +1,453 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * i.MX6UL LCDIF controller + * + * Copyright (c) 2026 Yucai Liu <1486344514@qq.com> + */ + +#include "qemu/osdep.h" +#include "hw/display/imx6ul_lcdif.h" +#include "hw/core/irq.h" +#include "hw/core/registerfields.h" +#include "hw/display/framebuffer.h" +#include "migration/vmstate.h" +#include "system/address-spaces.h" +#include "qemu/module.h" +#include "qemu/units.h" +#include "ui/pixel_ops.h" + +#define LCDIF_MMIO_SIZE (16 * KiB) +#define LCDIF_RESET_CTRL1 0x000f0000 + +REG32(CTRL, 0x00) + FIELD(CTRL, RUN, 0, 1) + FIELD(CTRL, WORD_LENGTH, 8, 2) +REG32(CTRL1, 0x10) + FIELD(CTRL1, CUR_FRAME_DONE_IRQ, 9, 1) + FIELD(CTRL1, CUR_FRAME_DONE_IRQ_EN, 13, 1) + FIELD(CTRL1, BYTE_PACKING_FORMAT, 16, 4) +REG32(V4_TRANSFER_COUNT, 0x30) + FIELD(V4_TRANSFER_COUNT, H_COUNT, 0, 16) + FIELD(V4_TRANSFER_COUNT, V_COUNT, 16, 16) +REG32(V4_CUR_BUF, 0x40) +REG32(V4_NEXT_BUF, 0x50) +REG32(AS_NEXT_BUF, 0x230) + +#define REG_SET 0x4 +#define REG_CLR 0x8 +#define REG_TOG 0xc + +#define CTRL_WORD_LENGTH_16 0 +#define CTRL_WORD_LENGTH_24 3 + +#define FRAME_PERIOD_NS (16 * 1000 * 1000ULL) + +enum IMX6ULLCDIFReg { + IMX6UL_LCDIF_REG_CTRL =3D A_CTRL >> 4, + IMX6UL_LCDIF_REG_CTRL1 =3D A_CTRL1 >> 4, + IMX6UL_LCDIF_REG_V4_TRANSFER_COUNT =3D A_V4_TRANSFER_COUNT >> 4, + IMX6UL_LCDIF_REG_V4_CUR_BUF =3D A_V4_CUR_BUF >> 4, + IMX6UL_LCDIF_REG_V4_NEXT_BUF =3D A_V4_NEXT_BUF >> 4, + IMX6UL_LCDIF_REG_AS_NEXT_BUF =3D A_AS_NEXT_BUF >> 4, +}; + +static inline bool imx6ul_lcdif_reg_exists(hwaddr reg) +{ + return (reg >> 4) < IMX6UL_LCDIF_REGS_NUM; +} + +static inline bool imx6ul_lcdif_reg_has_setclr(hwaddr reg) +{ + switch (reg) { + case A_CTRL: + case A_CTRL1: + return true; + default: + return false; + } +} + +static inline bool imx6ul_lcdif_is_running(IMX6ULLCDIFState *s) +{ + uint32_t ctrl =3D s->regs[IMX6UL_LCDIF_REG_CTRL]; + + return FIELD_EX32(ctrl, CTRL, RUN); +} + +static inline bool imx6ul_lcdif_frame_done_pending(IMX6ULLCDIFState *s) +{ + uint32_t ctrl1 =3D s->regs[IMX6UL_LCDIF_REG_CTRL1]; + + return FIELD_EX32(ctrl1, CTRL1, CUR_FRAME_DONE_IRQ); +} + +static void imx6ul_lcdif_schedule_frame(IMX6ULLCDIFState *s) +{ + int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + timer_mod(s->frame_timer, now + FRAME_PERIOD_NS); +} + +static void imx6ul_lcdif_maybe_schedule_frame(IMX6ULLCDIFState *s) +{ + if (imx6ul_lcdif_is_running(s) && !imx6ul_lcdif_frame_done_pending(s))= { + imx6ul_lcdif_schedule_frame(s); + } else { + timer_del(s->frame_timer); + } +} + +static void imx6ul_lcdif_update_irq(IMX6ULLCDIFState *s) +{ + uint32_t ctrl1 =3D s->regs[IMX6UL_LCDIF_REG_CTRL1]; + bool level =3D FIELD_EX32(ctrl1, CTRL1, CUR_FRAME_DONE_IRQ_EN) && + FIELD_EX32(ctrl1, CTRL1, CUR_FRAME_DONE_IRQ); + + qemu_set_irq(s->irq, level); +} + +static void imx6ul_lcdif_frame_done(IMX6ULLCDIFState *s) +{ + uint32_t ctrl1 =3D s->regs[IMX6UL_LCDIF_REG_CTRL1]; + + ctrl1 =3D FIELD_DP32(ctrl1, CTRL1, CUR_FRAME_DONE_IRQ, 1); + s->regs[IMX6UL_LCDIF_REG_CTRL1] =3D ctrl1; + imx6ul_lcdif_update_irq(s); +} + +static void imx6ul_lcdif_draw_line_rgb565(void *opaque, uint8_t *dst, + const uint8_t *src, int width, + int dststep) +{ + uint32_t *dst32 =3D (uint32_t *)dst; + int i; + + for (i =3D 0; i < width; i++) { + uint16_t pixel =3D lduw_le_p(src); + uint8_t r =3D ((pixel >> 11) & 0x1f) << 3; + uint8_t g =3D ((pixel >> 5) & 0x3f) << 2; + uint8_t b =3D (pixel & 0x1f) << 3; + + *dst32++ =3D rgb_to_pixel32(r, g, b); + src +=3D 2; + } +} + +static void imx6ul_lcdif_draw_line_xrgb8888(void *opaque, uint8_t *dst, + const uint8_t *src, int width, + int dststep) +{ + uint32_t *dst32 =3D (uint32_t *)dst; + int i; + + for (i =3D 0; i < width; i++) { + uint32_t pixel =3D ldl_le_p(src); + uint8_t r =3D (pixel >> 16) & 0xff; + uint8_t g =3D (pixel >> 8) & 0xff; + uint8_t b =3D pixel & 0xff; + + *dst32++ =3D rgb_to_pixel32(r, g, b); + src +=3D 4; + } +} + +static void imx6ul_lcdif_update_display(void *opaque) +{ + IMX6ULLCDIFState *s =3D opaque; + DisplaySurface *surface =3D qemu_console_surface(s->con); + uint32_t transfer_count =3D s->regs[IMX6UL_LCDIF_REG_V4_TRANSFER_COUNT= ]; + uint32_t width =3D FIELD_EX32(transfer_count, V4_TRANSFER_COUNT, H_COU= NT); + uint32_t height =3D FIELD_EX32(transfer_count, V4_TRANSFER_COUNT, V_CO= UNT); + uint32_t ctrl =3D s->regs[IMX6UL_LCDIF_REG_CTRL]; + uint32_t frame_base =3D s->regs[IMX6UL_LCDIF_REG_V4_CUR_BUF]; + drawfn fn; + int first =3D 0; + int last =3D 0; + int src_width; + + if (!imx6ul_lcdif_is_running(s) || width =3D=3D 0 || height =3D=3D 0) { + return; + } + + switch (FIELD_EX32(ctrl, CTRL, WORD_LENGTH)) { + case CTRL_WORD_LENGTH_16: + s->src_bpp =3D 2; + fn =3D imx6ul_lcdif_draw_line_rgb565; + break; + case CTRL_WORD_LENGTH_24: + s->src_bpp =3D 4; + fn =3D imx6ul_lcdif_draw_line_xrgb8888; + break; + default: + return; + } + + if (surface_width(surface) !=3D width || surface_height(surface) !=3D = height) { + qemu_console_resize(s->con, width, height); + surface =3D qemu_console_surface(s->con); + s->invalidate =3D true; + } + + src_width =3D width * s->src_bpp; + if (s->invalidate || s->fb_base !=3D frame_base || + s->src_width !=3D src_width || s->rows !=3D height) { + framebuffer_update_memory_section(&s->fbsection, get_system_memory= (), + frame_base, height, src_width); + s->fb_base =3D frame_base; + s->src_width =3D src_width; + s->rows =3D height; + } + + framebuffer_update_display(surface, &s->fbsection, width, height, + src_width, surface_stride(surface), 0, + s->invalidate, fn, s, &first, &last); + if (first >=3D 0) { + dpy_gfx_update(s->con, 0, first, width, last - first + 1); + } + + s->invalidate =3D false; +} + +static void imx6ul_lcdif_invalidate_display(void *opaque) +{ + IMX6ULLCDIFState *s =3D opaque; + + s->invalidate =3D true; +} + +static const GraphicHwOps imx6ul_lcdif_graphic_ops =3D { + .invalidate =3D imx6ul_lcdif_invalidate_display, + .gfx_update =3D imx6ul_lcdif_update_display, +}; + +static void imx6ul_lcdif_frame_timer_cb(void *opaque) +{ + IMX6ULLCDIFState *s =3D opaque; + + if (!imx6ul_lcdif_is_running(s) || imx6ul_lcdif_frame_done_pending(s))= { + return; + } + + imx6ul_lcdif_frame_done(s); +} + +static uint64_t imx6ul_lcdif_read(void *opaque, hwaddr offset, unsigned si= ze) +{ + IMX6ULLCDIFState *s =3D opaque; + hwaddr reg =3D offset & ~0xf; + uint32_t idx; + + assert(size =3D=3D 4); + assert(!(offset & 0x3)); + assert(offset < LCDIF_MMIO_SIZE); + + idx =3D reg >> 4; + if (idx >=3D ARRAY_SIZE(s->regs)) { + return 0; + } + + return s->regs[idx]; +} + +static void imx6ul_lcdif_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + IMX6ULLCDIFState *s =3D opaque; + hwaddr reg =3D offset & ~0xf; + uint32_t idx; + uint32_t oldv; + + assert(size =3D=3D 4); + assert(!(offset & 0x3)); + assert(offset < LCDIF_MMIO_SIZE); + + if (!imx6ul_lcdif_reg_exists(reg)) { + return; + } + + idx =3D reg >> 4; + oldv =3D s->regs[idx]; + + switch (offset & 0xf) { + case 0: + s->regs[idx] =3D (uint32_t)value; + break; + case REG_SET: + if (!imx6ul_lcdif_reg_has_setclr(reg)) { + return; + } + s->regs[idx] =3D oldv | (uint32_t)value; + break; + case REG_CLR: + if (!imx6ul_lcdif_reg_has_setclr(reg)) { + return; + } + s->regs[idx] =3D oldv & ~(uint32_t)value; + break; + case REG_TOG: + if (!imx6ul_lcdif_reg_has_setclr(reg)) { + return; + } + s->regs[idx] =3D oldv ^ (uint32_t)value; + break; + default: + g_assert_not_reached(); + } + + switch (reg) { + case A_CTRL: + if (!FIELD_EX32(oldv, CTRL, RUN) && + FIELD_EX32(s->regs[idx], CTRL, RUN)) { + s->invalidate =3D true; + graphic_hw_invalidate(s->con); + imx6ul_lcdif_maybe_schedule_frame(s); + break; + } + if (FIELD_EX32(oldv, CTRL, RUN) && + !FIELD_EX32(s->regs[idx], CTRL, RUN)) { + timer_del(s->frame_timer); + } + break; + case A_CTRL1: + if (FIELD_EX32(oldv, CTRL1, CUR_FRAME_DONE_IRQ) && + !FIELD_EX32(s->regs[idx], CTRL1, CUR_FRAME_DONE_IRQ)) { + imx6ul_lcdif_maybe_schedule_frame(s); + } + break; + case A_V4_TRANSFER_COUNT: + s->invalidate =3D true; + graphic_hw_invalidate(s->con); + break; + case A_V4_CUR_BUF: + s->invalidate =3D true; + graphic_hw_invalidate(s->con); + break; + case A_V4_NEXT_BUF: + s->regs[IMX6UL_LCDIF_REG_V4_CUR_BUF] =3D s->regs[idx]; + imx6ul_lcdif_frame_done(s); + s->invalidate =3D true; + graphic_hw_invalidate(s->con); + imx6ul_lcdif_maybe_schedule_frame(s); + return; + case A_AS_NEXT_BUF: + imx6ul_lcdif_frame_done(s); + imx6ul_lcdif_maybe_schedule_frame(s); + return; + default: + break; + } + + imx6ul_lcdif_update_irq(s); +} + +static const MemoryRegionOps imx6ul_lcdif_ops =3D { + .read =3D imx6ul_lcdif_read, + .write =3D imx6ul_lcdif_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx6ul_lcdif_reset(DeviceState *dev) +{ + IMX6ULLCDIFState *s =3D IMX6UL_LCDIF(dev); + + memset(s->regs, 0, sizeof(s->regs)); + s->regs[IMX6UL_LCDIF_REG_CTRL1] =3D LCDIF_RESET_CTRL1; + s->fb_base =3D 0; + s->src_width =3D 0; + s->rows =3D 0; + s->src_bpp =3D 0; + s->invalidate =3D true; + timer_del(s->frame_timer); + imx6ul_lcdif_update_irq(s); +} + +static int imx6ul_lcdif_post_load(void *opaque, int version_id) +{ + IMX6ULLCDIFState *s =3D opaque; + + s->fb_base =3D 0; + s->src_width =3D 0; + s->rows =3D 0; + s->src_bpp =3D 0; + s->invalidate =3D true; + + imx6ul_lcdif_update_irq(s); + if (imx6ul_lcdif_is_running(s) && + !imx6ul_lcdif_frame_done_pending(s) && + !timer_pending(s->frame_timer)) { + imx6ul_lcdif_schedule_frame(s); + } + + return 0; +} + +static const VMStateDescription vmstate_imx6ul_lcdif =3D { + .name =3D TYPE_IMX6UL_LCDIF, + .version_id =3D 1, + .minimum_version_id =3D 1, + .post_load =3D imx6ul_lcdif_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, IMX6ULLCDIFState, IMX6UL_LCDIF_REGS_NUM= ), + VMSTATE_TIMER_PTR(frame_timer, IMX6ULLCDIFState), + VMSTATE_END_OF_LIST() + }, +}; + +static void imx6ul_lcdif_realize(DeviceState *dev, Error **errp) +{ + IMX6ULLCDIFState *s =3D IMX6UL_LCDIF(dev); + + s->frame_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + imx6ul_lcdif_frame_timer_cb, s); + s->invalidate =3D true; + memory_region_init_io(&s->iomem, OBJECT(dev), &imx6ul_lcdif_ops, s, + TYPE_IMX6UL_LCDIF, LCDIF_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); + s->con =3D graphic_console_init(dev, 0, &imx6ul_lcdif_graphic_ops, s); +} + +static void imx6ul_lcdif_unrealize(DeviceState *dev) +{ + IMX6ULLCDIFState *s =3D IMX6UL_LCDIF(dev); + + timer_del(s->frame_timer); + timer_free(s->frame_timer); + s->frame_timer =3D NULL; + + if (s->con) { + graphic_console_close(s->con); + s->con =3D NULL; + } +} + +static void imx6ul_lcdif_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D imx6ul_lcdif_realize; + dc->unrealize =3D imx6ul_lcdif_unrealize; + dc->vmsd =3D &vmstate_imx6ul_lcdif; + device_class_set_legacy_reset(dc, imx6ul_lcdif_reset); + dc->desc =3D "i.MX6UL LCDIF"; +} + +static const TypeInfo imx6ul_lcdif_info =3D { + .name =3D TYPE_IMX6UL_LCDIF, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMX6ULLCDIFState), + .class_init =3D imx6ul_lcdif_class_init, +}; + +static void imx6ul_lcdif_register_types(void) +{ + type_register_static(&imx6ul_lcdif_info); +} + +type_init(imx6ul_lcdif_register_types) diff --git a/hw/display/meson.build b/hw/display/meson.build index e730c289b1..ffecedbf70 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -12,6 +12,7 @@ system_ss.add(when: ['CONFIG_VGA_CIRRUS', 'CONFIG_VGA_ISA= '], if_true: files('cir system_ss.add(when: 'CONFIG_G364FB', if_true: files('g364fb.c')) system_ss.add(when: 'CONFIG_JAZZ_LED', if_true: files('jazz_led.c')) system_ss.add(when: 'CONFIG_PL110', if_true: files('pl110.c')) +system_ss.add(when: 'CONFIG_IMX6UL_LCDIF', if_true: files('imx6ul_lcdif.c'= )) system_ss.add(when: 'CONFIG_SII9022', if_true: files('sii9022.c')) system_ss.add(when: 'CONFIG_SSD0303', if_true: files('ssd0303.c')) system_ss.add(when: 'CONFIG_SSD0323', if_true: files('ssd0323.c')) diff --git a/include/hw/display/imx6ul_lcdif.h b/include/hw/display/imx6ul_= lcdif.h new file mode 100644 index 0000000000..42fee2fd1d --- /dev/null +++ b/include/hw/display/imx6ul_lcdif.h @@ -0,0 +1,37 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * + * i.MX6UL LCDIF controller + * + * Copyright (c) 2026 Yucai Liu <1486344514@qq.com> + */ + +#ifndef IMX6UL_LCDIF_H +#define IMX6UL_LCDIF_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "qemu/timer.h" +#include "ui/console.h" + +#define TYPE_IMX6UL_LCDIF "imx6ul-lcdif" +#define IMX6UL_LCDIF_REGS_NUM ((0x230 >> 4) + 1) +OBJECT_DECLARE_SIMPLE_TYPE(IMX6ULLCDIFState, IMX6UL_LCDIF) + +struct IMX6ULLCDIFState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + MemoryRegionSection fbsection; + qemu_irq irq; + QemuConsole *con; + QEMUTimer *frame_timer; + uint32_t fb_base; + uint32_t src_width; + uint32_t rows; + uint8_t src_bpp; + bool invalidate; + uint32_t regs[IMX6UL_LCDIF_REGS_NUM]; +}; + +#endif /* IMX6UL_LCDIF_H */ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294297; cv=none; d=zohomail.com; s=zohoarc; b=J5Y2/h3NhK7rI/4+/lRGw5F5SMTfTVnFSjwAMp43Je368cmQOK5wtjrxdiMyW/2mMlCYIWlh5RZk6UFvJlhOpYnNsxbaLpprDAo0rJj13tog6mEU7Z6NdrMjm8mAkVd0dRY7hMRqjWIP13TqSxfyvRZTb+yUBcM6QSh+G5Lqydg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294297; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Also make FSL_IMX6UL select CONFIG_IMX6UL_LCDIF and map the LCDIF region with a 16 KiB size to match the SoC memory map. Signed-off-by: Yucai Liu <1486344514@qq.com> Message-id: 20260412110240.93116-3-yangyanglan718@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/fsl-imx6ul.c | 12 ++++++++++-- include/hw/arm/fsl-imx6ul.h | 4 +++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index b940af9345..c31752e83a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -656,6 +656,7 @@ config FSL_IMX6UL imply I2C_DEVICES select A15MPCORE select IMX + select IMX6UL_LCDIF select IMX_FEC select IMX_I2C select IMX_USBPHY diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 225e179126..1863558a0d 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx6ul.h" +#include "hw/display/imx6ul_lcdif.h" #include "hw/misc/unimp.h" #include "hw/usb/imx-usb-phy.h" #include "hw/core/boards.h" @@ -136,6 +137,11 @@ static void fsl_imx6ul_init(Object *obj) object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); } =20 + /* + * LCDIF + */ + object_initialize_child(obj, "lcdif", &s->lcdif, TYPE_IMX6UL_LCDIF); + /* * SDHCIs */ @@ -656,8 +662,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error= **errp) /* * LCD */ - create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, - FSL_IMX6UL_LCDIF_SIZE); + sysbus_realize(SYS_BUS_DEVICE(&s->lcdif), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->lcdif), 0, FSL_IMX6UL_LCDIF_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lcdif), 0, + qdev_get_gpio_in(gic, FSL_IMX6UL_LCDIF_IRQ)); =20 /* * CSU diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index f8f9c249a2..6205fe6b77 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -33,6 +33,7 @@ #include "hw/net/imx_fec.h" #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" +#include "hw/display/imx6ul_lcdif.h" #include "system/memory.h" #include "target/arm/cpu.h" #include "qom/object.h" @@ -84,6 +85,7 @@ struct FslIMX6ULState { IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS]; IMXUSBPHYState usbphy[FSL_IMX6UL_NUM_USB_PHYS]; ChipideaState usb[FSL_IMX6UL_NUM_USBS]; + IMX6ULLCDIFState lcdif; MemoryRegion rom; MemoryRegion caam; MemoryRegion ocram; @@ -143,7 +145,7 @@ enum FslIMX6ULMemoryMap { FSL_IMX6UL_PXP_SIZE =3D (16 * KiB), =20 FSL_IMX6UL_LCDIF_ADDR =3D 0x021C8000, - FSL_IMX6UL_LCDIF_SIZE =3D 0x100, + FSL_IMX6UL_LCDIF_SIZE =3D (16 * KiB), =20 FSL_IMX6UL_CSI_ADDR =3D 0x021C4000, FSL_IMX6UL_CSI_SIZE =3D 0x100, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294745; cv=none; d=zohomail.com; s=zohoarc; b=gVld2uxHU/zrGGYOc7dKfaIb2Z7fHI5CiZ1z0mbJFc3Ec5iwXiqjozo9cHU3ZRSN5jOxA08kJO2dEyXQ5lO6W/l3lvaWJAHg/Lv39PgKRzEVLUngV8BORU6r0hSGY0XuPjrFtrb9eZxprSeRU5i6FH1xRmP9NqVXeMoESgc6Has= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294745; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=YcYVYYNIRSP1snD5TdIYSPjOwpX5L7NMhYaBvEW9/ZM=; b=inBL1eEjKT9CyOmqm2iBcWcUHv9trNjhYuqdJ4b0RV4Zb/Hve/Y28up3iWGT6K9UZF3DKRilJUw5ceOoDQIMBRwRSnOQqYRZbak2VtJFmiUp+StFfXE0Fz1/VLS5UZzINnHfs1tJySIHeyrCJgvgtPHcnmCXVkutFUPFQBitVF4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294745124412.03614364427506; Mon, 27 Apr 2026 05:59:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUf-0000TP-Tu; Mon, 27 Apr 2026 08:55:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0008BG-OW for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNr-0005iF-OH for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:27 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-488b3f8fa2bso103395805e9.1 for ; Mon, 27 Apr 2026 05:48:19 -0700 (PDT) Received: from lanath.. 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Define the basic syndrome layout and convert the helpers that take the imm16 data directly. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-2-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 75 ++++++++++++++++++++++++++++++++----------- 1 file changed, 57 insertions(+), 18 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index bff61f052c..517fb2368b 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -25,7 +25,7 @@ #ifndef TARGET_ARM_SYNDROME_H #define TARGET_ARM_SYNDROME_H =20 -#include "qemu/bitops.h" +#include "hw/core/registerfields.h" =20 /* Valid Syndrome Register EC field values */ enum arm_exception_class { @@ -76,6 +76,11 @@ enum arm_exception_class { EC_AA64_BKPT =3D 0x3c, }; =20 +/* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */ +FIELD(SYNDROME, EC, 26, 6) +FIELD(SYNDROME, IL, 25, 1) +FIELD(SYNDROME, ISS, 0, 25) + typedef enum { SME_ET_AccessTrap, SME_ET_Streaming, @@ -113,12 +118,12 @@ typedef enum { =20 static inline uint32_t syn_get_ec(uint32_t syn) { - return syn >> ARM_EL_EC_SHIFT; + return FIELD_EX32(syn, SYNDROME, EC); } =20 static inline uint32_t syn_set_ec(uint32_t syn, uint32_t ec) { - return deposit32(syn, ARM_EL_EC_SHIFT, ARM_EL_EC_LENGTH, ec); + return FIELD_DP32(syn, SYNDROME, EC, ec); } =20 /* @@ -133,49 +138,74 @@ static inline uint32_t syn_set_ec(uint32_t syn, uint3= 2_t ec) */ static inline uint32_t syn_uncategorized(void) { - return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_UNCATEGORIZED); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 +FIELD(ISS_IMM16, IMM16, 0, 16) + static inline uint32_t syn_aa64_svc(uint32_t imm16) { - return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_SVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_hvc(uint32_t imm16) { - return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_HVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_smc(uint32_t imm16) { - return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA64_SMC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) { - return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); + uint32_t res =3D syn_set_ec(0, EC_AA32_SVC); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_hvc(uint32_t imm16) { - return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); + uint32_t res =3D syn_set_ec(0, EC_AA32_HVC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_smc(void) { - return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_AA32_SMC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_aa64_bkpt(uint32_t imm16) { - return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff= ); + uint32_t res =3D syn_set_ec(0, EC_AA64_BKPT); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) { - return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) - | (is_16bit ? 0 : ARM_EL_IL); + uint32_t res =3D syn_set_ec(0, EC_AA32_BKPT); + res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); + return res; } =20 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, @@ -246,7 +276,9 @@ static inline uint32_t syn_simd_access_trap(int cv, int= cond, bool is_16bit) =20 static inline uint32_t syn_sve_access_trap(void) { - return (EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_SVEACCESSTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 /* @@ -361,12 +393,16 @@ static inline uint32_t syn_wfx(int cv, int cond, int = ti, bool is_16bit) =20 static inline uint32_t syn_illegalstate(void) { - return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_ILLEGALSTATE); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_pcalignment(void) { - return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_PCALIGNMENT); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn) @@ -388,7 +424,10 @@ static inline uint32_t syn_gcs_gcsstr(int ra, int rn) =20 static inline uint32_t syn_serror(uint32_t extra) { - return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; + uint32_t res =3D syn_set_ec(0, EC_SERROR); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, SYNDROME, ISS, extra); + return res; } =20 static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294623; cv=none; d=zohomail.com; s=zohoarc; b=QmXrBMF0pTH5/CjNhe9D8F2MRzDN4oCkAiR3jrBvR12yk3O1obVu6n2GohmWMbrjZ3OsuSk3Ji8/TzlRZRS3nxDuW+H9ojD+9QKnRQZ278Ex/C3jO1gj64Fok2ZR0IvuplnJFbJfjyBEVmSS8b8JWlxAbsvses5icADKRMR+KYo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294623; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=SJipAdayGX2WmDgNJX5wmrQEzJn24e51it/1vwkX3Wc=; b=OhsURHA9XT6fulMxXLlkC1Dxw+oZdTmh+4i7ILbVeHu8s/eAXsdkITRoe5cA4r1oX/Na51xgcvBdUM1XrukkZHKI64RvhD6BqVzzGADMaSOEkUpNZgyoBIzmzU00VfGtUPe68IJoEVTyRqicdMcBtYU8x1SgeYQgUq2WeZHbKXw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294623701728.3836204317457; Mon, 27 Apr 2026 05:57:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUd-0000B8-TI; Mon, 27 Apr 2026 08:55:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0008BO-SO for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNw-0005ic-IS for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:27 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-48334ee0aeaso107050985e9.1 for ; Mon, 27 Apr 2026 05:48:19 -0700 (PDT) Received: from lanath.. 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The co-processor syndromes are split between single and duel register moves. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-3-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 124 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 102 insertions(+), 22 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 517fb2368b..29462aa103 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -78,7 +78,7 @@ enum arm_exception_class { =20 /* Generic syndrome encoding layout for HSR and lower 32 bits of ESR_EL2 */ FIELD(SYNDROME, EC, 26, 6) -FIELD(SYNDROME, IL, 25, 1) +FIELD(SYNDROME, IL, 25, 1) /* IL=3D1 for 32 bit instructions */ FIELD(SYNDROME, ISS, 0, 25) =20 typedef enum { @@ -172,7 +172,7 @@ static inline uint32_t syn_aa64_smc(uint32_t imm16) static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) { uint32_t res =3D syn_set_ec(0, EC_AA32_SVC); - res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); return res; } @@ -203,58 +203,138 @@ static inline uint32_t syn_aa64_bkpt(uint32_t imm16) static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) { uint32_t res =3D syn_set_ec(0, EC_AA32_BKPT); - res =3D FIELD_DP32(res, SYNDROME, IL, is_16bit ? 0 : 1); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); res =3D FIELD_DP32(res, ISS_IMM16, IMM16, imm16); return res; } =20 +/* + * ISS encoding for an exception from MSR, MRS, or System instruction + * in AArch64 state. + */ +FIELD(SYSREG_ISS, ISREAD, 0, 1) /* Direction, 1 is read */ +FIELD(SYSREG_ISS, CRM, 1, 4) +FIELD(SYSREG_ISS, RT, 5, 5) +FIELD(SYSREG_ISS, CRN, 10, 4) +FIELD(SYSREG_ISS, OP1, 14, 3) +FIELD(SYSREG_ISS, OP2, 17, 3) +FIELD(SYSREG_ISS, OP0, 20, 2) + static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, int crn, int crm, int rt, int isread) { - return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL - | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) - | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_SYSTEMREGISTERTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, SYSREG_ISS, OP0, op0); + res =3D FIELD_DP32(res, SYSREG_ISS, OP2, op2); + res =3D FIELD_DP32(res, SYSREG_ISS, OP1, op1); + res =3D FIELD_DP32(res, SYSREG_ISS, CRN, crn); + res =3D FIELD_DP32(res, SYSREG_ISS, RT, rt); + res =3D FIELD_DP32(res, SYSREG_ISS, CRM, crm); + res =3D FIELD_DP32(res, SYSREG_ISS, ISREAD, isread); + + return res; } =20 +/* + * ISS encoding for an exception from an MCR or MRC access + * (move to/from co-processor) + */ +FIELD(COPROC_ISS, ISREAD, 0, 1) +FIELD(COPROC_ISS, CRM, 1, 4) +FIELD(COPROC_ISS, RT, 5, 5) +FIELD(COPROC_ISS, CRN, 10, 4) +FIELD(COPROC_ISS, OP1, 14, 3) +FIELD(COPROC_ISS, OP2, 17, 3) +FIELD(COPROC_ISS, COND, 20, 4) +FIELD(COPROC_ISS, CV, 24, 1) + static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int op= c2, int crn, int crm, int rt, int isre= ad, bool is_16bit) { - return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP14RTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, COPROC_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_ISS, OP2, opc2); + res =3D FIELD_DP32(res, COPROC_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_ISS, CRN, crn); + res =3D FIELD_DP32(res, COPROC_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int op= c2, int crn, int crm, int rt, int isre= ad, bool is_16bit) { - return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) - | (crn << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP15RTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, COPROC_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_ISS, OP2, opc2); + res =3D FIELD_DP32(res, COPROC_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_ISS, CRN, crn); + res =3D FIELD_DP32(res, COPROC_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_ISS, ISREAD, isread); + + return res; } =20 +/* + * ISS encoding for an exception from an MCRR or MRRC access + * (move to/from co-processor with 2 regs) + */ +FIELD(COPROC_R2_ISS, ISREAD, 0, 1) +FIELD(COPROC_R2_ISS, CRM, 1, 4) +FIELD(COPROC_R2_ISS, RT, 5, 5) +FIELD(COPROC_R2_ISS, RT2, 10, 5) +FIELD(COPROC_R2_ISS, OP1, 16, 4) +FIELD(COPROC_R2_ISS, COND, 20, 4) +FIELD(COPROC_R2_ISS, CV, 24, 1) + static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int c= rm, int rt, int rt2, int isread, bool is_16bit) { - return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP14RRTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, COPROC_R2_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_R2_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_R2_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int c= rm, int rt, int rt2, int isread, bool is_16bit) { - return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (opc1 << 16) - | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; + uint32_t res =3D syn_set_ec(0, EC_CP15RRTTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, COPROC_R2_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_R2_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_R2_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT2, rt2); + res =3D FIELD_DP32(res, COPROC_R2_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_R2_ISS, CRM, crm); + res =3D FIELD_DP32(res, COPROC_R2_ISS, ISREAD, isread); + + return res; } =20 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294295; cv=none; d=zohomail.com; s=zohoarc; b=OpjMtAVz2nOwdQiwx0+sCTjsizFpzuVKWxUM4QA1rK19O5dm7tb7hf6a71TtKcnsYBhSfkjHxUyUkqSUrJUFm8xSwAD2LlMcl5UhbfyGTvmYP5jYCBJJ+S8sc93u7ZjVyIasEorrOyu7IX+vvgqhU1r6BDqR68gBtuXlEX7Isfs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294295; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=JQoy/74+JPqjK/uUVejtPxwT3Exjei52SuJo0vtd7fU=; b=M1tutQwfNLbG6/LbaREliOKz/o9UwKxiLQLb8gWKRB46MIxqQHAlAdNX/4+cw82SvEnZw12wLhN39Br8Q31Cx152GmOCULe/cy4/cuv4HY+byjEGyuEWJvs4H2o5HZLdL9ihjRCswOMziOGB5sPtkFelVQc2OI6QvpL6O3KRxqw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294295348982.3156650372927; Mon, 27 Apr 2026 05:51:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLQl-0002Wj-5f; Mon, 27 Apr 2026 08:51:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0008BK-Q1 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNw-0005iu-JD for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:27 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-488ff90d6c7so87216145e9.2 for ; Mon, 27 Apr 2026 05:48:20 -0700 (PDT) Received: from lanath.. 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We should only see the COPROC encoding on v7 architectures. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-4-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 29462aa103..72051443d5 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -337,21 +337,26 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int = cond, int opc1, int crm, return res; } =20 +/* + * ISS encoding for an exception from an access to a register of + * instruction resulting from the FPEN or TFP traps. + */ +FIELD(FP_ISS, COPROC, 0, 4) /* ARMv7 only */ +FIELD(FP_ISS, COND, 20, 4) +FIELD(FP_ISS, CV, 24, 1) + static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit, int coproc) { /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA =3D=3D 0 */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | coproc; -} + uint32_t res =3D syn_set_ec(0, EC_ADVSIMDFPACCESSTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); =20 -static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bi= t) -{ - /* AArch32 SIMD trap: TA =3D=3D 1 coproc =3D=3D 0 */ - return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20) | (1 << 5); + res =3D FIELD_DP32(res, FP_ISS, CV, cv); + res =3D FIELD_DP32(res, FP_ISS, COND, cond); + res =3D FIELD_DP32(res, FP_ISS, COPROC, coproc); + + return res; } =20 static inline uint32_t syn_sve_access_trap(void) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294720; cv=none; d=zohomail.com; s=zohoarc; b=AR21StFcEojTdHCvFIfn/3CjSedirXlgJbP0s76fBDWVywSiUnqwqONwaoa0fDwxkX9BhPb2+qAbANZLeKc2EOOs2EOGC/krnad39/JAKigOusqHyZlN95AEFwd41WjKmKNWt4a4CxsnhDZvDeMNiVNSqjzxFYKpo8COTRUIsNs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294720; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DTW9JTovBn9qcOa6N2q6qfwrq5ih1ehtyvkagKiaSQo=; b=ndd7AkkI966OgZy4rclv7IXmlplZPbpxS22D6AdI5b4DyMAR4hbYbtOA3t4lEXkzYP8gcF+kMiF1JDQkbcuvbPg2JqcrHJWsNj9ouVJEzRGlbHxwjBAP0JZvBS8mrIQdqxKr4/1llwVKDeviHnUKNi1QgNWdUh27jRWbhrCacQA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294720639687.7733450208018; Mon, 27 Apr 2026 05:58:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLV2-0002IS-G5; Mon, 27 Apr 2026 08:55:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0008BM-R6 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNw-0005j4-JP for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:28 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-488af9fdaa7so60562415e9.1 for ; Mon, 27 Apr 2026 05:48:21 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-5-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 72051443d5..63c8e66ea9 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -367,12 +367,21 @@ static inline uint32_t syn_sve_access_trap(void) } =20 /* + * ISS encoding for an exception from an ERET, ERETAA or ERETAB + * instructions. + * * eret_op is bits [1:0] of the ERET instruction, so: * 0 for ERET, 2 for ERETAA, 3 for ERETAB. */ +FIELD(ERET_ISS, OP, 0, 2) + static inline uint32_t syn_erettrap(int eret_op) { - return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; + uint32_t res =3D syn_set_ec(0, EC_ERETTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, ERET_ISS, OP, eret_op); + + return res; } =20 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294678; cv=none; d=zohomail.com; s=zohoarc; b=GLyZfMZX2j1f3hRI08s1wRaxa/Q0BiJJvHhEZqTXN3rJXe47yStl22pmbBRNrJhit1Xliv2hVtwXwDx4FhWA2JtBBPmpz/wLnpp/dgF+BsYXpyIwtGz+qriBVazZNCspHi/X2TI8VmwE4malE3HLFjU0Y8EO+D4VzfO0O4Uf9+Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294678; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=VsXVphtTzSqGkb8cuK6ICBOoamz39qRjTqSYcGiqm6A=; b=M60np2edqYMF9Rxad7+HGSMy7TOP46UEzu4+/NXTSrQGXv0eqLiQasVbl6QBZ8qVn6imh32VyM+9ALz3ThlicXoNuasCJQkcyjfx62zXvL6CAahUoJC+qp5YxlQhm56MZdHdCADgMR4rJtGF9M6cxcO/nbM714Azrl8RQcFwV68= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294678133200.1743030492289; Mon, 27 Apr 2026 05:57:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLR2-0003CC-QO; Mon, 27 Apr 2026 08:51:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0008BH-On for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNw-0005jE-IV for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:26 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-48a563e4ef7so68793535e9.0 for ; Mon, 27 Apr 2026 05:48:22 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294101; x=1777898901; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VsXVphtTzSqGkb8cuK6ICBOoamz39qRjTqSYcGiqm6A=; b=SYG5U5k4pY9wGpZmn6x6ZXvJzx8coEVFEt5yGogMPUv7LVXzL1jO89usvNj1nyRA3P fYaE/VgtkjQqbeU6c0v2Ns3HaVlKZgMa0po/gS24KE//GYXNilwrKMiqaLnRVPWfwm/f zSNe1g7zGX5/ZFV4kPzpZh/TNYntbIjw0ZCHJl+yTyk04/HetmOBkPV35B31vkHuGco/ ezRBQwkr9AdeFEobDVACPFki1dpMUg1/yU2xU0ZWEnQQEDceAF10wFDQPfDVrYgoyf1f TEZvCD52S39ZIr7RzAyNrpHYVaD4yUQDpo/V8ddku1JNa9zbl21SK48VoBMQfH5BrcS7 wScQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294101; x=1777898901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=VsXVphtTzSqGkb8cuK6ICBOoamz39qRjTqSYcGiqm6A=; b=e0woX6HSMwm8fAl4l1T9+zpBmLTDjEv83j9ogECeyPnr+5S4evHAL2vAlyfXKEYj6y OHCD5lx0AP9bB2fM86VoWhOa2kRMBJfqVtLD0EC8V6qVL+1vkEYAZDPKeA4W9+1FsZBx whm8gg7FIYWUFNE6B9VReLbg++qGYcOJyH2WCTPpvYzKv97NFmIY4x5BTeLjdJOeGNmZ iDO5dEK7JVRjDI/wyRPqQNBq6lP/KtBjtrgg65NB8+8j8Su0OdF7QKFEMgm5iLDL7eST a0rk7G7l/QBNSuA0m/8wHYE2B9sb/kQOr0tfDUUP01cVwLHKdbmjWsZ608oLpjhhiI07 XDWg== X-Gm-Message-State: AOJu0YwMqdRZmfP7tXe/T14eV56lvEf+2z+cIDXanOCUvrbVBED+Ecv7 2qdytX29PrrcrjwPJGpNw2gv71Kd8uPqDtjwHdyinR4YFqMLg6Sy/iVPMdYBQ/rpsLic2v1ntLZ G9m2c X-Gm-Gg: AeBDietKVlVFnfuYf1zaNDe3aEF07/xKpzucI1x19dd674SARqQrDgljRZl9GH/aYtM 9S58dq4YixgAvc8pL4IzL6+gHywUlbCb40sfF4XZl3FHg4JV1Qu2z1I35uqL81KsfMa2/l69oa6 jk2FwRlYHn443qN6xc85xadXf2ui8Ie9xMMHtgPUQ3W10rBvAJh9wYvuiHEEFF52pzVhMxn3H7V +zLOONm7kDGMapI3JMSxB71kdjqOhJSLXa3vjB9dZ2VsLSb8WaehAFGCasbxskL/WOfCJ0pHlHr YOdxmycekG7hT4l0zUHw4m4GTF+7qdPhxqDirM8zcTyf9c0IQDmw4EPWDVjyHB3lp8uz3Qjf2t1 bSD6618cvjkuHys2ftk81rZxy6B1j4MjQj5GZv2k94i/pR9sCwqROHJr5I8SKDZYb/yVsGcadXA Nbngt1FcigdSAp5T9UlZSZDhjHJEsDVYUI6FhqMB+uQKYouWuQGY2ui4t0nNThlBgMBnislJbCf ec7CCVNkRnve1JhdgD8xVGBhxPlNVg/Pcr5emfl2A== X-Received: by 2002:a05:600c:8b84:b0:480:1c69:9d36 with SMTP id 5b1f17b1804b1-488fb76e4aamr663834355e9.17.1777294101056; Mon, 27 Apr 2026 05:48:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/63] target/arm: migrate SME trap syndromes to registerfields Date: Mon, 27 Apr 2026 13:47:19 +0100 Message-ID: <20260427124738.966578-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294679141154100 From: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-6-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 63c8e66ea9..6105347598 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -384,10 +384,18 @@ static inline uint32_t syn_erettrap(int eret_op) return res; } =20 +/* + * ISS encoding for an exception due to SME functionality + */ +FIELD(SME_ISS, SMTC, 0, 2) + static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) { - return (EC_SMETRAP << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) | etype; + uint32_t res =3D syn_set_ec(0, EC_SMETRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + res =3D FIELD_DP32(res, SME_ISS, SMTC, etype); + + return res; } =20 static inline uint32_t syn_pacfail(bool data, int keynumber) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294561; cv=none; d=zohomail.com; s=zohoarc; b=UH/xnuIHFvd0ubhpzfPFM8Ouh2J8SmUf4DmN/f16Fcz1aEwg1QKf9vPJqOKc/nMhrlbyu8RfTeHYPRD58kLZaOnt2lJf9MTjuwqUowJedxh18dR8CGffVIaZ1rFDush/x2WNwYPqcLU5DOsdfuBIji/JI0SGXiWjCkRTopTutGE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294561; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rTgagNZc5+/mV+3XbzfZwoEUH7aZwakCX4wYssDEI18=; b=ddvj8kdNSipBbW2q0SjU/Z/zK80DzDobm4pY9GN0zpvnVo5DMKzC3f+TML+bQ6uwFsQHqs0rkiQzJccgocmiq8r8kNWsIjnD8oTVzGdbSPr5Y7x4+aXz76HLBKumtNVt2OXGAxBm4WUYdcumoyjMwoFcFgrESPiIqAD5rmdA7HI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294561107352.36429953663037; Mon, 27 Apr 2026 05:56:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLR1-000321-QJ; Mon, 27 Apr 2026 08:51:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0008BI-Os for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNw-0005jU-Iu for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:27 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so172752535e9.2 for ; Mon, 27 Apr 2026 05:48:23 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-7-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 6105347598..fd8639d4f0 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -398,15 +398,32 @@ static inline uint32_t syn_smetrap(SMEExceptionType e= type, bool is_16bit) return res; } =20 +/* + * ISS encoding for a PAC Fail exceptions + */ +FIELD(PACFAIL_ISS, BnA, 0, 1) /* B key or A key */ +FIELD(PACFAIL_ISS, DnI, 1, 1) /* Data or Instruction */ + static inline uint32_t syn_pacfail(bool data, int keynumber) { - int error_code =3D (data << 1) | keynumber; - return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code; + uint32_t res =3D syn_set_ec(0, EC_PACFAIL); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, PACFAIL_ISS, DnI, data); + res =3D FIELD_DP32(res, PACFAIL_ISS, BnA, keynumber); + + return res; } =20 +/* + * ISS encoding for an exception from a trapped Pointer + * Authentication instruction is RES0 + */ static inline uint32_t syn_pactrap(void) { - return (EC_PACTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL; + uint32_t res =3D syn_set_ec(0, EC_PACTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + return res; } =20 static inline uint32_t syn_btitrap(int btype) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294518; cv=none; d=zohomail.com; s=zohoarc; b=jwtHo8WcBhNSAbAHgn7D4XCVTcHn9GLs4bAvQrtVcq3In6fZQuH1VnCVlM36lhdrN4sjl6EwTSZqnTEUbdrsw3CaQjtSdk/OpR5gaIXZNhYnpSuyEhzV+aJLaDum223fUD4AJYGdpIXp/NoJz41wY8/PFNXiY2B6AWWPQPkIiHc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294518; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=NoxPWYjE0P+COs6BRPCbb0INkdJMc1oijSaje5EH4RU=; b=cZaEIYGKgHwW/ghrAuPaMAZcbzMfOM2vZJERNgZxeZLYLbk+Ms2DTSzgMn9Z0RcHEhQh5aLdcnNjfUQjExrgoU4EqOIr1z+XkzqFqvZzKVy7B16LGrQMGqPyVv5vbu65Fnl/JdeUm8OkRAwmD5+QMSST4HDEbFERBcKKZx7xV+o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294518488748.6529086323246; Mon, 27 Apr 2026 05:55:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUT-0007ZS-9R; Mon, 27 Apr 2026 08:55:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0008BL-QY for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNw-0005jc-Jr for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:28 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-488a9033b2cso109082875e9.2 for ; Mon, 27 Apr 2026 05:48:23 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:48:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/63] target/arm: migrate BTI trap syndromes to registerfields Date: Mon, 27 Apr 2026 13:47:21 +0100 Message-ID: <20260427124738.966578-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294518758158500 From: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-8-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index fd8639d4f0..52a6745cb2 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -426,9 +426,18 @@ static inline uint32_t syn_pactrap(void) return res; } =20 +/* + * ISS encoding for an exception from a Branch Target Identification + * instruction. + */ +FIELD(BTI_ISS, BTYPE, 0, 2) + static inline uint32_t syn_btitrap(int btype) { - return (EC_BTITRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | btype; + uint32_t res =3D syn_set_ec(0, EC_BTITRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, BTI_ISS, BTYPE, btype); + return res; } =20 static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294918; cv=none; d=zohomail.com; s=zohoarc; b=S3wIc3Lkt8nssT3q+C+RuFNdAGQlM0OT9ywxHVVOp3xS79WVf0livC7OwOMkEcvXcifxT9Q1MrM9PvqUNonH7q3vHowbRwhkaLq/tBonDQ16EbhTTQ+CkRvqbdTJKnYUYWYM3QhTZBulxm2s82F80trVupnQ51qai9qhYrkX/ZQ= ARC-Message-Signature: i=1; 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-9-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 52a6745cb2..6fcf0ac757 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -440,10 +440,26 @@ static inline uint32_t syn_btitrap(int btype) return res; } =20 +/* + * ISS encoding for trapped BXJ execution + * + * This is an Armv7 encoding. + */ +FIELD(BXJ_ISS, RM, 0, 4) +/* bits 4:19 are Reserved, UNK/SBZP */ +FIELD(BXJ_ISS, COND, 20, 4) +FIELD(BXJ_ISS, CV, 24, 1) + static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) { - return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | - (cv << 24) | (cond << 20) | rm; + uint32_t res =3D syn_set_ec(0, EC_BXJTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, BXJ_ISS, CV, cv); + res =3D FIELD_DP32(res, BXJ_ISS, COND, cond); + res =3D FIELD_DP32(res, BXJ_ISS, RM, rm); + + return res; } =20 static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr, --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294712; cv=none; d=zohomail.com; s=zohoarc; b=BjKSCqwkmtkRB+y3rlBm3K6PGqoNv28gcfyW1wEtYh6ncxFvxZct5m2FNIJcSpIVPpqDtNNMP6V2qR1K34GqLoJAmFit+dr9IMhnFxFZ9BFld3n3AHsj1feWIb1jwk73CHvLzldR2zG6aC/bk5CGHE0xLgQ4HmqveYXUmj9S8UQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294712; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4VCNxcfPSepY5zbr/MmlLHQMN69/N0gZhxZj3FQ2tKs=; b=kp4Wx00CKWmRf042yz9U/eCetz8OJ3QjSPVniE+M0V7MjtsdqrSHhcx5DO1RgsT7oO7lSA/BN9Len9aXughilFdLCWpOPWIynDYr88ENQIegzEtryJ6aCUKW5Ltse+4JmqVjHMgL4bGY/8xEo00J5olqo/0bg2OdCR9C6E8xu68= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294712882962.4270010342127; Mon, 27 Apr 2026 05:58:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLW8-0003NP-Da; Mon, 27 Apr 2026 08:56:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0008BP-TA for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLNy-0005kQ-PW for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:31 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4891e5b9c1fso86375545e9.2 for ; Mon, 27 Apr 2026 05:48:25 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:48:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/63] target/arm: migrate Granule Protection traps to registerfields Date: Mon, 27 Apr 2026 13:47:23 +0100 Message-ID: <20260427124738.966578-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294713868158500 From: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-10-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 6fcf0ac757..bc65106c61 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -462,12 +462,36 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, = int rm) return res; } =20 +/* + * ISS encoding for a Granule Protection Check exception + * + * These are only reported to EL3 + */ +FIELD(GPC_ISS, xFSC, 0, 6) +FIELD(GPC_ISS, WnR, 6, 1) /* Write not Read */ +FIELD(GPC_ISS, S1PTW, 7, 1) +FIELD(GPC_ISS, CM, 8, 1) +FIELD(GPC_ISS, VNCR, 13, 1) +FIELD(GPC_ISS, GPCSC, 14, 6) +FIELD(GPC_ISS, InD, 20, 1) /* Instruction not Data access */ +FIELD(GPC_ISS, S2PTW, 21, 1) + static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, int vncr, int cm, int s1ptw, int wnr, int fsc) { - return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) - | (ind << 20) | (gpcsc << 14) | (vncr << 13) | (cm << 8) - | (s1ptw << 7) | (wnr << 6) | fsc; + uint32_t res =3D syn_set_ec(0, EC_GPC); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, GPC_ISS, S2PTW, s2ptw); + res =3D FIELD_DP32(res, GPC_ISS, InD, ind); + res =3D FIELD_DP32(res, GPC_ISS, GPCSC, gpcsc); + res =3D FIELD_DP32(res, GPC_ISS, VNCR, vncr); + res =3D FIELD_DP32(res, GPC_ISS, CM, cm); + res =3D FIELD_DP32(res, GPC_ISS, S1PTW, s1ptw); + res =3D FIELD_DP32(res, GPC_ISS, WnR, wnr); + res =3D FIELD_DP32(res, GPC_ISS, xFSC, fsc); + + return res; } =20 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294648; cv=none; d=zohomail.com; s=zohoarc; b=KokIcQ0GQgyVxf6xEwSXfHVCMHpTwaXfjPqfNRu2CCMTuvukuP0qNEy9V4p7zZkIcP81jjOgCIRrUK587TMuVpBofYw2qqeGfK+yLkuiXM1eLRwtBcGJx0Z4gH0C5WhSuQT0k09QsvSVjpV4/pFyUN9CClyZumalC1OvF6FXfKk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294648; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260422125250.1303100-11-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 87 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 74 insertions(+), 13 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index bc65106c61..2031b3704f 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -494,20 +494,64 @@ static inline uint32_t syn_gpc(int s2ptw, int ind, in= t gpcsc, int vncr, return res; } =20 +/* + * ISS encoding for an exception from an Instruction Abort + * + * (aka instruction abort) + */ +FIELD(IABORT_ISS, IFSC, 0, 6) +FIELD(IABORT_ISS, S1PTW, 7, 1) +FIELD(IABORT_ISS, EA, 9, 1) +FIELD(IABORT_ISS, FnV, 10, 1) /* FAR not Valid */ +FIELD(IABORT_ISS, SET, 11, 2) +FIELD(IABORT_ISS, PFV, 14, 1) +FIELD(IABORT_ISS, TopLevel, 21, 1) /* FEAT_THE */ + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { - return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; + uint32_t res =3D syn_set_ec(0, EC_INSNABORT + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, IABORT_ISS, EA, ea); + res =3D FIELD_DP32(res, IABORT_ISS, S1PTW, s1ptw); + res =3D FIELD_DP32(res, IABORT_ISS, IFSC, fsc); + + return res; } =20 +/* + * ISS encoding for an exception from a Data Abort + */ +FIELD(DABORT_ISS, DFSC, 0, 6) +FIELD(DABORT_ISS, WNR, 6, 1) +FIELD(DABORT_ISS, S1PTW, 7, 1) +FIELD(DABORT_ISS, CM, 8, 1) +FIELD(DABORT_ISS, EA, 9, 1) +FIELD(DABORT_ISS, FnV, 10, 1) +FIELD(DABORT_ISS, LST, 11, 2) +FIELD(DABORT_ISS, VNCR, 13, 1) +FIELD(DABORT_ISS, AR, 14, 1) +FIELD(DABORT_ISS, SF, 15, 1) +FIELD(DABORT_ISS, SRT, 16, 5) +FIELD(DABORT_ISS, SSE, 21, 1) +FIELD(DABORT_ISS, SAS, 22, 2) +FIELD(DABORT_ISS, ISV, 24, 1) + static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv, int ea, int cm, int s1ptw, int wnr, int fsc) { - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | ARM_EL_IL - | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7) - | (wnr << 6) | fsc; + uint32_t res =3D syn_set_ec(0, EC_DATAABORT + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, DABORT_ISS, FnV, fnv); + res =3D FIELD_DP32(res, DABORT_ISS, EA, ea); + res =3D FIELD_DP32(res, DABORT_ISS, CM, cm); + res =3D FIELD_DP32(res, DABORT_ISS, S1PTW, s1ptw); + res =3D FIELD_DP32(res, DABORT_ISS, WNR, wnr); + res =3D FIELD_DP32(res, DABORT_ISS, DFSC, fsc); + + return res; } =20 static inline uint32_t syn_data_abort_with_iss(int same_el, @@ -517,11 +561,22 @@ static inline uint32_t syn_data_abort_with_iss(int sa= me_el, int wnr, int fsc, bool is_16bit) { - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) - | (is_16bit ? 0 : ARM_EL_IL) - | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) - | (sf << 15) | (ar << 14) - | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; + uint32_t res =3D syn_set_ec(0, EC_DATAABORT + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, DABORT_ISS, ISV, 1); + res =3D FIELD_DP32(res, DABORT_ISS, SAS, sas); + res =3D FIELD_DP32(res, DABORT_ISS, SSE, sse); + res =3D FIELD_DP32(res, DABORT_ISS, SRT, srt); + res =3D FIELD_DP32(res, DABORT_ISS, SF, sf); + res =3D FIELD_DP32(res, DABORT_ISS, AR, ar); + res =3D FIELD_DP32(res, DABORT_ISS, EA, ea); + res =3D FIELD_DP32(res, DABORT_ISS, CM, cm); + res =3D FIELD_DP32(res, DABORT_ISS, S1PTW, s1ptw); + res =3D FIELD_DP32(res, DABORT_ISS, WNR, wnr); + res =3D FIELD_DP32(res, DABORT_ISS, DFSC, fsc); + + return res; } =20 /* @@ -530,8 +585,14 @@ static inline uint32_t syn_data_abort_with_iss(int sam= e_el, */ static inline uint32_t syn_data_abort_vncr(int ea, int wnr, int fsc) { - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (1 << ARM_EL_EC_SHIFT) - | ARM_EL_IL | ARM_EL_VNCR | (wnr << 6) | fsc; + uint32_t res =3D syn_set_ec(0, EC_DATAABORT_SAME_EL); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, DABORT_ISS, VNCR, 1); + res =3D FIELD_DP32(res, DABORT_ISS, WNR, wnr); + res =3D FIELD_DP32(res, DABORT_ISS, DFSC, fsc); + + return res; } =20 static inline uint32_t syn_swstep(int same_el, int isv, int ex) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294296; cv=none; d=zohomail.com; s=zohoarc; b=esQ8fzTTYAzC9yYhtfsC6yddazKX01vLdEUT1tk7vdd9mCBibQ/mLnMLxyuYEhTQ9/+0BOMsNH7+M4Hejm+8ucu0U89sw1HZ8uV+ej3RtasN8YHrwoZGosnWEv7IiSNfzQgIdtWB2twjiIRzZjzpsvf9IFRfljPMYUYQc67yMEs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294296; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=mOoSY+iuv6Itz71wlhRRL9GhUQ6RnDF/CADilvxqJcA=; b=Umjrgrkg2xY3nC/IMOClnVjkL2B85NX7OrDoqJARfupxCg2gaZAnZVIRMbUOeizVFU94CbZSTmDXHluD4/S3pS4Qt1zVVBBtf4HqmULpShFkocQj6GRPlanwfEQwOxkrFZr4bdfjiB7z8OeHuY7P1NUuzuQ2hD8QKMdgfUkujOo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177729429611131.5025473706429; Mon, 27 Apr 2026 05:51:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLQD-0002Bz-Hm; Mon, 27 Apr 2026 08:50:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO7-0008D8-PY for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:36 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0005ku-HT for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so172754555e9.2 for ; Mon, 27 Apr 2026 05:48:27 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-12-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 54 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 6 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 2031b3704f..2ad6b97aea 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -595,22 +595,64 @@ static inline uint32_t syn_data_abort_vncr(int ea, in= t wnr, int fsc) return res; } =20 +/* + * ISS encoding for an exception from a Software Step exception. + */ +FIELD(SOFTSTEP_ISS, IFSC, 0, 6) +FIELD(SOFTSTEP_ISS, EX, 6, 1) +FIELD(SOFTSTEP_ISS, ISV, 24, 1) + static inline uint32_t syn_swstep(int same_el, int isv, int ex) { - return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SH= IFT) - | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; + uint32_t res =3D syn_set_ec(0, EC_SOFTWARESTEP + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, SOFTSTEP_ISS, ISV, isv); + res =3D FIELD_DP32(res, SOFTSTEP_ISS, EX, ex); + res =3D FIELD_DP32(res, SOFTSTEP_ISS, IFSC, 0x22); + + return res; } =20 +/* + * ISS encoding for an exception from a Watchpoint exception + */ +FIELD(WATCHPOINT_ISS, DFSC, 0, 6) +FIELD(WATCHPOINT_ISS, WNR, 6, 1) +FIELD(WATCHPOINT_ISS, CM, 8, 1) +FIELD(WATCHPOINT_ISS, FnV, 10, 1) +FIELD(WATCHPOINT_ISS, VNCR, 13, 1) /* FEAT_NV2 */ +FIELD(WATCHPOINT_ISS, FnP, 15, 1) +FIELD(WATCHPOINT_ISS, WPF, 16, 1) +/* bellow mandatory from FEAT_Debugv8p9 */ +FIELD(WATCHPOINT_ISS, WPTV, 17, 1) /* FEAT_Debugv8p2 - WPT valid */ +FIELD(WATCHPOINT_ISS, WPT, 18, 6) /* FEAT_Debugv8p2 - missing WP number */ + static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) { - return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) - | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; + uint32_t res =3D syn_set_ec(0, EC_WATCHPOINT + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, WATCHPOINT_ISS, CM, cm); + res =3D FIELD_DP32(res, WATCHPOINT_ISS, WNR, wnr); + res =3D FIELD_DP32(res, WATCHPOINT_ISS, DFSC, 0x22); + + return res; } =20 +/* + * ISS encoding for an exception from a Breakpoint or a Vector Catch + * debug exception. + */ +FIELD(BREAKPOINT_ISS, IFSC, 0, 6) + static inline uint32_t syn_breakpoint(int same_el) { - return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIF= T) - | ARM_EL_IL | 0x22; + uint32_t res =3D syn_set_ec(0, EC_BREAKPOINT + same_el); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + res =3D FIELD_DP32(res, BREAKPOINT_ISS, IFSC, 0x22); + + return res; } =20 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-13-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 2ad6b97aea..65d0de63a8 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -655,11 +655,25 @@ static inline uint32_t syn_breakpoint(int same_el) return res; } =20 +/* + * ISS encoding for an exception from a WF* instruction + */ +FIELD(WFX_ISS, TI, 0, 2) +FIELD(WFX_ISS, RV, 2, 1) +FIELD(WFX_ISS, RN, 5, 5) +FIELD(WFX_ISS, COND, 20, 4) +FIELD(WFX_ISS, CV, 24, 1) + static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) { - return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | - (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | - (cv << 24) | (cond << 20) | ti; + uint32_t res =3D syn_set_ec(0, EC_WFX_TRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); + + res =3D FIELD_DP32(res, WFX_ISS, CV, cv); + res =3D FIELD_DP32(res, WFX_ISS, COND, cond); + res =3D FIELD_DP32(res, WFX_ISS, TI, ti); + + return res; } =20 static inline uint32_t syn_illegalstate(void) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294889; cv=none; d=zohomail.com; s=zohoarc; b=fJaUK5PxYg0suLvYi9I8QxKFS4LHD1m5VyX2ZqNjuZWL+jxmAOnBsZHGUcLGO37ZVQbUTebScmF3mEBqi/MXGxA1vPXzjFRh6b6CKEX6VvHoQHUi4BsRxZwA7QRCF1OR2cmlD5oJLGZUtuMPCvU8LjEm/upROkUTCvf9xyiJaOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294889; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Iut+4BJW06xHtE0SB3YNoS1Ssi4OQgnXbFlPQro7fSE=; b=hDtrfoxP17Bbm6zueWZdwZmrwY8XoDeYfiCg+qQc6aR8w4HOmkQ1Ad2WWheEtQ9jaTQPr9WQYsEaz9ovE0CpgohSvYhbeTvzkpgxZI5TLXzMp8wvYfD8Fq7FOa9PNtxLB3vUXxP40QKgs9mvndZnXShhzdx42ke6XFabTYhmjio= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294889613413.7197519791798; Mon, 27 Apr 2026 06:01:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLW0-00038t-8r; Mon, 27 Apr 2026 08:56:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO7-0008D5-P8 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:36 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0005lD-IQ for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-488b8bc6bc9so73666275e9.3 for ; Mon, 27 Apr 2026 05:48:28 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-14-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 39 +++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 65d0de63a8..7ff8c30e2b 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -690,21 +690,48 @@ static inline uint32_t syn_pcalignment(void) return res; } =20 +/* + * ISS encoding for a GCS exception + * + * Field validity depends on EXTYPE + */ +FIELD(GCS_ISS, IT, 0, 5) +FIELD(GCS_ISS, RN, 5, 5) /* only for non EXLOCK exceptions */ +FIELD(GCS_ISS, RADDR, 10, 5) /* only for GCSSTR/GCSSTTR traps */ +FIELD(GCS_ISS, EXTYPE, 20, 4) + static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn) { - return ((EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL | - (GCS_ET_DataCheck << 20) | (rn << 5) | it); + uint32_t res =3D syn_set_ec(0, EC_GCS); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_DataCheck); + res =3D FIELD_DP32(res, GCS_ISS, RN, rn); + res =3D FIELD_DP32(res, GCS_ISS, IT, it); + + return res; } =20 static inline uint32_t syn_gcs_exlock(void) { - return (EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL | (GCS_ET_EXLOCK << 20); + uint32_t res =3D syn_set_ec(0, EC_GCS); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_EXLOCK); + + return res; } =20 -static inline uint32_t syn_gcs_gcsstr(int ra, int rn) +static inline uint32_t syn_gcs_gcsstr(int raddr, int rn) { - return ((EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL | - (GCS_ET_GCSSTR_GCSSTTR << 20) | (ra << 10) | (rn << 5)); + uint32_t res =3D syn_set_ec(0, EC_GCS); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, GCS_ISS, EXTYPE, GCS_ET_GCSSTR_GCSSTTR); + res =3D FIELD_DP32(res, GCS_ISS, RADDR, raddr); + res =3D FIELD_DP32(res, GCS_ISS, RN, rn); + + return res; } =20 static inline uint32_t syn_serror(uint32_t extra) --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294401; cv=none; d=zohomail.com; s=zohoarc; b=TGrkX/oVVGswBNe5yY8g31T7NfaF8u69OAlyE+ErFxTAfC9mjt42+VAQ6OQFT7Hz1S+zIq9HLof0hOX3vgCbjkYabYn2jbIzZad/xnSSbTToL4OvLdjwaM3DAw4t6kFO2ZDoAlfssgmJzA2QQGoe1FKZVw1F6UM1OdRIR9OlpLQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294401; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=9y4m/iMelPf9i9IEtiQcavxusS+opbaUucMeNQfMLfc=; b=Hs7vb9DfrppnJBJ3P5vUzMfCq6+krIi/ApIKf7UudFX6vMS908x/8aj42D39C48/D/BJhlAScjMSdofabuLxMHoQ40mZ6y+V1Wb2+FJWA9YsIeyeDD88+3gmyZInGI/hCQeSMPY6eIAo5pBIiR4jFeY+BRjWNXW2YIUu+EnU0TQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294401877229.23717960155705; Mon, 27 Apr 2026 05:53:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLRQ-0003qa-8x; Mon, 27 Apr 2026 08:52:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO7-0008D6-P2 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:36 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0005lJ-Ie for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4891f625344so91592505e9.0 for ; Mon, 27 Apr 2026 05:48:29 -0700 (PDT) Received: from lanath.. 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Mon, 27 Apr 2026 05:48:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 54/63] target/arm: migrate memory op syndromes to registerfields Date: Mon, 27 Apr 2026 13:47:28 +0100 Message-ID: <20260427124738.966578-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294402302158500 From: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-15-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 7ff8c30e2b..841fd3292b 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -742,14 +742,39 @@ static inline uint32_t syn_serror(uint32_t extra) return res; } =20 +/* + * ISS encoding for an exception from the Memory Copy and Memory Set + * instructions. + */ +FIELD(MOP_ISS, SIZEREG, 0, 5) +FIELD(MOP_ISS, SRCREG, 5, 5) +FIELD(MOP_ISS, DESTREG, 10, 5) +FIELD(MOP_ISS, FORMATOPT, 16, 2) +FIELD(MOP_ISS, OPT_A, 16, 1) +FIELD(MOP_ISS, WRONG_OPT, 17, 1) +FIELD(MOP_ISS, EPILOGUE, 18, 1) +FIELD(MOP_ISS, OPTIONS, 19, 4) +FIELD(MOP_ISS, IS_SETG, 23, 1) +FIELD(MOP_ISS, MEMINST, 24, 1) + static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, bool epilogue, bool wrong_option, bool opti= on_a, int destreg, int srcreg, int sizereg) { - return (EC_MOP << ARM_EL_EC_SHIFT) | ARM_EL_IL | - (is_set << 24) | (is_setg << 23) | (options << 19) | - (epilogue << 18) | (wrong_option << 17) | (option_a << 16) | - (destreg << 10) | (srcreg << 5) | sizereg; + uint32_t res =3D syn_set_ec(0, EC_MOP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, MOP_ISS, MEMINST, is_set); + res =3D FIELD_DP32(res, MOP_ISS, IS_SETG, is_setg); + res =3D FIELD_DP32(res, MOP_ISS, OPTIONS, options); + res =3D FIELD_DP32(res, MOP_ISS, EPILOGUE, epilogue); + res =3D FIELD_DP32(res, MOP_ISS, WRONG_OPT, wrong_option); + res =3D FIELD_DP32(res, MOP_ISS, OPT_A, option_a); + res =3D FIELD_DP32(res, MOP_ISS, DESTREG, destreg); + res =3D FIELD_DP32(res, MOP_ISS, SRCREG, srcreg); + res =3D FIELD_DP32(res, MOP_ISS, SIZEREG, sizereg); + + return res; } =20 =20 --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294711; cv=none; d=zohomail.com; s=zohoarc; b=HLkbmnzGCQo5vcDSagh18vi25N3Xk7T7k6BFn5RnQXTZWgkHjxnLulP5x9CaIaThlqMGCXUg9lTe1KBG5u39Y43PHfT4zBuow8kJBbXEhjRdXjyJzJfUeT51fEVTDnOUf90OkC6dyJinKdcuxbkvzJhD+Rhh20qjuP11oawbw0g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-16-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 16 ++++++++++++++++ target/arm/tcg/vfp_helper.c | 5 +---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 841fd3292b..53137394e2 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -251,6 +251,22 @@ FIELD(COPROC_ISS, OP2, 17, 3) FIELD(COPROC_ISS, COND, 20, 4) FIELD(COPROC_ISS, CV, 24, 1) =20 +static inline uint32_t syn_cp10_rt_trap(int cv, int cond, int opc1, + int crn, int rt, int isread) +{ + uint32_t res =3D syn_set_ec(0, EC_FPIDTRAP); + res =3D FIELD_DP32(res, SYNDROME, IL, 1); + + res =3D FIELD_DP32(res, COPROC_ISS, CV, cv); + res =3D FIELD_DP32(res, COPROC_ISS, COND, cond); + res =3D FIELD_DP32(res, COPROC_ISS, OP1, opc1); + res =3D FIELD_DP32(res, COPROC_ISS, CRN, crn); + res =3D FIELD_DP32(res, COPROC_ISS, RT, rt); + res =3D FIELD_DP32(res, COPROC_ISS, ISREAD, isread); + + return res; +} + static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int op= c2, int crn, int crm, int rt, int isre= ad, bool is_16bit) diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index 45f2eb0930..e692bc568b 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -1359,10 +1359,7 @@ void HELPER(check_hcr_el2_trap)(CPUARMState *env, ui= nt32_t rt, uint32_t reg) g_assert_not_reached(); } =20 - syndrome =3D ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) - | ARM_EL_IL - | (1 << 24) | (0xe << 20) | (7 << 14) - | (reg << 10) | (rt << 5) | 1); + syndrome =3D syn_cp10_rt_trap(1, 0xe, 7, reg, rt, 1); =20 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); } --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294649; cv=none; d=zohomail.com; s=zohoarc; b=MaRWlnnid1jAbUXKH8yh76oA+Q4MwYaap2Gu24Dlid2eIyHTbp7T/UdcVt32zJ/V6+c4zteD3kCDm2CX34lmzuE86VDwFVCiNeZGfJi+AQoB2BMRxTbKcI3/oJjpWAnn9t9t/ZKvu8UH94HIDzsBlQSDL4Q5TxMGIrS01JcHYd0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294649; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=0a1Ls59o9nhOOy82JK/fcbf0nGoU5bJBXvtu1cJOEwE=; b=jUAjmeIUMaM/fw3qNYHzZ0hfI8pQH9qhrAAPhPrrrnUm+UubFgLUzM2hcHUQKTOwcf6HyLv2Jt5f7A4PKqoOZJn7Cu3KTMIIXIWLesNpUTMw70ZZqJ4aM7s9BANwOaBJ7PUcjyhdlFXoykG1dGmtFcBKwNtRCRJ3OXTqmpoYl1c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294649630871.0705538377962; Mon, 27 Apr 2026 05:57:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUd-00008q-GB; Mon, 27 Apr 2026 08:55:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO7-0008D4-Ow for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:36 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO4-0005lb-RW for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:35 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so172756035e9.2 for ; Mon, 27 Apr 2026 05:48:31 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-17-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ccd6353190..7e7677a584 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8844,9 +8844,9 @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState= *cs) */ if (cs->exception_index =3D=3D EXCP_PREFETCH_ABORT || (cs->exception_index =3D=3D EXCP_DATA_ABORT && - !(env->exception.syndrome & ARM_EL_ISV)) || + !FIELD_EX32(env->exception.syndrome, SYNDROME, IL)) || syn_get_ec(env->exception.syndrome) =3D=3D EC_UNCATEGORIZE= D) { - env->exception.syndrome &=3D ~ARM_EL_IL; + env->exception.syndrome =3D FIELD_DP32(env->exception.synd= rome, SYNDROME, IL, 0); } } env->cp15.esr_el[2] =3D env->exception.syndrome; --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294889; cv=none; d=zohomail.com; s=zohoarc; b=RgG+CzHXYqE+CNoH1UQL9psQyc2CbZwnWAVc4TcURHMoCxwvBSYUtaHJhphHkhMobNVICyopR59X82bXO88sF1ZJh//fL3PYvR3Q7Gqu4OQefKCyecBZ/GHb7lakYXt2QTcO8uCMLoLcuAeQPu4KHe5GjDBLqGpsoufeMgOaK3Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294889; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=YDoQbWYjuWr+STze5DrZodJz/uNdiizqomxJ3dlpfIo=; b=c01f40aS4KcI7ggGdHSaLgB/ZUoa+04SwfWrFNdqvBe+nrMom9hBfmwqdr77X6tzpVvBegW1Wvr2itX1q8XcK67EF9u31OHXOLbtiGHx/cz6lgA3hV87PgUf2VY5bMazrNCyyZ24G7AJappDXcEuvzjsXd2QCB4DEHfObB7WovU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294889776243.80294959065247; Mon, 27 Apr 2026 06:01:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUh-0000W4-DL; Mon, 27 Apr 2026 08:55:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO9-0008FM-6Z for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:37 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO6-0005li-BD for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:36 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4891e86fabeso111458725e9.1 for ; Mon, 27 Apr 2026 05:48:32 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488ffc5e3f4sm448974115e9.2.2026.04.27.05.48.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 05:48:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777294112; x=1777898912; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YDoQbWYjuWr+STze5DrZodJz/uNdiizqomxJ3dlpfIo=; b=EnmXoz+n0+qiKrAgQimh2QtejQkE2ROOSINF7uxEX8jYcT43CPh0u3zngtfCMc/Raj qSFvAn2Z0tWX76/9zQn0EXLsu7nB5ZoY9dMbfCo5O3T3XBKAxSZYRHhyFpNb3m5NDkz7 qHcxYfKFkjM591tB9atbBEjW81QaHRocO+sUrX9wSpUsAH8Fgq+bB6yzAcAmaSYiJ9kF tvHlHhBPLOn3AYBORuQOWMg+49Q1c6mxkHdlpcpizyOJT67sAc1867HxGKE48gTa3ghY grBHHWVPHEPZvzlvyOEgjSFTdl6GbUG2dLWklJWYDJDo4/f1oHug6710Q4ilqRqAaHkl 51Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777294112; x=1777898912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=YDoQbWYjuWr+STze5DrZodJz/uNdiizqomxJ3dlpfIo=; b=JXrILhLbTud8pqcVVx+uuLE+pOi4HyVX0pIlAOFSeC/bva9MObHpXvlJRN24XbAUfw NFc8E7Pvx/KPJp0fUJFHrhDJq//6r7ECv34/4Xl92mVaKwk8+6jBf9djCr2z8q1fRvxJ GpkF8h/deFPSNhNXVDXZGMCCvHw+9a6LUQjQhx92Sa85w/ipA3KCKDJuJlNLqFabTWKt CSWf1IZ3UVl6er2y0ILk8f6DiqXVyDocDqV146M6NsV3lHd4QpFFW+XtS5AfUXIp6z3O 9efJb3drmnyr5QnZ0fG8QwDJjyihAzlAuZIxM5iJpynrBnt6P2IGwdsQJX7SVYtZhPqI rs2Q== X-Gm-Message-State: AOJu0YzGuuiNRxQzFyYVI3pP+UEOAAez44PfsZWpkKELfKtUW3/7Tx4M ArGD88gy03yJepFttRy0urtcc3weft163WWYfxKywjO8uILJ/sYSZogi3KVDlfGCS9hCksledzE gjhTZ X-Gm-Gg: AeBDiesqYGp4uq4YCMXD1qnazb2nGkSvgSCAaI1vxlEBroPQdUuwGPNBNOTVFErtnzv AsM+AD6NTpRqoeeIFAspdNLpF8/rU/0AolYv5SltrvzDdAlwo00x+kY08MHTfP9WnvYSSu7ooWn r+yXY4Zter3/bTkyAWMUo0JW8+LqvBohygC/a6kpI2QSVu7TftAuLsOtUMQv7eqqBPjTrwCqY3w lJyU45GaoYlBqxxxo/Rx/7KOddOYuOdrAVf8JojUFdDh//HWG+9WhNI+vXWPj3ZdjSAV+Eum70o a1laLfjw7GucS+H/EM/ZVC1KLFWa3SPTJJPqDLZpfbu0JgdvouJMp6aJde95JUveMsleKt+w3QF GH3Tml7LewJm9bK4PCFNs/xjN7a+2Ktrm3AcdYq6OFv5UuNmLZCZfkOj3mUyBVOKRBOTwQrq4xM 8smvaYVTkQwXjGWKWZOxcWatmrDXakqls+rZMLGqlUp7sjFORVXRdg2cW/MUkwv3cjcvdwMUaEu v4tLNFK8qvTXnsqelzfmic7OUJaW2fBjJB87prKcg== X-Received: by 2002:a05:600c:1f83:b0:488:8840:e5ae with SMTP id 5b1f17b1804b1-488fb787afemr598550145e9.24.1777294111697; Mon, 27 Apr 2026 05:48:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 57/63] target/arm: use syndrome helpers to set SAME_EL EC bit Date: Mon, 27 Apr 2026 13:47:31 +0100 Message-ID: <20260427124738.966578-58-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427124738.966578-1-peter.maydell@linaro.org> References: <20260427124738.966578-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777294891182158500 From: Alex Benn=C3=A9e This removes the last use of ARM_EL_EC_SHIFT. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-18-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 1 - target/arm/tcg/debug.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 53137394e2..d4dfab8cd1 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -107,7 +107,6 @@ typedef enum { } GCSInstructionType; =20 #define ARM_EL_EC_LENGTH 6 -#define ARM_EL_EC_SHIFT 26 #define ARM_EL_IL_SHIFT 25 #define ARM_EL_ISV_SHIFT 24 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 5214e3c08a..07a52643e7 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -56,7 +56,7 @@ raise_exception_debug(CPUARMState *env, uint32_t excp, ui= nt32_t syndrome) * Similarly for watchpoint and breakpoint matches. */ assert(debug_el >=3D cur_el); - syndrome |=3D (debug_el =3D=3D cur_el) << ARM_EL_EC_SHIFT; + syndrome |=3D (debug_el =3D=3D cur_el) << R_SYNDROME_EC_SHIFT; raise_exception(env, excp, syndrome, debug_el); } =20 --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294891; cv=none; d=zohomail.com; s=zohoarc; b=dNJNfI9e5/yyRuFuJf3JsKXJf1Wt7R53K6AAQm11vb66zbD6XHr5ojR70lHqTXrtuhlBL/Om64w6ypJbbPq19bmRLyMdtE7/C1cM3duQjDRpEOIOkj9XQqSX6oVCgETxpLYjOk3tt8jtHqLSrdJ5DsLeF6WETI09LsQhFk0TiKE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294891; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=SNjguSagUUFWrnR8Tu095/iRj+cQaq/6CTCp6Ze1XcY=; b=QRavjVs+gP8iTUW+Naqv67nk8BeWA+i7oKWiOPfY+k5nOL7LC2o71wq/3xwVjw3ougN7zXSFfXlRHAQjP3YZf6pf6DNIpwrqsiegGheMF2vHbJBZB0czm4ug8i1avSgxuMZsxIIj3bNIzqKmStPF1pMifSnquPJoALG8xUFeNn4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294891552973.0213078246007; Mon, 27 Apr 2026 06:01:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUj-0000zU-Bh; Mon, 27 Apr 2026 08:55:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLO9-0008Ez-1m for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:37 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO6-0005mo-BQ for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:36 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-488a88aeec9so127026025e9.2 for ; Mon, 27 Apr 2026 05:48:33 -0700 (PDT) Received: from lanath.. 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While we are at it assert it really is a EC_DATAABORT. Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-19-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/whpx/whpx-all.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index bbf0f6be96..4cfc7f9969 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -356,15 +356,16 @@ static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY= _ACCESS_CONTEXT *ctx) { uint64_t syndrome =3D ctx->Syndrome; =20 - bool isv =3D syndrome & ARM_EL_ISV; - bool iswrite =3D (syndrome >> 6) & 1; - bool sse =3D (syndrome >> 21) & 1; - uint32_t sas =3D (syndrome >> 22) & 3; + bool isv =3D FIELD_EX32(syndrome, DABORT_ISS, ISV); + bool iswrite =3D FIELD_EX32(syndrome, DABORT_ISS, WNR); + bool sse =3D FIELD_EX32(syndrome, DABORT_ISS, SSE); + uint32_t sas =3D FIELD_EX32(syndrome, DABORT_ISS, SAS); uint32_t len =3D 1 << sas; - uint32_t srt =3D (syndrome >> 16) & 0x1f; - uint32_t cm =3D (syndrome >> 8) & 0x1; + uint32_t srt =3D FIELD_EX32(syndrome, DABORT_ISS, SRT); + uint32_t cm =3D FIELD_EX32(syndrome, DABORT_ISS, CM); uint64_t val =3D 0; =20 + assert(syn_get_ec(syndrome) =3D=3D EC_DATAABORT); assert(!cm); assert(isv); =20 --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294752; cv=none; d=zohomail.com; s=zohoarc; b=WWsMdN0vQ93V4k/bKl9pbAKymuZMtuqyS/Pc/XwaCdq51ZhbvI+JtcQhSafmuWuoeN8NBAEnT691b9dIN+Z0ywyWKO9/EaCweLUzZ7QjYNSTj8+rFZ8fX27BIIQiCXJzg0JbO6u4q6Gy103ps18+LPm61YhjJp2qq0A079Muxeo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294752; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2kPC1nSjy09rWvg26KQH5UE7UfFjCOQkaqBSnSpqoXk=; b=SGix0AMleKazmt/rzfzjlCADrj1mboWB77iPPuosvKnUPnXMyb7i853SsCxXh6szFGGHd/YzqMCtjw6w0DGuKAksm/VlBczFoAdFV0Qw7sz9HNIWJiMbXYRtNDy6zaht+zO1fUbO2FSfrzOZ9gFqr6dPTnW8KvTk8p0ddOZyNJU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294752709659.0965626939154; Mon, 27 Apr 2026 05:59:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLU8-0006Kq-1A; Mon, 27 Apr 2026 08:54:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLOA-0008Hh-Km for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:41 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO7-0005n2-HN for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:38 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-488ad135063so93529745e9.0 for ; Mon, 27 Apr 2026 05:48:34 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260422125250.1303100-20-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 678afe5c8e..ef4c3671e9 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2123,14 +2123,14 @@ static int hvf_handle_exception(CPUState *cpu, hv_v= cpu_exit_exception_t *excp) break; } case EC_DATAABORT: { - bool isv =3D syndrome & ARM_EL_ISV; - bool iswrite =3D (syndrome >> 6) & 1; - bool s1ptw =3D (syndrome >> 7) & 1; - bool sse =3D (syndrome >> 21) & 1; - uint32_t sas =3D (syndrome >> 22) & 3; + bool isv =3D FIELD_EX32(syndrome, DABORT_ISS, ISV); + bool iswrite =3D FIELD_EX32(syndrome, DABORT_ISS, WNR); + bool s1ptw =3D FIELD_EX32(syndrome, DABORT_ISS, S1PTW); + bool sse =3D FIELD_EX32(syndrome, DABORT_ISS, SSE); + uint32_t sas =3D FIELD_EX32(syndrome, DABORT_ISS, SAS); uint32_t len =3D 1 << sas; - uint32_t srt =3D (syndrome >> 16) & 0x1f; - uint32_t cm =3D (syndrome >> 8) & 0x1; + uint32_t srt =3D FIELD_EX32(syndrome, DABORT_ISS, SRT); + uint32_t cm =3D FIELD_EX32(syndrome, DABORT_ISS, CM); uint64_t val =3D 0; uint64_t ipa =3D excp->physical_address; AddressSpace *as =3D cpu_get_address_space(cpu, ARMASIdx_NS); --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294735; cv=none; d=zohomail.com; s=zohoarc; b=Quq8xVbD4NucgB72geE1seIeBCQaJGsSNm6rWHQ9C0y6SGGVq2+WlWs/gOsJpnB0KcurppKFtDJAIEroH4Nq+lPam2TtjDGr/b0QALxdaPckNTdkO46i/fS12RMQFEhT3Fqp0DR+xPms3ctZiz67Cn8GAIGeyq1jdhDukAzRckw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294735; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=YYQbiZSahbTQPAFgyLEs1FpETFb2M0uP0kJrECbl7E0=; b=POvsnrVovubjk3wFsDVtuwmPlWXaRxAH9hfAjeXlnA3BA2UeThbpUtUW2mT3iQSRkCBImldte7dFLfDrrM7JmF9hf7N4fJYYKe0Ztder11cvJXgIhxdQlcY/TyJEmYpJQyFzYsdiurjjHZ2V+feaObw1afPSE8unOBj8GVn2ILg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294735952823.1603157684702; Mon, 27 Apr 2026 05:58:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUM-0006wF-AG; Mon, 27 Apr 2026 08:55:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLOA-0008Hg-KO for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:41 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO8-0005nU-Nh for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:38 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4890d945eb4so51142245e9.0 for ; Mon, 27 Apr 2026 05:48:35 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-21-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 565954269f..c74d8e785a 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -56,7 +56,7 @@ static inline uint64_t merge_syn_data_abort(uint32_t temp= late_syn, */ assert(!fi->stage2); syn =3D syn_data_abort_vncr(fi->ea, is_write, fsc); - } else if (!(template_syn & ARM_EL_ISV) || target_el !=3D 2 + } else if (!FIELD_EX32(template_syn, DABORT_ISS, ISV) || target_el != =3D 2 || fi->s1ptw || !fi->stage2) { syn =3D syn_data_abort_no_iss(same_el, 0, fi->ea, 0, fi->s1ptw, is_write, fsc); --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294886; cv=none; d=zohomail.com; s=zohoarc; b=jxZ/i1V7/SiNSi/BVRYp+c33ZNQuHV4qIcL3diIabwfysk0bQGvqw0Jr0jIgMDOSmitGFEJ7AQPHvqlHPpKnfUga1W25EYtGzHCk/rA7N0S/byhFPFr8Plrqm7lv+V5Pz4H+xdDrebgL3IrNTQoiT5Uq3Wb8QG6DUKZvvLD6TSM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294886; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=qx/HoouzfD2bG9m7t08A8JbHrDNgqGRID4fYcDYHUJo=; b=QSO/MVCWhF+0TLWl3+wErbdhIijx00IgPo9ofaBQ8UqJz63tUvPO9i4+11KFNWqURhdCQFT8+04TrrWTx3v520Fj7BE8OB4YfQHkMgkvQCI5PGmgeiNX6Yu5fmE8yNNtK9YA4gzRP9V7kd5kW/cFC0ez8VM7ULABU2mi0R3Q5jE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294886428555.4330760510782; Mon, 27 Apr 2026 06:01:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUV-0007s7-3n; Mon, 27 Apr 2026 08:55:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLOB-0008K4-Vo for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:41 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO9-0005ny-4B for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:39 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4838c15e3cbso94455495e9.3 for ; Mon, 27 Apr 2026 05:48:36 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-22-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/tlb_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index c74d8e785a..bbe1e70bc4 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -48,7 +48,7 @@ static inline uint64_t merge_syn_data_abort(uint32_t temp= late_syn, * ST64BV, or ST64BV0 insns report syndrome info even for stage-1 * faults and regardless of the target EL. */ - if (template_syn & ARM_EL_VNCR) { + if (FIELD_EX32(template_syn, DABORT_ISS, VNCR)) { /* * FEAT_NV2 faults on accesses via VNCR_EL2 are a special case: * they are always reported as "same EL", even though we are going @@ -190,7 +190,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, * because we masked that out in disas_set_insn_syndrome()) */ bool is_vncr =3D (access_type !=3D MMU_INST_FETCH) && - (env->exception.syndrome & ARM_EL_VNCR); + FIELD_EX32(env->exception.syndrome, DABORT_ISS, VNCR); =20 if (is_vncr) { /* FEAT_NV2 faults on accesses via VNCR_EL2 go to EL2 */ --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294623; cv=none; d=zohomail.com; s=zohoarc; b=SH4lxNsKZLDauROFsxQCHkwRb2TB0+5+jVHezQRiyCAdMhOLp7Z3JnMIbGQPAJ9g0+g8ae1IAYJLJb+fLJSVgs2fO7mtVBR4Ufqc5lHgH/AoBHSNBWFEOyyffnUUh+Ohdiyg7ZeXmQgZr8nKD4lgVAOu6igowqf/oWvrqjHky94= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294623; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jLexmZ22R7yN//oFkj+EbU4YprJnXV4rKA/t3VPqaqc=; b=CGeUNdlLIUWuHRVG9gP2ZHXUJUBxfzdQQLQsVbx/pjbdY/AQx0u/KLohKQS30d0rs/pxyEPN8yVtEueXtlaB0h7H3SiP8uXmMu7iLz5azmwjvUl1LQgLregn0yxbXxyKmSTI3ddSgpkRCJIUi9RHmNnxA8kak4xeiS8oeC2pVAE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294623323579.8909764300993; Mon, 27 Apr 2026 05:57:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUm-0001RJ-PK; Mon, 27 Apr 2026 08:55:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLOB-0008K5-Vi for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:41 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLO9-0005oC-M9 for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:39 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so172758825e9.2 for ; Mon, 27 Apr 2026 05:48:37 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-23-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d4dfab8cd1..04a71eebcb 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -106,15 +106,6 @@ typedef enum { GCS_IT_GCSPOPX =3D 9, } GCSInstructionType; =20 -#define ARM_EL_EC_LENGTH 6 -#define ARM_EL_IL_SHIFT 25 -#define ARM_EL_ISV_SHIFT 24 -#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) -#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) - -/* In the Data Abort syndrome */ -#define ARM_EL_VNCR (1 << 13) - static inline uint32_t syn_get_ec(uint32_t syn) { return FIELD_EX32(syn, SYNDROME, EC); --=20 2.43.0 From nobody Mon May 25 13:49:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777294845; cv=none; d=zohomail.com; s=zohoarc; b=iBPMZrMDyeb/6FPLEc34Gt/qCC0nHibWIXcCs4ICwwVsf7ERMpYPssqQXN0gbvPH9mqlZuFFrm7bzHhWrGEHHiS1OlLK8/PeUtKbTX4bcgQZcutxuNbkggs3KO0p92/qEsmjlTBkbVw+1R6sC2mZ3EZIBJf2izWPi3RI+fYqK7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777294845; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=88UCjHkoy1vmDeZmG5DzL1f9FS5Tx4PV0gRNHIRsxWs=; b=iYGCoL+QG18ZRskcbGU5Go8zOvLfZHsFiTlSJGS+MCPkVbbFtL4vI+bS6hZwA4ExGJkx2raglFmEAMPY3w0yHjZkUv103N2sF5netYCuepCPu2SXmY+VI9t+vHu53sw/YPZtsjvFa6YKGGNAQdbuXdmfC8fh6muGg7SoSsrjEgE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777294845208214.12019557442363; Mon, 27 Apr 2026 06:00:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wHLUW-0007wv-E0; Mon, 27 Apr 2026 08:55:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wHLOC-0008KB-BI for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:41 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wHLOA-0005p1-Fn for qemu-devel@nongnu.org; Mon, 27 Apr 2026 08:48:39 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4893940bb5eso53245405e9.3 for ; Mon, 27 Apr 2026 05:48:38 -0700 (PDT) Received: from lanath.. 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Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e Message-id: 20260422125250.1303100-24-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/syndrome.h | 11 ++++++++++- target/arm/tcg/helper-defs.h | 2 +- target/arm/tcg/op_helper.c | 7 ++++--- target/arm/tcg/translate-a64.c | 2 +- 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 04a71eebcb..4d1f1c529e 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -670,7 +670,14 @@ FIELD(WFX_ISS, RN, 5, 5) FIELD(WFX_ISS, COND, 20, 4) FIELD(WFX_ISS, CV, 24, 1) =20 -static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) +typedef enum { + WFI =3D 0b00, + WFE =3D 0b01, + WFIT =3D 0b10, + WFET =3D 0xb11 +} wfx_ti; + +static inline uint32_t syn_wfx(int cv, int cond, int rn, bool rv, wfx_ti t= i, bool is_16bit) { uint32_t res =3D syn_set_ec(0, EC_WFX_TRAP); res =3D FIELD_DP32(res, SYNDROME, IL, !is_16bit); @@ -678,6 +685,8 @@ static inline uint32_t syn_wfx(int cv, int cond, int ti= , bool is_16bit) res =3D FIELD_DP32(res, WFX_ISS, CV, cv); res =3D FIELD_DP32(res, WFX_ISS, COND, cond); res =3D FIELD_DP32(res, WFX_ISS, TI, ti); + res =3D FIELD_DP32(res, WFX_ISS, RN, rn); + res =3D FIELD_DP32(res, WFX_ISS, RV, rv); =20 return res; } diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index 5a10a9fba3..a05f2258f2 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -55,7 +55,7 @@ DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) -DEF_HELPER_2(wfit, void, env, i64) +DEF_HELPER_2(wfit, void, env, i32) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 75ad53ec6c..e8f0996ed3 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -398,7 +398,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) env->regs[15] -=3D insn_len; } =20 - raise_exception(env, excp, syn_wfx(1, 0xe, 0, insn_len =3D=3D 2), + raise_exception(env, excp, syn_wfx(1, 0xe, 0, false, WFI, insn_len= =3D=3D 2), target_el); } =20 @@ -408,7 +408,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) #endif } =20 -void HELPER(wfit)(CPUARMState *env, uint64_t timeout) +void HELPER(wfit)(CPUARMState *env, uint32_t rd) { #ifdef CONFIG_USER_ONLY /* @@ -427,6 +427,7 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) int target_el =3D check_wfx_trap(env, false, &excp); /* The WFIT should time out when CNTVCT_EL0 >=3D the specified value. = */ uint64_t cntval =3D gt_get_countervalue(env); + uint64_t timeout =3D env->xregs[rd]; /* * We want the value that we would get if we read CNTVCT_EL0 from * the current exception level, so the direct_access offset, not @@ -447,7 +448,7 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) =20 if (target_el) { env->pc -=3D 4; - raise_exception(env, excp, syn_wfx(1, 0xe, 2, false), target_el); + raise_exception(env, excp, syn_wfx(1, 0xe, rd, true, WFIT, false),= target_el); } =20 if (uadd64_overflow(timeout, offset, &nexttick)) { diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 48b5c57255..9a27c4c6ec 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2065,7 +2065,7 @@ static bool trans_WFIT(DisasContext *s, arg_WFIT *a) } =20 gen_a64_update_pc(s, 4); - gen_helper_wfit(tcg_env, cpu_reg(s, a->rd)); + gen_helper_wfit(tcg_env, tcg_constant_i32(a->rd)); /* Go back to the main loop to check for interrupts */ s->base.is_jmp =3D DISAS_EXIT; return true; --=20 2.43.0