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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777283885; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=diJW5Us/fw0hRQLpzr2MUjzdR2wROGfvvxAZaCmGEN4=; b=iI3Syy5ELOVgU8IzdZ9yXv4z65CJhuUq+XqNF7qtI7AsuMjJ0xLUt4yW3HvuQV2ghkGKzN djkPQCx9O/8sEpq2RRe7xKaaRt1Ty1ve0SDZI9dN79GxxaROWBs71v4rvPJ+fTsW/WwMxG vrW7w3hF8E9BLyB9SFT0VS1r6g9BwyQ= X-MC-Unique: jPSkIPMBOXukjwkrbKpo3A-1 X-Mimecast-MFC-AGG-ID: jPSkIPMBOXukjwkrbKpo3A_1777283883 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org Subject: [PULL 03/10] target/i386/tcg/sysemu: Allow 32-bit SMM code to be used in the 64-bit binary Date: Mon, 27 Apr 2026 11:57:40 +0200 Message-ID: <20260427095747.1070244-4-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283922127158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth This is a preparation for the QEMU universal binary where we might want to support both, the x86_64 and the i386 target, in one binary. Instead of using #ifdef TARGET_X86_64 here, check the LM bit to select the 32-bit or 64-bit code during runtime. Signed-off-by: Thomas Huth Message-ID: <20260325120944.29391-3-thuth@redhat.com> --- target/i386/tcg/system/smm_helper.c | 65 +++++++++++++++++++---------- 1 file changed, 43 insertions(+), 22 deletions(-) diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/s= mm_helper.c index 3be78cd53d3..4bbe18a86fb 100644 --- a/target/i386/tcg/system/smm_helper.c +++ b/target/i386/tcg/system/smm_helper.c @@ -23,24 +23,15 @@ #include "exec/log.h" #include "tcg/helper-tcg.h" =20 - -/* SMM support */ - -#ifdef TARGET_X86_64 -#define SMM_REVISION_ID 0x00020064 -#else -#define SMM_REVISION_ID 0x00020000 -#endif - -static void sm_state_init(X86CPU *cpu) +static void sm_state_init_64(X86CPU *cpu) { +#ifdef TARGET_X86_64 CPUX86State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); SegmentCache *dt; int i, offset; target_ulong sm_state =3D env->smbase + 0x8000; =20 -#ifdef TARGET_X86_64 for (i =3D 0; i < 6; i++) { dt =3D &env->segs[i]; offset =3D 0x7e00 + i * 16; @@ -92,9 +83,21 @@ static void sm_state_init(X86CPU *cpu) x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]); =20 - x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); + x86_stl_phys(cs, sm_state + 0x7efc, 0x00020064); /* SMM revision ID= */ x86_stl_phys(cs, sm_state + 0x7f00, env->smbase); #else + g_assert_not_reached(); +#endif +} + +static void sm_state_init_32(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + SegmentCache *dt; + int i, offset; + target_ulong sm_state =3D env->smbase + 0x8000; + x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]); x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env)); @@ -140,9 +143,8 @@ static void sm_state_init(X86CPU *cpu) } x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]); =20 - x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); + x86_stl_phys(cs, sm_state + 0x7efc, 0x00020000); /* SMM revision ID = */ x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); -#endif } =20 void do_smm_enter(X86CPU *cpu) @@ -160,13 +162,15 @@ void do_smm_enter(X86CPU *cpu) env->hflags2 |=3D HF2_NMI_MASK; } =20 - sm_state_init(cpu); + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + sm_state_init_64(cpu); + cpu_load_efer(env, 0); + } else { + sm_state_init_32(cpu); + } =20 /* init SMM cpu state */ =20 -#ifdef TARGET_X86_64 - cpu_load_efer(env, 0); -#endif cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip =3D 0x00008000; @@ -197,15 +201,16 @@ void do_smm_enter(X86CPU *cpu) DESC_G_MASK | DESC_A_MASK); } =20 -static void rsm_load_regs(CPUX86State *env) +static void rsm_load_regs_64(CPUX86State *env) { +#ifdef TARGET_X86_64 CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; =20 sm_state =3D env->smbase + 0x8000; -#ifdef TARGET_X86_64 + cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0)); =20 env->gdt.base =3D x86_ldq_phys(cs, sm_state + 0x7e68); @@ -260,6 +265,19 @@ static void rsm_load_regs(CPUX86State *env) env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7f00); } #else + g_assert_not_reached(); +#endif +} + +static void rsm_load_regs_32(CPUX86State *env) +{ + CPUState *cs =3D env_cpu(env); + target_ulong sm_state; + int i, offset; + uint32_t val; + + sm_state =3D env->smbase + 0x8000; + cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8)); cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4), @@ -312,14 +330,17 @@ static void rsm_load_regs(CPUX86State *env) if (val & 0x20000) { env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7ef8); } -#endif } =20 void helper_rsm(CPUX86State *env) { X86CPU *cpu =3D env_archcpu(env); =20 - rsm_load_regs(env); + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + rsm_load_regs_64(env); + } else { + rsm_load_regs_32(env); + } =20 if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) =3D=3D 0) { env->hflags2 &=3D ~HF2_NMI_MASK; --=20 2.53.0