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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777283882; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CApNhrC8Uo90IDNwWPD2mDbMfjH7rj94AQmsKwXeTgE=; b=MNuLyxdZ0mXt6RzRWBZEoGAhtGomb5WvKlHw6PCxOBiJbCp72yHveJfuC3gmKwbEmi9PN1 4SEBD2uIWqbsQwnr2yLBZKeb/pF0fITnR3ahcFhDjI/WDw6d/UPNpH0/RH4zc9ealiqpQl H7OlmjU0STOrmN7ZIlUVss9ljPQ6UmE= X-MC-Unique: Ji_DAO2hNBOvZVbcdwZlKQ-1 X-Mimecast-MFC-AGG-ID: Ji_DAO2hNBOvZVbcdwZlKQ_1777283879 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Fabiano Rosas Subject: [PULL 01/10] meson.build: Bump the minimum GCC version to v10.4 Date: Mon, 27 Apr 2026 11:57:38 +0200 Message-ID: <20260427095747.1070244-2-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283951462154100 From: Thomas Huth Our minimum supported version of GCC used to be v7.4 since we still wanted to support NetBSD 9.x in the past: https://gitlab.com/qemu-project/qemu/-/issues/614 https://gitlab.com/qemu-project/qemu/-/commit/3830df5f83b9b52d949676 However, NetBSD 10 has already been released since two years ago (see https://www.netbsd.org/releases/formal-10/NetBSD-10.0.html), so according to our support policy, starting with QEMU v11.0, we don't have to take care of the previous major release of NetBSD anymore. Looking at the various distros that we take care of (see e.g. https://repology.org/project/gcc/versions), and the NetBSD 10.0 3rd party package information: https://cvsweb.netbsd.org/bsdweb.cgi/src/doc/3RDPARTY?rev=3D1.1905.2.14;co= ntent-type=3Dtext%2Fplain;only_with_tag=3Dnetbsd-10-0-RELEASE ... it seems like NetBSD 10 has the lowest version of GCC again, but at least it's GCC 10.4 now. Thus bump our GCC requirement to this version now. Reviewed-by: Daniel P. Berrang=C3=A9 Acked-by: Fabiano Rosas Signed-off-by: Thomas Huth Message-ID: <20260310155331.320066-1-thuth@redhat.com> --- meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meson.build b/meson.build index 096303f021c..7d25b1ec7ef 100644 --- a/meson.build +++ b/meson.build @@ -329,7 +329,7 @@ endif =20 foreach lang : all_languages compiler =3D meson.get_compiler(lang) - if compiler.get_id() =3D=3D 'gcc' and compiler.version().version_compare= ('>=3D7.4') + if compiler.get_id() =3D=3D 'gcc' and compiler.version().version_compare= ('>=3D10.4') # ok elif compiler.get_id() =3D=3D 'clang' and compiler.compiles(''' #ifdef __apple_build_version__ @@ -345,7 +345,7 @@ foreach lang : all_languages elif compiler.get_id() =3D=3D 'emscripten' # ok else - error('You either need GCC v7.4 or Clang v10.0 (or XCode Clang v15.0) = to compile QEMU') + error('You either need GCC v10.4 or Clang v10.0 (or XCode Clang v15.0)= to compile QEMU') endif endforeach =20 --=20 2.53.0 From nobody Mon May 25 13:47:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283923046154100 Content-Type: text/plain; charset="utf-8" From: Thomas Huth This code movement will make the next patch easier to read. Signed-off-by: Thomas Huth Message-ID: <20260325120944.29391-2-thuth@redhat.com> --- target/i386/tcg/system/smm_helper.c | 47 ++++++++++++++++++----------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/s= mm_helper.c index fb028a8272f..3be78cd53d3 100644 --- a/target/i386/tcg/system/smm_helper.c +++ b/target/i386/tcg/system/smm_helper.c @@ -32,26 +32,13 @@ #define SMM_REVISION_ID 0x00020000 #endif =20 -void do_smm_enter(X86CPU *cpu) +static void sm_state_init(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); - target_ulong sm_state; SegmentCache *dt; int i, offset; - - qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); - log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); - - env->msr_smi_count++; - env->hflags |=3D HF_SMM_MASK; - if (env->hflags2 & HF2_NMI_MASK) { - env->hflags2 |=3D HF2_SMM_INSIDE_NMI_MASK; - } else { - env->hflags2 |=3D HF2_NMI_MASK; - } - - sm_state =3D env->smbase + 0x8000; + target_ulong sm_state =3D env->smbase + 0x8000; =20 #ifdef TARGET_X86_64 for (i =3D 0; i < 6; i++) { @@ -156,6 +143,25 @@ void do_smm_enter(X86CPU *cpu) x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); #endif +} + +void do_smm_enter(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); + + env->msr_smi_count++; + env->hflags |=3D HF_SMM_MASK; + if (env->hflags2 & HF2_NMI_MASK) { + env->hflags2 |=3D HF2_SMM_INSIDE_NMI_MASK; + } else { + env->hflags2 |=3D HF2_NMI_MASK; + } + + sm_state_init(cpu); + /* init SMM cpu state */ =20 #ifdef TARGET_X86_64 @@ -191,9 +197,8 @@ void do_smm_enter(X86CPU *cpu) DESC_G_MASK | DESC_A_MASK); } =20 -void helper_rsm(CPUX86State *env) +static void rsm_load_regs(CPUX86State *env) { - X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; @@ -308,6 +313,14 @@ void helper_rsm(CPUX86State *env) env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7ef8); } #endif +} + +void helper_rsm(CPUX86State *env) +{ + X86CPU *cpu =3D env_archcpu(env); + + rsm_load_regs(env); + if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) =3D=3D 0) { env->hflags2 &=3D ~HF2_NMI_MASK; } --=20 2.53.0 From nobody Mon May 25 13:47:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1777283920; cv=none; d=zohomail.com; s=zohoarc; b=HipvKc7Y+g43G1mSngoS1A+IEZCpBDZWmlI9p7yV6F9GqDfVqvnMlay9KmNz6+qPwFXT1WUJsxBJPH9Mtz8jZGFANs1cbvO1LNELAz+xUNJrSdExicVu1wm29hPRO6mWcpeB91ophKoUjpdzHKctjIEWIZYtjYG4LTj3MmyWQXI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777283920; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 27 Apr 2026 09:58:03 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.44.48.146]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C0C693000707; Mon, 27 Apr 2026 09:58:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777283885; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=diJW5Us/fw0hRQLpzr2MUjzdR2wROGfvvxAZaCmGEN4=; b=iI3Syy5ELOVgU8IzdZ9yXv4z65CJhuUq+XqNF7qtI7AsuMjJ0xLUt4yW3HvuQV2ghkGKzN djkPQCx9O/8sEpq2RRe7xKaaRt1Ty1ve0SDZI9dN79GxxaROWBs71v4rvPJ+fTsW/WwMxG vrW7w3hF8E9BLyB9SFT0VS1r6g9BwyQ= X-MC-Unique: jPSkIPMBOXukjwkrbKpo3A-1 X-Mimecast-MFC-AGG-ID: jPSkIPMBOXukjwkrbKpo3A_1777283883 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org Subject: [PULL 03/10] target/i386/tcg/sysemu: Allow 32-bit SMM code to be used in the 64-bit binary Date: Mon, 27 Apr 2026 11:57:40 +0200 Message-ID: <20260427095747.1070244-4-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283922127158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth This is a preparation for the QEMU universal binary where we might want to support both, the x86_64 and the i386 target, in one binary. Instead of using #ifdef TARGET_X86_64 here, check the LM bit to select the 32-bit or 64-bit code during runtime. Signed-off-by: Thomas Huth Message-ID: <20260325120944.29391-3-thuth@redhat.com> --- target/i386/tcg/system/smm_helper.c | 65 +++++++++++++++++++---------- 1 file changed, 43 insertions(+), 22 deletions(-) diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/s= mm_helper.c index 3be78cd53d3..4bbe18a86fb 100644 --- a/target/i386/tcg/system/smm_helper.c +++ b/target/i386/tcg/system/smm_helper.c @@ -23,24 +23,15 @@ #include "exec/log.h" #include "tcg/helper-tcg.h" =20 - -/* SMM support */ - -#ifdef TARGET_X86_64 -#define SMM_REVISION_ID 0x00020064 -#else -#define SMM_REVISION_ID 0x00020000 -#endif - -static void sm_state_init(X86CPU *cpu) +static void sm_state_init_64(X86CPU *cpu) { +#ifdef TARGET_X86_64 CPUX86State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); SegmentCache *dt; int i, offset; target_ulong sm_state =3D env->smbase + 0x8000; =20 -#ifdef TARGET_X86_64 for (i =3D 0; i < 6; i++) { dt =3D &env->segs[i]; offset =3D 0x7e00 + i * 16; @@ -92,9 +83,21 @@ static void sm_state_init(X86CPU *cpu) x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]); =20 - x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); + x86_stl_phys(cs, sm_state + 0x7efc, 0x00020064); /* SMM revision ID= */ x86_stl_phys(cs, sm_state + 0x7f00, env->smbase); #else + g_assert_not_reached(); +#endif +} + +static void sm_state_init_32(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + SegmentCache *dt; + int i, offset; + target_ulong sm_state =3D env->smbase + 0x8000; + x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]); x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env)); @@ -140,9 +143,8 @@ static void sm_state_init(X86CPU *cpu) } x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]); =20 - x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); + x86_stl_phys(cs, sm_state + 0x7efc, 0x00020000); /* SMM revision ID = */ x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); -#endif } =20 void do_smm_enter(X86CPU *cpu) @@ -160,13 +162,15 @@ void do_smm_enter(X86CPU *cpu) env->hflags2 |=3D HF2_NMI_MASK; } =20 - sm_state_init(cpu); + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + sm_state_init_64(cpu); + cpu_load_efer(env, 0); + } else { + sm_state_init_32(cpu); + } =20 /* init SMM cpu state */ =20 -#ifdef TARGET_X86_64 - cpu_load_efer(env, 0); -#endif cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip =3D 0x00008000; @@ -197,15 +201,16 @@ void do_smm_enter(X86CPU *cpu) DESC_G_MASK | DESC_A_MASK); } =20 -static void rsm_load_regs(CPUX86State *env) +static void rsm_load_regs_64(CPUX86State *env) { +#ifdef TARGET_X86_64 CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; =20 sm_state =3D env->smbase + 0x8000; -#ifdef TARGET_X86_64 + cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0)); =20 env->gdt.base =3D x86_ldq_phys(cs, sm_state + 0x7e68); @@ -260,6 +265,19 @@ static void rsm_load_regs(CPUX86State *env) env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7f00); } #else + g_assert_not_reached(); +#endif +} + +static void rsm_load_regs_32(CPUX86State *env) +{ + CPUState *cs =3D env_cpu(env); + target_ulong sm_state; + int i, offset; + uint32_t val; + + sm_state =3D env->smbase + 0x8000; + cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8)); cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4), @@ -312,14 +330,17 @@ static void rsm_load_regs(CPUX86State *env) if (val & 0x20000) { env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7ef8); } -#endif } =20 void helper_rsm(CPUX86State *env) { X86CPU *cpu =3D env_archcpu(env); =20 - rsm_load_regs(env); + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + rsm_load_regs_64(env); + } else { + rsm_load_regs_32(env); + } =20 if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) =3D=3D 0) { env->hflags2 &=3D ~HF2_NMI_MASK; --=20 2.53.0 From nobody Mon May 25 13:47:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=a7MnxO9YxprDAdHvxmaoSseAOu1eT56DM4IYeRy3AxD9sW7JICGlVaOl43bAJR/cY7o9sA amqwRHLU0hLDiPk15ISNIOvpoyE6Cpm97v24O8yydWYCvlFZU0hWm1+tmVmmo8jzneLrYC ZX4Z0hYo024zrgqg6JSAnom45E5uIvE= X-MC-Unique: pEYc-xDxMHSCJFw4alm1lg-1 X-Mimecast-MFC-AGG-ID: pEYc-xDxMHSCJFw4alm1lg_1777283888 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Tanya Agarwal Subject: [PULL 04/10] target: convert TABS indentation to spaces for consistency Date: Mon, 27 Apr 2026 11:57:41 +0200 Message-ID: <20260427095747.1070244-5-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283924030158500 Content-Type: text/plain; charset="utf-8" From: Tanya Agarwal To follow consistent coding style, convert TABS indentation to spaces for consistency. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/372 Signed-off-by: Tanya Agarwal Reviewed-by: Thomas Huth Message-ID: <20260328170913.3673-1-tanyaagarwal25699@gmail.com> Signed-off-by: Thomas Huth --- target/alpha/cpu.h | 6 +- target/i386/cpu.h | 40 ++--- target/i386/svm.h | 308 ++++++++++++++++++------------------- target/microblaze/cpu.h | 12 +- target/sparc/asi.h | 328 ++++++++++++++++++++-------------------- 5 files changed, 347 insertions(+), 347 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 45944e46b54..b530cd0088b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -311,9 +311,9 @@ enum { }; =20 /* Alpha-specific interrupt pending bits. */ -#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 -#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 -#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 +#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 +#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 +#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 =20 /* OSF/1 Page table bits. */ enum { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0b539155c40..a09d5de121e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -417,12 +417,12 @@ typedef enum X86Seg { #define MSR_IA32_CORE_CAPABILITY 0xcf =20 #define MSR_IA32_ARCH_CAPABILITIES 0x10a -#define ARCH_CAP_TSX_CTRL_MSR (1<<7) +#define ARCH_CAP_TSX_CTRL_MSR (1 << 7) =20 #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT 0x3f =20 -#define MSR_IA32_TSX_CTRL 0x122 +#define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_IA32_PKRS 0x6e1 #define MSR_RAPL_POWER_UNIT 0x00000606 @@ -1482,24 +1482,24 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU = *cpu, FeatureWord w); #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF #endif =20 -#define EXCP00_DIVZ 0 -#define EXCP01_DB 1 -#define EXCP02_NMI 2 -#define EXCP03_INT3 3 -#define EXCP04_INTO 4 -#define EXCP05_BOUND 5 -#define EXCP06_ILLOP 6 -#define EXCP07_PREX 7 -#define EXCP08_DBLE 8 -#define EXCP09_XERR 9 -#define EXCP0A_TSS 10 -#define EXCP0B_NOSEG 11 -#define EXCP0C_STACK 12 -#define EXCP0D_GPF 13 -#define EXCP0E_PAGE 14 -#define EXCP10_COPR 16 -#define EXCP11_ALGN 17 -#define EXCP12_MCHK 18 +#define EXCP00_DIVZ 0 +#define EXCP01_DB 1 +#define EXCP02_NMI 2 +#define EXCP03_INT3 3 +#define EXCP04_INTO 4 +#define EXCP05_BOUND 5 +#define EXCP06_ILLOP 6 +#define EXCP07_PREX 7 +#define EXCP08_DBLE 8 +#define EXCP09_XERR 9 +#define EXCP0A_TSS 10 +#define EXCP0B_NOSEG 11 +#define EXCP0C_STACK 12 +#define EXCP0D_GPF 13 +#define EXCP0E_PAGE 14 +#define EXCP10_COPR 16 +#define EXCP11_ALGN 17 +#define EXCP12_MCHK 18 =20 #define EXCP_VMEXIT 0x100 /* only for system emulation */ #define EXCP_SYSCALL 0x101 /* only for user emulation */ diff --git a/target/i386/svm.h b/target/i386/svm.h index 1bd78447306..23c36637d4a 100644 --- a/target/i386/svm.h +++ b/target/i386/svm.h @@ -54,88 +54,88 @@ =20 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK =20 -#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR -#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI -#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT -#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT +#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR +#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI +#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT +#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT =20 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR =20 -#define SVM_EXIT_READ_CR0 0x000 -#define SVM_EXIT_READ_CR3 0x003 -#define SVM_EXIT_READ_CR4 0x004 -#define SVM_EXIT_READ_CR8 0x008 -#define SVM_EXIT_WRITE_CR0 0x010 -#define SVM_EXIT_WRITE_CR3 0x013 -#define SVM_EXIT_WRITE_CR4 0x014 -#define SVM_EXIT_WRITE_CR8 0x018 -#define SVM_EXIT_READ_DR0 0x020 -#define SVM_EXIT_READ_DR1 0x021 -#define SVM_EXIT_READ_DR2 0x022 -#define SVM_EXIT_READ_DR3 0x023 -#define SVM_EXIT_READ_DR4 0x024 -#define SVM_EXIT_READ_DR5 0x025 -#define SVM_EXIT_READ_DR6 0x026 -#define SVM_EXIT_READ_DR7 0x027 -#define SVM_EXIT_WRITE_DR0 0x030 -#define SVM_EXIT_WRITE_DR1 0x031 -#define SVM_EXIT_WRITE_DR2 0x032 -#define SVM_EXIT_WRITE_DR3 0x033 -#define SVM_EXIT_WRITE_DR4 0x034 -#define SVM_EXIT_WRITE_DR5 0x035 -#define SVM_EXIT_WRITE_DR6 0x036 -#define SVM_EXIT_WRITE_DR7 0x037 +#define SVM_EXIT_READ_CR0 0x000 +#define SVM_EXIT_READ_CR3 0x003 +#define SVM_EXIT_READ_CR4 0x004 +#define SVM_EXIT_READ_CR8 0x008 +#define SVM_EXIT_WRITE_CR0 0x010 +#define SVM_EXIT_WRITE_CR3 0x013 +#define SVM_EXIT_WRITE_CR4 0x014 +#define SVM_EXIT_WRITE_CR8 0x018 +#define SVM_EXIT_READ_DR0 0x020 +#define SVM_EXIT_READ_DR1 0x021 +#define SVM_EXIT_READ_DR2 0x022 +#define SVM_EXIT_READ_DR3 0x023 +#define SVM_EXIT_READ_DR4 0x024 +#define SVM_EXIT_READ_DR5 0x025 +#define SVM_EXIT_READ_DR6 0x026 +#define SVM_EXIT_READ_DR7 0x027 +#define SVM_EXIT_WRITE_DR0 0x030 +#define SVM_EXIT_WRITE_DR1 0x031 +#define SVM_EXIT_WRITE_DR2 0x032 +#define SVM_EXIT_WRITE_DR3 0x033 +#define SVM_EXIT_WRITE_DR4 0x034 +#define SVM_EXIT_WRITE_DR5 0x035 +#define SVM_EXIT_WRITE_DR6 0x036 +#define SVM_EXIT_WRITE_DR7 0x037 #define SVM_EXIT_EXCP_BASE 0x040 -#define SVM_EXIT_INTR 0x060 -#define SVM_EXIT_NMI 0x061 -#define SVM_EXIT_SMI 0x062 -#define SVM_EXIT_INIT 0x063 -#define SVM_EXIT_VINTR 0x064 -#define SVM_EXIT_CR0_SEL_WRITE 0x065 -#define SVM_EXIT_IDTR_READ 0x066 -#define SVM_EXIT_GDTR_READ 0x067 -#define SVM_EXIT_LDTR_READ 0x068 -#define SVM_EXIT_TR_READ 0x069 -#define SVM_EXIT_IDTR_WRITE 0x06a -#define SVM_EXIT_GDTR_WRITE 0x06b -#define SVM_EXIT_LDTR_WRITE 0x06c -#define SVM_EXIT_TR_WRITE 0x06d -#define SVM_EXIT_RDTSC 0x06e -#define SVM_EXIT_RDPMC 0x06f -#define SVM_EXIT_PUSHF 0x070 -#define SVM_EXIT_POPF 0x071 -#define SVM_EXIT_CPUID 0x072 -#define SVM_EXIT_RSM 0x073 -#define SVM_EXIT_IRET 0x074 -#define SVM_EXIT_SWINT 0x075 -#define SVM_EXIT_INVD 0x076 -#define SVM_EXIT_PAUSE 0x077 -#define SVM_EXIT_HLT 0x078 -#define SVM_EXIT_INVLPG 0x079 -#define SVM_EXIT_INVLPGA 0x07a -#define SVM_EXIT_IOIO 0x07b -#define SVM_EXIT_MSR 0x07c -#define SVM_EXIT_TASK_SWITCH 0x07d -#define SVM_EXIT_FERR_FREEZE 0x07e -#define SVM_EXIT_SHUTDOWN 0x07f -#define SVM_EXIT_VMRUN 0x080 -#define SVM_EXIT_VMMCALL 0x081 -#define SVM_EXIT_VMLOAD 0x082 -#define SVM_EXIT_VMSAVE 0x083 -#define SVM_EXIT_STGI 0x084 -#define SVM_EXIT_CLGI 0x085 -#define SVM_EXIT_SKINIT 0x086 -#define SVM_EXIT_RDTSCP 0x087 -#define SVM_EXIT_ICEBP 0x088 -#define SVM_EXIT_WBINVD 0x089 +#define SVM_EXIT_INTR 0x060 +#define SVM_EXIT_NMI 0x061 +#define SVM_EXIT_SMI 0x062 +#define SVM_EXIT_INIT 0x063 +#define SVM_EXIT_VINTR 0x064 +#define SVM_EXIT_CR0_SEL_WRITE 0x065 +#define SVM_EXIT_IDTR_READ 0x066 +#define SVM_EXIT_GDTR_READ 0x067 +#define SVM_EXIT_LDTR_READ 0x068 +#define SVM_EXIT_TR_READ 0x069 +#define SVM_EXIT_IDTR_WRITE 0x06a +#define SVM_EXIT_GDTR_WRITE 0x06b +#define SVM_EXIT_LDTR_WRITE 0x06c +#define SVM_EXIT_TR_WRITE 0x06d +#define SVM_EXIT_RDTSC 0x06e +#define SVM_EXIT_RDPMC 0x06f +#define SVM_EXIT_PUSHF 0x070 +#define SVM_EXIT_POPF 0x071 +#define SVM_EXIT_CPUID 0x072 +#define SVM_EXIT_RSM 0x073 +#define SVM_EXIT_IRET 0x074 +#define SVM_EXIT_SWINT 0x075 +#define SVM_EXIT_INVD 0x076 +#define SVM_EXIT_PAUSE 0x077 +#define SVM_EXIT_HLT 0x078 +#define SVM_EXIT_INVLPG 0x079 +#define SVM_EXIT_INVLPGA 0x07a +#define SVM_EXIT_IOIO 0x07b +#define SVM_EXIT_MSR 0x07c +#define SVM_EXIT_TASK_SWITCH 0x07d +#define SVM_EXIT_FERR_FREEZE 0x07e +#define SVM_EXIT_SHUTDOWN 0x07f +#define SVM_EXIT_VMRUN 0x080 +#define SVM_EXIT_VMMCALL 0x081 +#define SVM_EXIT_VMLOAD 0x082 +#define SVM_EXIT_VMSAVE 0x083 +#define SVM_EXIT_STGI 0x084 +#define SVM_EXIT_CLGI 0x085 +#define SVM_EXIT_SKINIT 0x086 +#define SVM_EXIT_RDTSCP 0x087 +#define SVM_EXIT_ICEBP 0x088 +#define SVM_EXIT_WBINVD 0x089 /* only included in documentation, maybe wrong */ -#define SVM_EXIT_MONITOR 0x08a -#define SVM_EXIT_MWAIT 0x08b -#define SVM_EXIT_XSETBV 0x08d -#define SVM_EXIT_NPF 0x400 +#define SVM_EXIT_MONITOR 0x08a +#define SVM_EXIT_MWAIT 0x08b +#define SVM_EXIT_XSETBV 0x08d +#define SVM_EXIT_NPF 0x400 =20 -#define SVM_EXIT_ERR -1 +#define SVM_EXIT_ERR -1 =20 #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */ =20 @@ -146,96 +146,96 @@ =20 #define SVM_CR0_RESERVED_MASK 0xffffffff00000000U =20 -#define SVM_MSRPM_SIZE (1ULL << 13) -#define SVM_IOPM_SIZE ((1ULL << 13) + 1) +#define SVM_MSRPM_SIZE (1ULL << 13) +#define SVM_IOPM_SIZE ((1ULL << 13) + 1) =20 struct QEMU_PACKED vmcb_control_area { - uint16_t intercept_cr_read; - uint16_t intercept_cr_write; - uint16_t intercept_dr_read; - uint16_t intercept_dr_write; - uint32_t intercept_exceptions; - uint64_t intercept; - uint8_t reserved_1[44]; - uint64_t iopm_base_pa; - uint64_t msrpm_base_pa; - uint64_t tsc_offset; - uint32_t asid; - uint8_t tlb_ctl; - uint8_t reserved_2[3]; - uint32_t int_ctl; - uint32_t int_vector; - uint32_t int_state; - uint8_t reserved_3[4]; - uint64_t exit_code; - uint64_t exit_info_1; - uint64_t exit_info_2; - uint32_t exit_int_info; - uint32_t exit_int_info_err; - uint64_t nested_ctl; - uint8_t reserved_4[16]; - uint32_t event_inj; - uint32_t event_inj_err; - uint64_t nested_cr3; - uint64_t lbr_ctl; - uint8_t reserved_5[832]; + uint16_t intercept_cr_read; + uint16_t intercept_cr_write; + uint16_t intercept_dr_read; + uint16_t intercept_dr_write; + uint32_t intercept_exceptions; + uint64_t intercept; + uint8_t reserved_1[44]; + uint64_t iopm_base_pa; + uint64_t msrpm_base_pa; + uint64_t tsc_offset; + uint32_t asid; + uint8_t tlb_ctl; + uint8_t reserved_2[3]; + uint32_t int_ctl; + uint32_t int_vector; + uint32_t int_state; + uint8_t reserved_3[4]; + uint64_t exit_code; + uint64_t exit_info_1; + uint64_t exit_info_2; + uint32_t exit_int_info; + uint32_t exit_int_info_err; + uint64_t nested_ctl; + uint8_t reserved_4[16]; + uint32_t event_inj; + uint32_t event_inj_err; + uint64_t nested_cr3; + uint64_t lbr_ctl; + uint8_t reserved_5[832]; }; =20 struct QEMU_PACKED vmcb_seg { - uint16_t selector; - uint16_t attrib; - uint32_t limit; - uint64_t base; + uint16_t selector; + uint16_t attrib; + uint32_t limit; + uint64_t base; }; =20 struct QEMU_PACKED vmcb_save_area { - struct vmcb_seg es; - struct vmcb_seg cs; - struct vmcb_seg ss; - struct vmcb_seg ds; - struct vmcb_seg fs; - struct vmcb_seg gs; - struct vmcb_seg gdtr; - struct vmcb_seg ldtr; - struct vmcb_seg idtr; - struct vmcb_seg tr; - uint8_t reserved_1[43]; - uint8_t cpl; - uint8_t reserved_2[4]; - uint64_t efer; - uint8_t reserved_3[112]; - uint64_t cr4; - uint64_t cr3; - uint64_t cr0; - uint64_t dr7; - uint64_t dr6; - uint64_t rflags; - uint64_t rip; - uint8_t reserved_4[88]; - uint64_t rsp; - uint8_t reserved_5[24]; - uint64_t rax; - uint64_t star; - uint64_t lstar; - uint64_t cstar; - uint64_t sfmask; - uint64_t kernel_gs_base; - uint64_t sysenter_cs; - uint64_t sysenter_esp; - uint64_t sysenter_eip; - uint64_t cr2; - uint8_t reserved_6[32]; - uint64_t g_pat; - uint64_t dbgctl; - uint64_t br_from; - uint64_t br_to; - uint64_t last_excp_from; - uint64_t last_excp_to; + struct vmcb_seg es; + struct vmcb_seg cs; + struct vmcb_seg ss; + struct vmcb_seg ds; + struct vmcb_seg fs; + struct vmcb_seg gs; + struct vmcb_seg gdtr; + struct vmcb_seg ldtr; + struct vmcb_seg idtr; + struct vmcb_seg tr; + uint8_t reserved_1[43]; + uint8_t cpl; + uint8_t reserved_2[4]; + uint64_t efer; + uint8_t reserved_3[112]; + uint64_t cr4; + uint64_t cr3; + uint64_t cr0; + uint64_t dr7; + uint64_t dr6; + uint64_t rflags; + uint64_t rip; + uint8_t reserved_4[88]; + uint64_t rsp; + uint8_t reserved_5[24]; + uint64_t rax; + uint64_t star; + uint64_t lstar; + uint64_t cstar; + uint64_t sfmask; + uint64_t kernel_gs_base; + uint64_t sysenter_cs; + uint64_t sysenter_esp; + uint64_t sysenter_eip; + uint64_t cr2; + uint8_t reserved_6[32]; + uint64_t g_pat; + uint64_t dbgctl; + uint64_t br_from; + uint64_t br_to; + uint64_t last_excp_from; + uint64_t last_excp_to; }; =20 struct QEMU_PACKED vmcb { - struct vmcb_control_area control; - struct vmcb_save_area save; + struct vmcb_control_area control; + struct vmcb_save_area save; }; =20 #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d26b933b6d0..5a856edaaa9 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -122,9 +122,9 @@ typedef struct CPUArchState CPUMBState; #define PVR0_USE_ICACHE_MASK 0x02000000 #define PVR0_USE_DCACHE_MASK 0x01000000 #define PVR0_USE_MMU_MASK 0x00800000 -#define PVR0_USE_BTC 0x00400000 +#define PVR0_USE_BTC 0x00400000 #define PVR0_ENDI_MASK 0x00200000 -#define PVR0_FAULT 0x00100000 +#define PVR0_FAULT 0x00100000 #define PVR0_VERSION_MASK 0x0000FF00 #define PVR0_USER1_MASK 0x000000FF #define PVR0_SPROT_MASK 0x00000001 @@ -271,10 +271,10 @@ struct CPUArchState { /* MSR_UM (1 << 11) */ /* MSR_VM (1 << 13) */ /* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp= */ -#define D_FLAG (1 << 12) /* Bit in ESR. */ -#define DRTI_FLAG (1 << 16) -#define DRTE_FLAG (1 << 17) -#define DRTB_FLAG (1 << 18) +#define D_FLAG (1 << 12) /* Bit in ESR. */ +#define DRTI_FLAG (1 << 16) +#define DRTE_FLAG (1 << 17) +#define DRTB_FLAG (1 << 18) =20 /* TB dependent CPUMBState. */ #define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \ diff --git a/target/sparc/asi.h b/target/sparc/asi.h index 14ffaa3842d..7d6dae6d616 100644 --- a/target/sparc/asi.h +++ b/target/sparc/asi.h @@ -102,7 +102,7 @@ =20 #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, s= s */ =20 -#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */ +#define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */ /* only available on SuperSparc I */ /* #define ASI_M_VIKING_TMP2 0x41 */ /* Emulation temporary 2 on Viking = */ =20 @@ -123,20 +123,20 @@ #define ASI_LEON_FLUSH_PAGE 0x10 =20 /* V9 Architecture mandary ASIs. */ -#define ASI_N 0x04 /* Nucleus */ -#define ASI_NL 0x0c /* Nucleus, little endian */ -#define ASI_AIUP 0x10 /* Primary, user */ -#define ASI_AIUS 0x11 /* Secondary, user */ -#define ASI_AIUPL 0x18 /* Primary, user, little endian */ -#define ASI_AIUSL 0x19 /* Secondary, user, little endian */ -#define ASI_P 0x80 /* Primary, implicit */ -#define ASI_S 0x81 /* Secondary, implicit */ -#define ASI_PNF 0x82 /* Primary, no fault */ -#define ASI_SNF 0x83 /* Secondary, no fault */ -#define ASI_PL 0x88 /* Primary, implicit, l-endian */ -#define ASI_SL 0x89 /* Secondary, implicit, l-endian */ -#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */ -#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */ +#define ASI_N 0x04 /* Nucleus */ +#define ASI_NL 0x0c /* Nucleus, little endian */ +#define ASI_AIUP 0x10 /* Primary, user */ +#define ASI_AIUS 0x11 /* Secondary, user */ +#define ASI_AIUPL 0x18 /* Primary, user, little endian */ +#define ASI_AIUSL 0x19 /* Secondary, user, little endian */ +#define ASI_P 0x80 /* Primary, implicit */ +#define ASI_S 0x81 /* Secondary, implicit */ +#define ASI_PNF 0x82 /* Primary, no fault */ +#define ASI_SNF 0x83 /* Secondary, no fault */ +#define ASI_PL 0x88 /* Primary, implicit, l-endian */ +#define ASI_SL 0x89 /* Secondary, implicit, l-endian */ +#define ASI_PNFL 0x8a /* Primary, no fault, l-endian */ +#define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */ =20 /* SpitFire and later extended ASIs. The "(III)" marker designates * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates @@ -147,170 +147,170 @@ #define ASI_MON_AIUP 0x12 /* (VIS4) Primary, user, monitor */ #define ASI_MON_AIUS 0x13 /* (VIS4) Secondary, user, monitor */ #define ASI_REAL 0x14 /* Real address, cacheable */ -#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */ +#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */ #define ASI_REAL_IO 0x15 /* Real address, non-cacheable */ -#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ -#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */ -#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */ +#define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */ +#define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */ +#define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */ #define ASI_REAL_L 0x1c /* Real address, cacheable, LE */ -#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/ +#define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/ #define ASI_REAL_IO_L 0x1d /* Real address, non-cacheable, LE */ -#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ -#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/ -#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */ -#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */ -#define ASI_MMU 0x21 /* (4V) MMU Context Registers */ +#define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */ +#define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/ +#define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */ +#define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */ +#define ASI_MMU 0x21 /* (4V) MMU Context Registers */ #define ASI_TWINX_AIUP 0x22 /* twin load, primary user */ #define ASI_TWINX_AIUS 0x23 /* twin load, secondary user */ #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load, - * secondary, user - */ -#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */ -#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */ -#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */ -#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */ + * secondary, user + */ +#define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cacheable, qword load */ +#define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */ +#define ASI_TWINX_REAL 0x26 /* twin load, real, cacheable */ +#define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */ #define ASI_TWINX_N 0x27 /* twin load, nucleus */ #define ASI_TWINX_AIUP_L 0x2a /* twin load, primary user, LE */ #define ASI_TWINX_AIUS_L 0x2b /* twin load, secondary user, LE */ -#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */ -#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */ -#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */ +#define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */ +#define ASI_TWINX_REAL_L 0x2e /* twin load, real, cacheable, LE */ +#define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */ #define ASI_TWINX_NL 0x2f /* twin load, nucleus, LE */ -#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ -#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ -#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ -#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */ -#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */ -#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */ -#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */ -#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */ -#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */ -#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */ -#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */ -#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */ -#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */ -#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */ -#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */ -#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */ -#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */ -#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */ -#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */ -#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */ -#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */ -#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */ -#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */ -#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */ -#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */ -#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */ -#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/ -#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */ -#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */ -#define ASI_UPA_CONFIG 0x4a /* UPA config space */ -#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */ -#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */ -#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */ -#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */ -#define ASI_AFSR 0x4c /* Async fault status register */ -#define ASI_AFAR 0x4d /* Async fault address register */ -#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */ -#define ASI_HYP_SCRATCHPAD 0x4f /* (4V) Hypervisor scratchpad */ -#define ASI_IMMU 0x50 /* Insn-MMU main register space */ -#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */ -#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */ -#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */ -#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */ -#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */ -#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */ -#define ASI_DMMU 0x58 /* Data-MMU main register space */ -#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */ -#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */ -#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */ -#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */ -#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */ -#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */ -#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */ -#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */ -#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ -#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ -#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ -#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ -#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ -#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ -#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ -#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */ -#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/ -#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */ -#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */ -#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */ -#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */ -#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */ -#define ASI_EC_W 0x76 /* E-cache diag write access */ -#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */ -#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */ -#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */ -#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */ -#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */ -#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/ -#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/ -#define ASI_EC_R 0x7e /* E-cache diag read access */ -#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */ -#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */ -#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */ -#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/ -#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */ -#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */ +#define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */ +#define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */ +#define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */ +#define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */ +#define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */ +#define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */ +#define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */ +#define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */ +#define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */ +#define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */ +#define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */ +#define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */ +#define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */ +#define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */ +#define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */ +#define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */ +#define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */ +#define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */ +#define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */ +#define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */ +#define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */ +#define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */ +#define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */ +#define ASI_LSU_CONTROL 0x45 /* Load-store control unit */ +#define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */ +#define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */ +#define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/ +#define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */ +#define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */ +#define ASI_UPA_CONFIG 0x4a /* UPA config space */ +#define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */ +#define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */ +#define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */ +#define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */ +#define ASI_AFSR 0x4c /* Async fault status register */ +#define ASI_AFAR 0x4d /* Async fault address register */ +#define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */ +#define ASI_HYP_SCRATCHPAD 0x4f /* (4V) Hypervisor scratchpad */ +#define ASI_IMMU 0x50 /* Insn-MMU main register space */ +#define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */ +#define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */ +#define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */ +#define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */ +#define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */ +#define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */ +#define ASI_DMMU 0x58 /* Data-MMU main register space */ +#define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */ +#define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */ +#define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */ +#define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */ +#define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */ +#define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */ +#define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */ +#define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */ +#define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ +#define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ +#define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ +#define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ +#define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ +#define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ +#define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */ +#define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/ +#define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */ +#define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */ +#define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */ +#define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */ +#define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */ +#define ASI_EC_W 0x76 /* E-cache diag write access */ +#define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */ +#define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */ +#define ASI_INTR_W 0x77 /* IRQ vector dispatch write */ +#define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */ +#define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */ +#define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/ +#define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st= */ +#define ASI_EC_R 0x7e /* E-cache diag read access */ +#define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */ +#define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */ +#define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */ +#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/ +#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */ +#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */ #define ASI_MON_P 0x84 /* (VIS4) Primary, monitor */ #define ASI_MON_S 0x85 /* (VIS4) Secondary, monitor */ -#define ASI_PIC 0xb0 /* (NG4) PIC registers */ -#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */ -#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */ -#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */ -#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */ -#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */ -#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */ -#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */ -#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */ -#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */ -#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */ -#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */ -#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */ -#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */ -#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */ -#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */ -#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */ -#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */ -#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/ -#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */ -#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ -#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ -#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ +#define ASI_PIC 0xb0 /* (NG4) PIC registers */ +#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */ +#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */ +#define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */ +#define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */ +#define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */ +#define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */ +#define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */ +#define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */ +#define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */ +#define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */ +#define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */ +#define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */ +#define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */ +#define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */ +#define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */ +#define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */ +#define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */ +#define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/ +#define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */ +#define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/ +#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ +#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ #define ASI_TWINX_P 0xe2 /* twin load, primary implicit */ -#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load, - * primary, implicit */ +#define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load, + * primary, implicit */ #define ASI_TWINX_S 0xe3 /* twin load, secondary implicit */ -#define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load, - * secondary, implicit */ +#define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load, + * secondary, implicit */ #define ASI_TWINX_PL 0xea /* twin load, primary implicit, LE */ #define ASI_TWINX_SL 0xeb /* twin load, secondary implicit, LE = */ -#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ -#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ -#define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load, - * Most-Recently-Used, primary, - * implicit - */ -#define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load, - * Most-Recently-Used, secondary, - * implicit - */ -#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */ -#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */ -#define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load, - * Most-Recently-Used, primary, - * implicit, little-endian - */ -#define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load, - * Most-Recently-Used, secondary, - * implicit, little-endian - */ +#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ +#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ +#define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load, + * Most-Recently-Used, primary, + * implicit + */ +#define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load, + * Most-Recently-Used, secondary, + * implicit + */ +#define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */ +#define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */ +#define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load, + * Most-Recently-Used, primary, + * implicit, little-endian + */ +#define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load, + * Most-Recently-Used, secondary, + * implicit, little-endian + */ =20 #endif /* SPARC_ASI_H */ --=20 2.53.0 From nobody Mon May 25 13:47:50 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=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 05/10] util: fix use of pthread_get_name_np on OpenBSD Date: Mon, 27 Apr 2026 11:57:42 +0200 Message-ID: <20260427095747.1070244-6-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, 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Berrang=C3=A9 The pthread_get_name_np function is present on FreeBSD and OpenBSD and has 'void' return not 'int'. We didn't notice this build problem on FreeBSD since it also has pthread_getname_np which does return int like Linux and we use the latter preferentially. Fixes: 215235d365e49c72a85ea2940751e45419676031 Closes: https://gitlab.com/qemu-project/qemu/-/work_items/3399 Signed-off-by: Daniel P. Berrang=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Message-ID: <20260417120531.2215549-1-berrange@redhat.com> Signed-off-by: Thomas Huth --- util/qemu-thread-posix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c index bd1c2ad2a59..089606c93fb 100644 --- a/util/qemu-thread-posix.c +++ b/util/qemu-thread-posix.c @@ -568,7 +568,8 @@ const char *qemu_thread_get_name(void) # if defined(CONFIG_PTHREAD_GETNAME_NP) rv =3D pthread_getname_np(pthread_self(), namebuf, sizeof(namebuf)); # elif defined(CONFIG_PTHREAD_GET_NAME_NP) - rv =3D pthread_get_name_np(pthread_self(), namebuf, sizeof(namebuf)); + pthread_get_name_np(pthread_self(), namebuf, sizeof(namebuf)); + rv =3D 0; # else rv =3D -1; # endif --=20 2.53.0 From nobody Mon May 25 13:47:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=V5Jxuf5erNRILrW2WQrAEsFYkX/kGsStLYVOgq23PFw=; b=LmGwmrCHhpt9xyF7R5/vd2u3IUNUmnLy1/XOj3xDEvrMiN7lCaMRCt7thdTIy1fPZKzo9Z syDYrgh4Ws06wlcBWDQSnOlcD/SFribHXNIuE5I+H49GkiBe0rD8GAWYU3KxuwWGd2o6lN NU6oR4Gs5zeKhW3XY4hUECAdxVN2t2Q= X-MC-Unique: sm1ka78GM3aL_57NMqH5hg-1 X-Mimecast-MFC-AGG-ID: sm1ka78GM3aL_57NMqH5hg_1777283893 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 06/10] tests/functional/qemu_test: Silence warnings from pylint in tesseract.py Date: Mon, 27 Apr 2026 11:57:43 +0200 Message-ID: <20260427095747.1070244-7-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283922139158500 From: Thomas Huth Pylint complains: tesseract.py:1:0: C0114: Missing module docstring (missing-module-docstrin= g) tesseract.py:12:0: C0116: Missing function or method docstring (missing-fu= nction-docstring) tesseract.py:15:11: W1510: 'subprocess.run' used without explicitly defini= ng the value for 'check'. (subprocess-run-check) tesseract.py:12:30: W0613: Unused argument 'tesseract_args' (unused-argume= nt) Thus add the missing bits and remove the unused tesseract_args argument. While we're at it, also add a SPDX identifier instead of the weird three dots at the beginning of the file, and drop the license boilerplate text. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Thomas Huth Message-ID: <20260422071145.244820-1-thuth@redhat.com> --- tests/functional/qemu_test/tesseract.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/tests/functional/qemu_test/tesseract.py b/tests/functional/qem= u_test/tesseract.py index 862faec2d2e..9d98181cb45 100644 --- a/tests/functional/qemu_test/tesseract.py +++ b/tests/functional/qemu_test/tesseract.py @@ -1,19 +1,21 @@ -# ... +# SPDX-License-Identifier: GPL-2.0-or-later # # Copyright (c) 2019 Philippe Mathieu-Daud=C3=A9 -# -# This work is licensed under the terms of the GNU GPL, version 2 or -# later. See the COPYING file in the top-level directory. +''' +Tesseract is an program for doing Optical Character Recognition (OCR), +which can be used in the tests to extract text from screenshots. +''' =20 import logging from subprocess import run =20 =20 -def tesseract_ocr(image_path, tesseract_args=3D''): +def tesseract_ocr(image_path): + ''' Run the tesseract OCR to extract text from a screenshot ''' console_logger =3D logging.getLogger('console') console_logger.debug(image_path) proc =3D run(['tesseract', image_path, 'stdout'], - capture_output=3DTrue, encoding=3D'utf8') + capture_output=3DTrue, encoding=3D'utf8', check=3DFalse) if proc.returncode: return None lines =3D [] --=20 2.53.0 From nobody Mon May 25 13:47:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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bh=F4/PW9AX1SjdG091xg18qEgQhoURcREzm5rwdhlIg+A=; b=KyKOXd4FqduSyGLtASby2jnyJi+qu0zvDAMIxNZik6AF+wJ6cb8xoFmxripd+h8QNIaOZ/ EKGpoIN6+PGKzeCm1U9O6Z3vcFbaf7ZhsaKc6ma7QDAy5k0Y9kEoeGIU7mfM6NcpshfN0S Ky13B20e0e0Q7Ufp15IxM2o4ANvhI8Y= X-MC-Unique: zedaxh50O-2-XZY2BpetJg-1 X-Mimecast-MFC-AGG-ID: zedaxh50O-2-XZY2BpetJg_1777283897 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Luc Michel , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 07/10] hw/core/register: add register_array_get_owner Date: Mon, 27 Apr 2026 11:57:44 +0200 Message-ID: <20260427095747.1070244-8-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283963465154100 From: Luc Michel Add the register_array_get_owner function to the register API. This function can be used to retrieve the device owning the given RegisterInfoArray. This was previously done inline by some devices. 5c6367bc1c8850f74812eeaaf87cff9911be58de modified the way register blocks are created and parented to the device. Since this is an implementation detail of the register API, it makes sense to have a function for this. Use it in the Versal OSPI and Versal/ZynqMP eFuse models instead of tinkering with the API internals. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3421 Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3422 Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3423 Signed-off-by: Luc Michel Tested-by: Thomas Huth Reviewed-by: Alistair Francis Fixes: 5c6367bc1c8 ("hw/core/register: add the REGISTER_ARRAY type") Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260424155646.533334-1-luc.michel@amd.com> Signed-off-by: Thomas Huth --- include/hw/core/register.h | 11 +++++++++++ hw/core/register.c | 5 +++++ hw/nvram/xlnx-versal-efuse-ctrl.c | 4 ++-- hw/nvram/xlnx-zynqmp-efuse.c | 4 ++-- hw/ssi/xlnx-versal-ospi.c | 10 +++------- 5 files changed, 23 insertions(+), 11 deletions(-) diff --git a/include/hw/core/register.h b/include/hw/core/register.h index 1f265f4ed71..c6f648fe95e 100644 --- a/include/hw/core/register.h +++ b/include/hw/core/register.h @@ -209,4 +209,15 @@ RegisterInfoArray *register_init_block64(DeviceState *= owner, bool debug_enabled, uint64_t memory_size); =20 +/** + * register_array_get_owner + * + * Retrieve the device owning the register info array @reg_array. + * + * @reg_array The register info array to retrieve the owner from + * + * Returns: the device owning @reg_array + */ +DeviceState *register_array_get_owner(const RegisterInfoArray *reg_array); + #endif diff --git a/hw/core/register.c b/hw/core/register.c index c3f3c936e70..99ca5e17758 100644 --- a/hw/core/register.c +++ b/hw/core/register.c @@ -322,6 +322,11 @@ static void register_array_finalize(Object *obj) g_free(r_array->r); } =20 +DeviceState *register_array_get_owner(const RegisterInfoArray *reg_array) +{ + return DEVICE(OBJECT(reg_array)->parent); +} + static const TypeInfo register_array_info =3D { .name =3D TYPE_REGISTER_ARRAY, .parent =3D TYPE_OBJECT, diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse= -ctrl.c index 69acdfa3047..f5d5587cb65 100644 --- a/hw/nvram/xlnx-versal-efuse-ctrl.c +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c @@ -619,11 +619,11 @@ static void efuse_ctrl_reg_write(void *opaque, hwaddr= addr, { RegisterInfoArray *reg_array =3D opaque; XlnxVersalEFuseCtrl *s; - Object *dev; + DeviceState *dev; =20 assert(reg_array !=3D NULL); =20 - dev =3D reg_array->mem.owner; + dev =3D register_array_get_owner(reg_array); assert(dev); =20 s =3D XLNX_VERSAL_EFUSE_CTRL(dev); diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c index e6bc54fc6bd..028120f824d 100644 --- a/hw/nvram/xlnx-zynqmp-efuse.c +++ b/hw/nvram/xlnx-zynqmp-efuse.c @@ -724,11 +724,11 @@ static void zynqmp_efuse_reg_write(void *opaque, hwad= dr addr, { RegisterInfoArray *reg_array =3D opaque; XlnxZynqMPEFuse *s; - Object *dev; + DeviceState *dev; =20 assert(reg_array !=3D NULL); =20 - dev =3D reg_array->mem.owner; + dev =3D register_array_get_owner(reg_array); assert(dev); =20 s =3D XLNX_ZYNQMP_EFUSE(dev); diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c index 467f0ce7033..e25e4c26c2e 100644 --- a/hw/ssi/xlnx-versal-ospi.c +++ b/hw/ssi/xlnx-versal-ospi.c @@ -1569,15 +1569,11 @@ static RegisterAccessInfo ospi_regs_info[] =3D { }; =20 /* Return dev-obj from reg-region created by register_init_block32 */ -static XlnxVersalOspi *xilinx_ospi_of_mr(void *mr_accessor) +static XlnxVersalOspi *xilinx_ospi_of_mr(void *opaque) { - RegisterInfoArray *reg_array =3D mr_accessor; - Object *dev; + RegisterInfoArray *reg_array =3D REGISTER_ARRAY(opaque); =20 - dev =3D reg_array->mem.owner; - assert(dev); - - return XILINX_VERSAL_OSPI(dev); + return XILINX_VERSAL_OSPI(register_array_get_owner(reg_array)); } =20 static void ospi_write(void *opaque, hwaddr addr, uint64_t value, --=20 2.53.0 From nobody Mon May 25 13:47:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1777283990; cv=none; d=zohomail.com; s=zohoarc; b=SNz6NCIuPJzNOXvGpwsmcCziaF1/Gud/QYCvKGoR03O7CPzvj/WAGlcblbjs79XRKxLztwud2Gb6+8fSyy7L8TjPstJKjCwfrTMkBvx6lHJm9d91/5ZGIcF4ixfTN0+wAdjS8wk2dzbodGuUR1Y6tKqfdkqE4tyCRhD6KFOGJGE= ARC-Message-Signature: i=1; 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Mon, 27 Apr 2026 09:58:19 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.44.48.146]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id DC6CC3000707; Mon, 27 Apr 2026 09:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777283904; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eFljm/P3eCUbucxFKDa5ngURwEtaHUriqo3+3248PFA=; b=HQgYZyNHGbU+ZdiHwIqPe4ZYGSTvq5yCor/MguKEl2g9wMHA0QYwE3PhMDC9bvSj3xTEn+ xxHE4ZjzzZq4Wse68TYdRqO+hr+Uezjtv5jop+Krn+lsME/lZqqnIbCexRjd2h/iiiqkvR T7jTH5GbBvWbae7qiCqyxF6450ay/Ek= X-MC-Unique: qbTtMEC1NXiyxGYl5HWiqA-1 X-Mimecast-MFC-AGG-ID: qbTtMEC1NXiyxGYl5HWiqA_1777283899 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Sourish Duttta Sharma Subject: [PULL 08/10] hw/i386/fw_cfg: Use g_new() and g_new0() instead of g_malloc() Date: Mon, 27 Apr 2026 11:57:45 +0200 Message-ID: <20260427095747.1070244-9-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283992322158500 Content-Type: text/plain; charset="utf-8" From: Sourish Dutta Sharma Replace g_malloc() and g_malloc0() calls that calculate the allocation size using sizeof() with the type-safe g_new() and g_new0() macros. This aligns the code with QEMU's coding style guidelines, improving readability and protecting against potential integer overflow vulnerabilities when allocating arrays. Signed-off-by: Sourish Duttta Sharma Message-ID: <20260224160020.137036-1-sourishduttasharma770@gmail.com> Signed-off-by: Thomas Huth --- hw/i386/fw_cfg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index 858e6ca9c53..2876490f069 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -91,7 +91,7 @@ void fw_cfg_build_smbios(PCMachineState *pcms, FWCfgState= *fw_cfg, =20 /* build the array of physical mem area from e820 table */ nr_e820 =3D e820_get_table(NULL); - mem_array =3D g_malloc0(sizeof(*mem_array) * nr_e820); + mem_array =3D g_new0(struct smbios_phys_mem_area, nr_e820); for (i =3D 0, array_count =3D 0; i < nr_e820; i++) { uint64_t addr, len; =20 @@ -207,7 +207,7 @@ void fw_cfg_build_feature_control(MachineState *ms, FWC= fgState *fw_cfg) return; } =20 - val =3D g_malloc(sizeof(*val)); + val =3D g_new(uint64_t, 1); *val =3D cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777283907; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e9zpsbG1qaE8A7Go/+EGU6gSYRamjFD7eQhgj5ujaP8=; b=EJEv/XdzpyespNUu2fDjEPMnUMlkZxTumkTG8jLh1Geis7Te8Wq+SE70fYf+44GRW60+CY N7rgiQC6Q8b9yw3rndigFLRMkr/HbcE1oq5LqF5ddmDNC2Gm1YiMULqX0U+ZVkN+bb8dFz Vnd1ITTndcnghpH1oPOVdKt5JLja1FY= X-MC-Unique: IOfPhE-jPY-P1JzASh1iww-1 X-Mimecast-MFC-AGG-ID: IOfPhE-jPY-P1JzASh1iww_1777283904 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, Dmitry Frolov , Max Filippov Subject: [PULL 09/10] target/xtensa: Replace malloc() with g_strdup_printf() Date: Mon, 27 Apr 2026 11:57:46 +0200 Message-ID: <20260427095747.1070244-10-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283946175158500 Content-Type: text/plain; charset="utf-8" From: Dmitry Frolov malloc() return value is used without a check. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Dmitry Frolov Reviewed-by: Max Filippov Message-ID: <20250730062142.1665980-1-frolov@swemel.ru> Signed-off-by: Thomas Huth --- target/xtensa/translate.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 6f9dd9fb5cf..175fd4b5cfc 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -112,17 +112,12 @@ void xtensa_collect_sr_names(const XtensaConfig *conf= ig) =20 if (*pname) { if (strstr(*pname, name) =3D=3D NULL) { - char *new_name =3D - malloc(strlen(*pname) + strlen(name) + 2); - - strcpy(new_name, *pname); - strcat(new_name, "/"); - strcat(new_name, name); - free(*pname); + char *new_name =3D g_strdup_printf("%s/%s", *pname, na= me); + g_free(*pname); *pname =3D new_name; } } else { - *pname =3D strdup(name); + *pname =3D g_strdup(name); } } } --=20 2.53.0 From nobody Mon May 25 13:47:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777283909; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ILwZ7gBkC8za9+N5E8PGnU+HMw/r8pM+wU6P+mH1Bc8=; b=DRAgF48fzJM77CNzFrPiArfSsaV8Igkllk2otges4oaTpT0bQPPHu2qUcvplzrB3vcBKIb HNhEAHz2bDrc40eSxG4rqBkTCNEwu32zQSUHgoezByjh1nJ6xXqonKqJWfPy9qTVrkMlhR CTWeuOhyD5s6CW1ykwXkfkjkhQRZDvI= X-MC-Unique: G27-2xdwP0e7_weHpUrCpw-1 X-Mimecast-MFC-AGG-ID: G27-2xdwP0e7_weHpUrCpw_1777283906 From: Thomas Huth To: Stefan Hajnoczi Cc: qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 10/10] tests/functional/ppc/test_ppe42: Fix warning from the latest version of pylint Date: Mon, 27 Apr 2026 11:57:47 +0200 Message-ID: <20260427095747.1070244-11-thuth@redhat.com> In-Reply-To: <20260427095747.1070244-1-thuth@redhat.com> References: <20260427095747.1070244-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1777283930034158500 From: Thomas Huth The pylint from Fedora 44 found a new issue in this test: tests/functional/ppc/test_ppe42.py:63:20: W0101: Unreachable code (unreach= able) And indeed, the "break" is unreachable since the previous self.fail() always aborts immediately. Thus let's remove the "break" to make pylint happy again. Message-ID: <20260427080731.389061-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Thomas Huth --- tests/functional/ppc/test_ppe42.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/functional/ppc/test_ppe42.py b/tests/functional/ppc/test= _ppe42.py index 7b360a40a54..53958a7938d 100755 --- a/tests/functional/ppc/test_ppe42.py +++ b/tests/functional/ppc/test_ppe42.py @@ -60,7 +60,6 @@ def _wait_pass_fail(self, timeout): self.log.debug(f"Execution stopped: {e}") self.log.debug("Exiting due to test failure") self.fail("Failure detected!") - break else: self.fail("Timed out waiting for test completion.") =20 --=20 2.53.0