[v4] monitor: Remove need of per-target handlers

[PATCH v4 20/32] target/riscv: Register target_get_monitor_def in SysemuCPUOps

Posted by Philippe Mathieu-Daudé 2 months, 3 weeks ago

Rename target_get_monitor_def() as riscv_monitor_get_register_legacy()
and register it as SysemuCPUOps::monitor_get_register() handler.
Take care to sign-extend values for 32-bit HARTs.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/internals.h |  3 +++
 target/riscv/cpu.c       |  1 +
 target/riscv/monitor.c   | 11 +++++++----
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 35b923c4bf5..47becca37f2 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -233,4 +233,7 @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
+                                      int64_t *pval);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8ac935ac06e..dbd88fa6655 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2720,6 +2720,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
     .write_elf64_note = riscv_cpu_write_elf64_note,
     .write_elf32_note = riscv_cpu_write_elf32_note,
+    .monitor_get_register = riscv_monitor_get_register_legacy,
     .legacy_vmsd = &vmstate_riscv_cpu,
 };
 #endif
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index bca04a7580c..3898595a3cb 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -27,6 +27,7 @@
 #include "monitor/hmp.h"
 #include "monitor/hmp-target.h"
 #include "system/memory.h"
+#include "internals.h"
 
 #ifdef TARGET_RISCV64
 #define PTE_HEADER_FIELDS       "vaddr            paddr            "\
@@ -311,16 +312,18 @@ static bool reg_is_vreg(const char *name)
     return false;
 }
 
-int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
+int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
+                                      int64_t *pval)
 {
-    CPURISCVState *env = &RISCV_CPU(cs)->env;
+    RISCVCPU *hart = RISCV_CPU(cs);
+    CPURISCVState *env = cpu_env(cs);
     target_ulong val = 0;
     uint64_t val64 = 0;
     int i;
 
     if (reg_is_ulong_integer(env, name, &val, false) ||
         reg_is_ulong_integer(env, name, &val, true)) {
-        *pval = val;
+        *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
         return 0;
     }
 
@@ -369,7 +372,7 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
          * to do the filtering of the registers that are present.
          */
         if (res == RISCV_EXCP_NONE) {
-            *pval = val;
+            *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
             return 0;
         }
     }
-- 
2.53.0

Re: [PATCH v4 20/32] target/riscv: Register target_get_monitor_def in SysemuCPUOps

Posted by Alistair Francis 2 months, 3 weeks ago

On Mon, Apr 27, 2026 at 6:11 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Rename target_get_monitor_def() as riscv_monitor_get_register_legacy()
> and register it as SysemuCPUOps::monitor_get_register() handler.
> Take care to sign-extend values for 32-bit HARTs.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/internals.h |  3 +++
>  target/riscv/cpu.c       |  1 +
>  target/riscv/monitor.c   | 11 +++++++----
>  3 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index 35b923c4bf5..47becca37f2 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -233,4 +233,7 @@ static inline int insn_len(uint16_t first_word)
>      return (first_word & 3) == 3 ? 4 : 2;
>  }
>
> +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
> +                                      int64_t *pval);
> +
>  #endif
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8ac935ac06e..dbd88fa6655 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2720,6 +2720,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
>      .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
>      .write_elf64_note = riscv_cpu_write_elf64_note,
>      .write_elf32_note = riscv_cpu_write_elf32_note,
> +    .monitor_get_register = riscv_monitor_get_register_legacy,
>      .legacy_vmsd = &vmstate_riscv_cpu,
>  };
>  #endif
> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> index bca04a7580c..3898595a3cb 100644
> --- a/target/riscv/monitor.c
> +++ b/target/riscv/monitor.c
> @@ -27,6 +27,7 @@
>  #include "monitor/hmp.h"
>  #include "monitor/hmp-target.h"
>  #include "system/memory.h"
> +#include "internals.h"
>
>  #ifdef TARGET_RISCV64
>  #define PTE_HEADER_FIELDS       "vaddr            paddr            "\
> @@ -311,16 +312,18 @@ static bool reg_is_vreg(const char *name)
>      return false;
>  }
>
> -int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
> +int riscv_monitor_get_register_legacy(CPUState *cs, const char *name,
> +                                      int64_t *pval)
>  {
> -    CPURISCVState *env = &RISCV_CPU(cs)->env;
> +    RISCVCPU *hart = RISCV_CPU(cs);
> +    CPURISCVState *env = cpu_env(cs);
>      target_ulong val = 0;
>      uint64_t val64 = 0;
>      int i;
>
>      if (reg_is_ulong_integer(env, name, &val, false) ||
>          reg_is_ulong_integer(env, name, &val, true)) {
> -        *pval = val;
> +        *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
>          return 0;
>      }
>
> @@ -369,7 +372,7 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
>           * to do the filtering of the registers that are present.
>           */
>          if (res == RISCV_EXCP_NONE) {
> -            *pval = val;
> +            *pval = riscv_cpu_is_32bit(hart) ? (int32_t)val : val;
>              return 0;
>          }
>      }
> --
> 2.53.0
>
>