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([180.233.125.15]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8ebba485sm36307102b3a.38.2026.04.26.06.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 06:49:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777211396; x=1777816196; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xlytXwevs67gNFcr4ujyMnKHEGjQPMghBz+4SCH2y1E=; b=rlYK4HFapxxU61YSLBWquYxKAdV83KqThs1zA2qf4qXthQATjPPzbxRLxZ2Xn0C5Nj 4cSF65xH2t1xn6/M2/udTyelID7P1czxCBy1N4G2I/SUy5Bh3F6s3Vvm1SjQc3czRgSl 5u+3xyKYL2EyzT2/BGOpcpDK3lP2s2suECBAI5pK1qk0DmYGzP3uJgZeLf+0dbpvq8sO DUld/xedPlDw01OHpSKfG9zj+5h7shi93Cee2otyVudGV4edj36mIC9rh9MLONky4ewl tjUU7ItmLbGvGdFRKhJUZ+Z0Y86yUnVIHh53fP3hUfJ+LOWpMYKPgh7aNdwytir7mjxI JD3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777211396; x=1777816196; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=xlytXwevs67gNFcr4ujyMnKHEGjQPMghBz+4SCH2y1E=; b=frgj9au3ALPriR2kZMbRQxFclBJwcopIG0AxQ97v1zTsrJ6BRpeoVjos9p8Y5AoCk0 SaolevBG212ABcCeYfLcn/kyLkMXErNhBNKdcTrdQAQ4FAHmMwTWrFSWd6z6UOkV+IZz ZJhSNqqcqddudUHNm7RCyFxcN97kDPCNc05hVU6CsEAidb1CMTLmSTqdvf0EFjtXJMfe Vf6rx6IEq4FJ1Vi6oUpRf+vABiUl8eTvZ0cAZPj1ln7yj51shI5mv211neLuO2DoNFNU GQpPo+Ar7KkCWKfLM1MWc0Sqn6+lVAVh+70/RlKl6hX/+taD0d+MDs746PmOlIKCtLYO TAZg== X-Gm-Message-State: AOJu0Yy+2Mtvn+iVoKnxq/A9UdaZCQ867lXwsN/tQoUzUI4bGlcrI0Pk dnLIjOuVoDdumjrtMqhIjTuMlAVtvKNTQf9t+CRGRua64JBE/LYBl7/d6hRiY51R+kR4nh2dMe0 +GcS5y6s= X-Gm-Gg: AeBDieu+fOk4ZQFOUMXxBNDI0dUhxDEUhJ28X+NyK5LPwccRJ8IsbuiWcAzRVh34G97 xs24fJ6+XrAVDKMKsdChvGaj0b8jc3omsQPSdpVAuM3EvW8WFHOYYx6QwgkFW0aUzfm9ofOeo73 Fn95jOhep57JMO0waRXKa0MZScieu/zQuhG5pF01ZIGRLVy6mx2KMzFVEZByu5qHEMIMK4RJx+y qrs0P9ol1q515pGj8iGXx3dp8o7aq7kLS8+G4JNf871UBKYM99UM547rWyLxxQaXH95/fJozThX h3527m6foblKeXqJh6MGxlUU7YEX8G1/qvQpCd4s6vgWI00Wdnxj86auWzuxob/ZnTeQuG8bMYq pRZPTVuisZGI1untgj5R3+HuI71ZWk3LJ8XuwY8REKgvYj1o3Wyoh0XEhS4X2UYTSn/Tf9U7IxU DZwUqiIjbqmSdGn2rb1gUhQD5QTtQEWnZSeQnifnrQ X-Received: by 2002:a05:6a00:408e:b0:827:2a07:231d with SMTP id d2e1a72fcca58-82f8c839c08mr41148041b3a.17.1777211396516; Sun, 26 Apr 2026 06:49:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 82/84] target/arm: Use FloatParts64 in bfdotadd_ebf Date: Sun, 26 Apr 2026 23:39:59 +1000 Message-ID: <20260426134002.865628-83-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260426134002.865628-1-richard.henderson@linaro.org> References: <20260426134002.865628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777211594250158500 Content-Type: text/plain; charset="utf-8" Use softfloat-parts.h so that we can more naturally perform the required operations witha single rounding step. This happens to also simplify the NaN detection step. Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 77 +++++++++++++++++++------------------ 1 file changed, 40 insertions(+), 37 deletions(-) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 91e98d28ae..1f305515cf 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -22,6 +22,7 @@ #include "helper.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" +#include "fpu/softfloat-parts.h" #include "qemu/int128.h" #include "crypto/clmul.h" #include "vec_internal.h" @@ -2895,61 +2896,63 @@ float32 bfdotadd(float32 sum, uint32_t e1, uint32_t= e2, float_status *fpst) float32 bfdotadd_ebf(float32 sum, uint32_t e1, uint32_t e2, float_status *fpst, float_status *fpst_odd) { + /* Unpack two BFloat16 into two Float32, trivially. */ float32 s1r =3D e1 << 16; float32 s1c =3D e1 & 0xffff0000u; float32 s2r =3D e2 << 16; float32 s2c =3D e2 & 0xffff0000u; float32 t32; =20 + /* + * Compare f16_dotadd() in sme_helper.c, but here we have + * bfloat16 inputs. In particular that means that we do not + * want the FPCR.FZ16 flush semantics, so we use the normal + * float_status for the input handling here. + */ + FloatParts64 p1r =3D float32_unpack_canonical(s1r, fpst); + FloatParts64 p1c =3D float32_unpack_canonical(s1c, fpst); + FloatParts64 p2r =3D float32_unpack_canonical(s2r, fpst); + FloatParts64 p2c =3D float32_unpack_canonical(s2c, fpst); + + int all_mask =3D (float_cmask(p1r.cls) | float_cmask(p1c.cls) | + float_cmask(p1r.cls) | float_cmask(p1c.cls)); + /* C.f. FPProcessNaNs4 */ - if (float32_is_any_nan(s1r) || float32_is_any_nan(s1c) || - float32_is_any_nan(s2r) || float32_is_any_nan(s2c)) { - if (float32_is_signaling_nan(s1r, fpst)) { - t32 =3D s1r; - } else if (float32_is_signaling_nan(s1c, fpst)) { - t32 =3D s1c; - } else if (float32_is_signaling_nan(s2r, fpst)) { - t32 =3D s2r; - } else if (float32_is_signaling_nan(s2c, fpst)) { - t32 =3D s2c; - } else if (float32_is_any_nan(s1r)) { - t32 =3D s1r; - } else if (float32_is_any_nan(s1c)) { - t32 =3D s1c; - } else if (float32_is_any_nan(s2r)) { - t32 =3D s2r; + if (unlikely(all_mask & float_cmask_anynan)) { + if (unlikely(all_mask & float_cmask_snan)) { + if (p1r.cls =3D=3D float_class_snan) { + t32 =3D s1r; + } else if (p1c.cls =3D=3D float_class_snan) { + t32 =3D s1c; + } else if (p2r.cls =3D=3D float_class_snan) { + t32 =3D s2r; + } else { + t32 =3D s2c; + } } else { - t32 =3D s2c; + if (p1r.cls =3D=3D float_class_qnan) { + t32 =3D s1r; + } else if (p1c.cls =3D=3D float_class_qnan) { + t32 =3D s1c; + } else if (p2r.cls =3D=3D float_class_qnan) { + t32 =3D s2r; + } else { + t32 =3D s2c; + } } /* * FPConvertNaN(FPProcessNaN(t32)) will be done as part * of the final addition below. */ } else { - /* - * Compare f16_dotadd() in sme_helper.c, but here we have - * bfloat16 inputs. In particular that means that we do not - * want the FPCR.FZ16 flush semantics, so we use the normal - * float_status for the input handling here. - */ - float64 e1r =3D float32_to_float64(s1r, fpst); - float64 e1c =3D float32_to_float64(s1c, fpst); - float64 e2r =3D float32_to_float64(s2r, fpst); - float64 e2c =3D float32_to_float64(s2c, fpst); - float64 t64; - /* * The ARM pseudocode function FPDot performs both multiplies - * and the add with a single rounding operation. Emulate this - * by performing the first multiply in round-to-odd, then doing - * the second multiply as fused multiply-add, and rounding to - * float32 all in one step. + * and the add with a single rounding operation. */ - t64 =3D float64_mul(e1r, e2r, fpst_odd); - t64 =3D float64r32_muladd(e1c, e2c, t64, 0, fpst); + FloatParts64 tmp =3D parts64_mul(&p1r, &p2r, fpst); + tmp =3D parts64_muladd_scalbn(&p1c, &p2c, &tmp, 0, 0, fpst); =20 - /* This conversion is exact, because we've already rounded. */ - t32 =3D float64_to_float32(t64, fpst); + t32 =3D float32_round_pack_canonical(&tmp, fpst); } =20 /* The final accumulation step is not fused. */ --=20 2.43.0