From nobody Tue Jul 28 16:55:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1777211856; cv=none; d=zohomail.com; s=zohoarc; b=OGmdFptguDxQMYvIwzBd1SmSeZHWd/wHbkuRHJBQeN67Nbe7zbt8AxYWgsZVLHP0CdWwHRdS7eEYX+5BmNdISe7lqsDyPl/9c6oYtUJ7/e925ql1F4cBHu3olohf4xYalSJCKwC524Dx3Ph2x3/+npg3WqoAvXcYp4Vv8NPm5bY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1777211856; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Qi2pCl7ZHfYdZTkVL3nvBP0b2n/j7SskgSjhFZXGku4=; b=bR/YBQO0k2VifWIU3ORBY1MK4KnyFQNNoGQdr8A+d2ygVYPugdmcTgKF5JYK2pW4IqRcARoyisFqvd29Wi94aIiFh9HRjrgYEcUmXIxLaiQ0EoofI75JCVQvo+97dIjPLH3qKSTvjxfHprpwYlIlm0ApITeyK8ORaotsNw64RUE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1777211856222722.5306431285715; Sun, 26 Apr 2026 06:57:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wGzpi-0000Xl-DN; Sun, 26 Apr 2026 09:47:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wGzof-0006IO-SY for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:35 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wGzod-0001lZ-FI for qemu-devel@nongnu.org; Sun, 26 Apr 2026 09:46:33 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2b7d3ecc10dso14946895ad.2 for ; Sun, 26 Apr 2026 06:46:31 -0700 (PDT) Received: from stoup.. ([180.233.125.15]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b5faa34ea7sm280544085ad.34.2026.04.26.06.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 06:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1777211190; x=1777815990; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qi2pCl7ZHfYdZTkVL3nvBP0b2n/j7SskgSjhFZXGku4=; b=isfU3Vvvxl7MCb5Qt8akEoxdnD9eJPkR2O/EgQvvWMvp0jWiTM2cqZqIyicfLQnMd+ ZzrijjIWkxElsiesRHrJSh/P5H8iq/Ct1zVqS8TBInE+nb0cnFa2KWAVIEmoaZz2Ol0A lWQegu+KZLqn3P5kjQD6OmORcqe36trJO+dSUAec80AYMb6MSP0clrsg7TquITophji8 6fWkHQCnnbyBM/7RuCRFjgbekijK44G3nMdDsP8fBz9KXG4kRSk5d/2L2l8A+ySBNn84 TbQMljrbzpDtfWc8a92forcK6aQDuR4DIYizxqmFw/5HTxlnZ6V7LcxC4gWPpeFyFpj/ Wvhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777211190; x=1777815990; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Qi2pCl7ZHfYdZTkVL3nvBP0b2n/j7SskgSjhFZXGku4=; b=YDvzidsDQapwEvwq9xZBe9vF7BB/pQsse1UExm/S93lmbb/OvTwLkNmERGRxCp/lJW um+X+Tfx2/QbCxq8SQgRwLz66vMBtactcE21qaOFTJBnMUf19PbbTXlBjIkshzgi1Lnm 2YJn60LAImOdvUmTbotqVaWosmCSQTdfuFpB8JmaMRTKu2JsZOWAXtUoIgZX9i8/H6eJ sSJWQEYjzZ229+5vnPEbKvgGfMgDyb1lGijtlcl/j6P+MmbQuvB/WBvGoIymnIYjyBRc MtnBn4/6aPhxn6rdd0KaLVIPDh8w/LFkjuPwjMAjB77qWQQo5j8dM3JupeVNIe9FeB3z 6+iA== X-Gm-Message-State: AOJu0YyGj2oS1AhobbJbb4EwGO1QHZ1TeyRtuw4guK6Er9YMC8LFsVVn Mlb48lRq3z1owyg5hCzijUMi/xacBIK5/3e3ZCv2hX7hZDwgScWxlDCkjRJ5jLhZ+EndYxM80jJ Ie68n5PI= X-Gm-Gg: AeBDievVaW9KKHnhXD9WaNkI1LMkIO1adak+ATmLGysndHaQYhlNczF6phFWdYxrtBW pw4/du6LdawcCQxfVtlvNZXp5hUHp6G62++MrFNbUF/NuncbUM0FyOro+xuQ3SlKaVSqu2Jg4Q9 bY1oqSGkR5viPJMgaRtxCNv2r1TsqnBKtGXgM6Aquxq3EpGEFt8EpID5iFKHDlvqYZOMXxbqbnA x6aiDz3d0SLDiIdNJL9pmIta6e9h/udePjiWk/84i2kcLOoA8wAzdeOFq0fAb0acZVkmDTBGI4t wAb50zGxPfFE4QQzOtBPb6W8aD6oVtN6FL+zxs4JLQUfVlMQk8q6Dro5tAMY1QShtXE+Pm2mva5 rxD+19M6sKVQGKBWuJl3ZVXERVI2ar8KPQ9ny0FxIo80u6wy1zVjSd/xFmPiKd7YJ6UviwFEBed fisFnjzC4pDribiu6pHxBwZpbFuIysgOjxynPqWEwy X-Received: by 2002:a17:902:ebc5:b0:2b0:62dd:3a80 with SMTP id d9443c01a7336-2b5f9ee30aamr381425155ad.17.1777211189920; Sun, 26 Apr 2026 06:46:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 74/84] fpu: Return struct from parts{64,128}_muladd_scalbn Date: Sun, 26 Apr 2026 23:39:51 +1000 Message-ID: <20260426134002.865628-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260426134002.865628-1-richard.henderson@linaro.org> References: <20260426134002.865628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777211857151158500 Content-Type: text/plain; charset="utf-8" At the same time, export. Signed-off-by: Richard Henderson --- include/fpu/softfloat-parts.h | 9 +++ fpu/softfloat.c | 81 ++++++++++--------- fpu/softfloat-parts.c.inc | 148 +++++++++++++++++----------------- 3 files changed, 122 insertions(+), 116 deletions(-) diff --git a/include/fpu/softfloat-parts.h b/include/fpu/softfloat-parts.h index 5b71809541..6416495eac 100644 --- a/include/fpu/softfloat-parts.h +++ b/include/fpu/softfloat-parts.h @@ -184,6 +184,15 @@ FloatParts64 parts64_div(const FloatParts64 *a, const = FloatParts64 *b, FloatParts128 parts128_div(const FloatParts128 *a, const FloatParts128 *b, float_status *s); =20 +FloatParts64 parts64_muladd_scalbn(const FloatParts64 *a, + const FloatParts64 *b, + const FloatParts64 *c, + int scale, int flags, float_status *s); +FloatParts128 parts128_muladd_scalbn(const FloatParts128 *a, + const FloatParts128 *b, + const FloatParts128 *c, + int scale, int flags, float_status *s= ); + void parts64_round_canonical(FloatParts64 *p, float_status *s, const FloatFmt *fmt); =20 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 1423695a5a..959a82636b 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1904,15 +1904,15 @@ float16_muladd_scalbn(float16 a, float16 b, float16= c, FloatParts64 pa =3D float16_unpack_canonical(a, status); FloatParts64 pb =3D float16_unpack_canonical(b, status); FloatParts64 pc =3D float16_unpack_canonical(c, status); - FloatParts64 *pr =3D - parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags, status); + FloatParts64 pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, + scale, flags, status); =20 /* Round before applying negate result. */ - parts64_uncanon(pr, status, &float16_params, false); - if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) { - pr->sign ^=3D 1; + parts64_uncanon(&pr, status, &float16_params, false); + if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) { + pr.sign ^=3D 1; } - return pack_raw64(pr, &float16_params); + return pack_raw64(&pr, &float16_params); } =20 float16 float16_muladd(float16 a, float16 b, float16 c, @@ -1928,14 +1928,15 @@ float32_muladd_scalbn(float32 a, float32 b, float32= c, FloatParts64 pa =3D float32_unpack_canonical(a, status); FloatParts64 pb =3D float32_unpack_canonical(b, status); FloatParts64 pc =3D float32_unpack_canonical(c, status); - FloatParts64 *pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags= , status); + FloatParts64 pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, + scale, flags, status); =20 /* Round before applying negate result. */ - parts64_uncanon(pr, status, &float32_params, false); - if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) { - pr->sign ^=3D 1; + parts64_uncanon(&pr, status, &float32_params, false); + if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) { + pr.sign ^=3D 1; } - return pack_raw64(pr, &float32_params); + return pack_raw64(&pr, &float32_params); } =20 float64 QEMU_SOFTFLOAT_ATTR @@ -1945,14 +1946,15 @@ float64_muladd_scalbn(float64 a, float64 b, float64= c, FloatParts64 pa =3D float64_unpack_canonical(a, status); FloatParts64 pb =3D float64_unpack_canonical(b, status); FloatParts64 pc =3D float64_unpack_canonical(c, status); - FloatParts64 *pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, scale, flags= , status); + FloatParts64 pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, + scale, flags, status); =20 /* Round before applying negate result. */ - parts64_uncanon(pr, status, &float64_params, false); - if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) { - pr->sign ^=3D 1; + parts64_uncanon(&pr, status, &float64_params, false); + if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) { + pr.sign ^=3D 1; } - return pack_raw64(pr, &float64_params); + return pack_raw64(&pr, &float64_params); } =20 static bool force_soft_fma; @@ -2102,14 +2104,14 @@ float64 float64r32_muladd(float64 a, float64 b, flo= at64 c, FloatParts64 pa =3D float64_unpack_canonical(a, status); FloatParts64 pb =3D float64_unpack_canonical(b, status); FloatParts64 pc =3D float64_unpack_canonical(c, status); - FloatParts64 *pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, st= atus); + FloatParts64 pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, sta= tus); =20 /* Round before applying negate result. */ - parts64_uncanon(pr, status, &float32_params, false); - if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) { - pr->sign ^=3D 1; + parts64_uncanon(&pr, status, &float32_params, false); + if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) { + pr.sign ^=3D 1; } - return float64r32_pack_raw(pr); + return float64r32_pack_raw(&pr); } =20 bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, @@ -2118,14 +2120,14 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, b= float16 b, bfloat16 c, FloatParts64 pa =3D bfloat16_unpack_canonical(a, status); FloatParts64 pb =3D bfloat16_unpack_canonical(b, status); FloatParts64 pc =3D bfloat16_unpack_canonical(c, status); - FloatParts64 *pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, st= atus); + FloatParts64 pr =3D parts64_muladd_scalbn(&pa, &pb, &pc, 0, flags, sta= tus); =20 /* Round before applying negate result. */ - parts64_uncanon(pr, status, &bfloat16_params, false); - if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) { - pr->sign ^=3D 1; + parts64_uncanon(&pr, status, &bfloat16_params, false); + if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) { + pr.sign ^=3D 1; } - return pack_raw64(pr, &bfloat16_params); + return pack_raw64(&pr, &bfloat16_params); } =20 float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c, @@ -2134,14 +2136,14 @@ float128 QEMU_FLATTEN float128_muladd(float128 a, f= loat128 b, float128 c, FloatParts128 pa =3D float128_unpack_canonical(a, status); FloatParts128 pb =3D float128_unpack_canonical(b, status); FloatParts128 pc =3D float128_unpack_canonical(c, status); - FloatParts128 *pr =3D parts128_muladd_scalbn(&pa, &pb, &pc, 0, flags, = status); + FloatParts128 pr =3D parts128_muladd_scalbn(&pa, &pb, &pc, 0, flags, s= tatus); =20 /* Round before applying negate result. */ - parts128_uncanon(pr, status, &float128_params, false); - if ((flags & float_muladd_negate_result) && !is_nan(pr->cls)) { - pr->sign ^=3D 1; + parts128_uncanon(&pr, status, &float128_params, false); + if ((flags & float_muladd_negate_result) && !is_nan(pr.cls)) { + pr.sign ^=3D 1; } - return float128_pack_raw(pr); + return float128_pack_raw(&pr); } =20 /* @@ -5113,7 +5115,7 @@ float32 float32_exp2(float32 a, float_status *status) rp =3D float64_unpack_canonical(float64_one, status); for (int i =3D 0; i < 15; i++) { tp =3D float64_unpack_canonical(float32_exp2_coefficients[i], stat= us); - rp =3D *parts64_muladd_scalbn(&tp, &xnp, &rp, 0, 0, status); + rp =3D parts64_muladd_scalbn(&tp, &xnp, &rp, 0, 0, status); xnp =3D *parts64_mul(&xnp, &xp, status); } =20 @@ -5162,7 +5164,7 @@ static void parts_s390_divide_to_integer(FloatParts64= *a, FloatParts64 *b, n->sign =3D a->sign ^ b->sign; *cc =3D 0; } else { - FloatParts64 *q, q_buf, *r_precise, r_precise_buf; + FloatParts64 *q, q_buf, r_precise; int float_exception_flags =3D 0; bool is_q_smallish; uint32_t r_flags; @@ -5191,12 +5193,11 @@ static void parts_s390_divide_to_integer(FloatParts= 64 *a, FloatParts64 *b, 0, status, fmt); =20 /* Compute precise remainder */ - r_precise_buf =3D *b; - r_precise =3D parts64_muladd_scalbn(&r_precise_buf, n, a, 0, + r_precise =3D parts64_muladd_scalbn(b, n, a, 0, float_muladd_negate_product, sta= tus); =20 /* Round remainder to the target format */ - *r =3D *r_precise; + *r =3D r_precise; status->float_exception_flags =3D 0; parts64_round_canonical(r, status, fmt); r_flags =3D status->float_exception_flags; @@ -5220,17 +5221,17 @@ static void parts_s390_divide_to_integer(FloatParts= 64 *a, FloatParts64 *b, * toward zero) or incremented. */ saved_r_sign =3D r->sign; - saved_r_precise_sign =3D r_precise->sign; + saved_r_precise_sign =3D r_precise.sign; r->sign =3D false; - r_precise->sign =3D false; - if (parts64_compare(r, r_precise, status, true) < + r_precise.sign =3D false; + if (parts64_compare(r, &r_precise, status, true) < float_relation_equal) { *dxc =3D 0x8; } else { *dxc =3D 0xc; } r->sign =3D saved_r_sign; - r_precise->sign =3D saved_r_precise_sign; + r_precise.sign =3D saved_r_precise_sign; } } } diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 82d59df406..ab773ed241 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -677,15 +677,15 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, Float= PartsN *b, * Requires A and C extracted into a double-sized structure to provide the * extra space for the widening multiply. */ -static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN *a, FloatPartsN *b, - FloatPartsN *c, int scale, - int flags, float_status *s) +FloatPartsN partsN(muladd_scalbn)(const FloatPartsN *a, + const FloatPartsN *b, + const FloatPartsN *c, + int scale, int flags, float_status *s) { - int ab_mask, abc_mask; - FloatPartsW p_widen, c_widen; - - ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); - abc_mask =3D float_cmask(c->cls) | ab_mask; + int ab_mask =3D float_cmask(a->cls) | float_cmask(b->cls); + int abc_mask =3D float_cmask(c->cls) | ab_mask; + bool c_sign =3D c->sign ^ !!(flags & float_muladd_negate_c); + bool p_sign =3D a->sign ^ b->sign ^ !!(flags & float_muladd_negate_pro= duct); =20 /* * It is implementation-defined whether the cases of (0,inf,qnan) @@ -694,18 +694,7 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN = *a, FloatPartsN *b, * off to the target-specific pick-a-NaN routine. */ if (unlikely(abc_mask & float_cmask_anynan)) { - *a =3D partsN(pick_nan_muladd)(a, b, c, s, ab_mask, abc_mask); - return a; - } - - if (flags & float_muladd_negate_c) { - c->sign ^=3D 1; - } - - /* Compute the sign of the product into A. */ - a->sign ^=3D b->sign; - if (flags & float_muladd_negate_product) { - a->sign ^=3D 1; + return partsN(pick_nan_muladd)(a, b, c, s, ab_mask, abc_mask); } =20 if (unlikely(!cmask_is_only_normals(ab_mask))) { @@ -715,86 +704,93 @@ static FloatPartsN *partsN(muladd_scalbn)(FloatPartsN= *a, FloatPartsN *b, } =20 if (ab_mask & float_cmask_inf) { - if (c->cls =3D=3D float_class_inf && a->sign !=3D c->sign) { + if (c->cls =3D=3D float_class_inf && p_sign !=3D c_sign) { float_raise(float_flag_invalid | float_flag_invalid_isi, s= ); goto d_nan; } - goto return_inf; + record_denormals_used(abc_mask, s); + return (FloatPartsN){ .sign =3D p_sign, .cls =3D float_class_i= nf }; } =20 - g_assert(ab_mask & float_cmask_zero); - if (is_anynorm(c->cls)) { - *a =3D *c; - goto return_normal; - } - if (c->cls =3D=3D float_class_zero) { + record_denormals_used(abc_mask, s); + + assert(ab_mask & float_cmask_zero); + switch (c->cls) { + case float_class_normal: + case float_class_denormal: + { + FloatPartsN r =3D *c; + r.exp +=3D scale; + return r; + } + + case float_class_zero: if (flags & float_muladd_suppress_add_product_zero) { - a->sign =3D c->sign; - } else if (a->sign !=3D c->sign) { + /* return zero with new sign */ + } else if (p_sign !=3D c_sign) { goto return_sub_zero; } - goto return_zero; + goto return_zero_c; + + case float_class_inf: + goto return_inf_c; + + default: + g_assert_not_reached(); } - g_assert(c->cls =3D=3D float_class_inf); } =20 + record_denormals_used(abc_mask, s); + if (unlikely(c->cls =3D=3D float_class_inf)) { - a->sign =3D c->sign; - goto return_inf; + goto return_inf_c; } =20 /* Perform the multiplication step. */ - p_widen.sign =3D a->sign; - p_widen.exp =3D a->exp + b->exp + 1; - fracN(mulw)(&p_widen, a, b); - if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) { - fracW(add)(&p_widen, &p_widen, &p_widen); - p_widen.exp -=3D 1; - } + { + FloatPartsW p_widen =3D { .sign =3D p_sign, .exp =3D a->exp + b->e= xp + 1 }; =20 - /* Perform the addition step. */ - if (c->cls !=3D float_class_zero) { - /* Zero-extend C to less significant bits. */ - fracN(widen)(&c_widen, c); - c_widen.exp =3D c->exp; + fracN(mulw)(&p_widen, a, b); + if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) { + fracW(add)(&p_widen, &p_widen, &p_widen); + p_widen.exp -=3D 1; + } =20 - if (a->sign =3D=3D c->sign) { - partsW(add_normal)(&p_widen, &c_widen); - } else if (!partsW(sub_normal)(&p_widen, &c_widen)) { - goto return_sub_zero; + /* Perform the addition step. */ + if (c->cls !=3D float_class_zero) { + /* Zero-extend C to less significant bits. */ + FloatPartsW c_widen =3D { .sign =3D c_sign, .exp =3D c->exp }; + fracN(widen)(&c_widen, c); + + if (p_widen.sign =3D=3D c_sign) { + partsW(add_normal)(&p_widen, &c_widen); + } else if (!partsW(sub_normal)(&p_widen, &c_widen)) { + goto return_sub_zero; + } + } + + /* Narrow with sticky bit, for proper rounding later. */ + { + FloatPartsN r =3D { + .sign =3D p_widen.sign, + .exp =3D p_widen.exp + scale, + .cls =3D float_class_normal, + }; + fracN(truncjam)(&r, &p_widen); + return r; } } =20 - /* Narrow with sticky bit, for proper rounding later. */ - fracN(truncjam)(a, &p_widen); - a->sign =3D p_widen.sign; - a->exp =3D p_widen.exp; - - return_normal: - a->exp +=3D scale; - finish_sign: - /* - * All result types except for "return the default NaN - * because this is an Invalid Operation" go through here; - * this matches the set of cases where we consumed a - * denormal input. - */ - record_denormals_used(abc_mask, s); - return a; + return_inf_c: + return (FloatPartsN){ .sign =3D c_sign, .cls =3D float_class_inf }; =20 return_sub_zero: - a->sign =3D s->float_rounding_mode =3D=3D float_round_down; - return_zero: - a->cls =3D float_class_zero; - goto finish_sign; - - return_inf: - a->cls =3D float_class_inf; - goto finish_sign; + c_sign =3D s->float_rounding_mode =3D=3D float_round_down; + return_zero_c: + return (FloatPartsN){ .sign =3D c_sign, .cls =3D float_class_zero }; =20 d_nan: - *a =3D partsN(default_nan)(s); - return a; + return partsN(default_nan)(s); } =20 /* --=20 2.43.0