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Sun, 26 Apr 2026 06:46:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 69/84] fpu: Introduce parts64_round_canonical Date: Sun, 26 Apr 2026 23:39:46 +1000 Message-ID: <20260426134002.865628-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260426134002.865628-1-richard.henderson@linaro.org> References: <20260426134002.865628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1777211517970158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- include/fpu/softfloat-parts.h | 7 +++++++ fpu/softfloat.c | 19 ++++++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/include/fpu/softfloat-parts.h b/include/fpu/softfloat-parts.h index 9f7ee34d6a..eb76b47934 100644 --- a/include/fpu/softfloat-parts.h +++ b/include/fpu/softfloat-parts.h @@ -175,4 +175,11 @@ FloatParts64 parts64_pick_nan(const FloatParts64 *, co= nst FloatParts64 *, FloatParts128 parts128_pick_nan(const FloatParts128 *, const FloatParts128= *, float_status *); =20 +/* + * Operations + */ + +void parts64_round_canonical(FloatParts64 *p, float_status *s, + const FloatFmt *fmt); + #endif diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e42782c656..0c931842c3 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1396,6 +1396,21 @@ float64 float64_round_pack_canonical(FloatParts64 *p= , float_status *s) return pack_raw64(p, &float64_params); } =20 +/* + * Round to Fmt while remaining canonicalized. + */ +void parts64_round_canonical(FloatParts64 *p, float_status *s, + const FloatFmt *fmt) +{ + parts64_uncanon(p, s, fmt, false); + /* + * We normally expect uncanon to be followed by pack_raw, + * so we don't actually crop the bits. Do so now. + */ + p->frac &=3D MAKE_64BIT_MASK(0, fmt->frac_size); + parts64_canonicalize(p, s, fmt); +} + static float64 float64r32_pack_raw(FloatParts64 *p) { /* @@ -5175,10 +5190,8 @@ static void parts_s390_divide_to_integer(FloatParts6= 4 *a, FloatParts64 *b, /* Round remainder to the target format */ *r =3D *r_precise; status->float_exception_flags =3D 0; - parts64_uncanon(r, status, fmt, false); + parts64_round_canonical(r, status, fmt); r_flags =3D status->float_exception_flags; - r->frac &=3D (1ULL << fmt->frac_size) - 1; - parts64_canonicalize(r, status, fmt); =20 /* POp table "Results: DIVIDE TO INTEGER (Part 2 of 2)" */ if (is_q_smallish) { --=20 2.43.0