Hi; here's the first arm pullreq for the 11.1 cycle. One feature, quite a bit of refactoring in target/arm, and also I have included the patches to MAINTAINERS to remove people who aren't active in the project any more. thanks -- PMM The following changes since commit bb230769b4d01de714bed686161ad39a8f4f3fd1: Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2026-04-22 14:30:04 -0400) are available in the Git repository at: https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20260423 for you to fetch changes up to 250c9de780448fd447056ea42c7ebfdb0b32ab92: MAINTAINERS: Remove Xie Changlong (2026-04-23 10:39:06 +0100) ---------------------------------------------------------------- target-arm queue: * virt: Allow user to specify cache topology * target/arm: Move OMAP CP15 register definitions to cpregs-omap.c * target/arm: cleanups for single-binary work * MAINTAINERS: remove people who are no longer active in the project ---------------------------------------------------------------- Alessandro Ratti (1): target/arm: Move OMAP CP15 register definitions to cpregs-omap.c Alireza Sanaee (8): target/arm/tcg: increase cache level for cpu=max hw/core/machine: topology functions capabilities added hw/arm/virt: add cache hierarchy to device tree bios-tables-test: prepare to change ARM ACPI virt PPTT acpi: Add parameters to pass cache descriptions to ACPI build_pptt() hw/acpi: add cache hierarchy to pptt table tests/qtest/bios-table-test: testing new ARM ACPI PPTT topology Update the ACPI tables based on new aml-build.c Peter Maydell (27): MAINTAINERS: Remove Ahmed Karaman MAINTAINERS: Remove Anup Patel MAINTAINERS: Remove Beniamino Galvani MAINTAINERS: Remove Jeff Cody MAINTAINERS: Remove Coiby Xu MAINTAINERS: Remove Damien Hedde MAINTAINERS: Remove Ed Maste MAINTAINERS: Remove Dongjiu Geng MAINTAINERS: Remove Huai-Cheng Kuo MAINTAINERS: Remove Bastian Koppelmann MAINTAINERS: Remove Mahmoud Mandour MAINTAINERS: Remove Magnus Damm MAINTAINERS: Remove Marcel Apfelbaum MAINTAINERS: Remove Aarushi Mehta MAINTAINERS: Remove Paul Burton MAINTAINERS: Remove Jia Liu MAINTAINERS: Remove Qiuhao Li MAINTAINERS: Remove Luigi Rizzo MAINTAINERS: Remove Ronnie Sahlberg MAINTAINERS: Remove Ryo ONODERA MAINTAINERS: Remove Shannon Zhao MAINTAINERS: Remove Su Hang MAINTAINERS: Remove Vijai Kumar K MAINTAINERS: Remove Yanan Wang MAINTAINERS: Remove Wen Congyang MAINTAINERS: Remove Xiao Guangrong MAINTAINERS: Remove Xie Changlong Philippe Mathieu-Daudé (2): target/arm: Replace target_ulong -> vaddr in guarded_page_br() target/arm: Remove target_ulong use in hvf_handle_psci_call() Pierrick Bouvier (21): include/tcg/tcg-op: extract memory operations to tcg-op-mem.h target/arm/translate.h: remove tcg-op.h include target/arm/tcg/translate.h: remove tcg-op-gvec.h include target/arm/tcg/translate.h: remove TARGET_AARCH64 target/arm/tcg/translate-vfp.c: make compilation unit common target/arm/tcg/translate-neon.c: make compilation unit common target/arm/tcg/translate-mve.c: make compilation unit common target/arm/tcg/translate-m-nocp.c: make compilation unit common target/arm/tcg/op_helper.c: make compilation unit common target/arm/tcg/gengvec.c: make compilation unit common target/arm/tcg/translate.c: remove MO_TE usage target/arm/tcg/translate.c: replace target_ulong with uint32_t target/arm/tcg/translate.c: extract aarch64_translate_code() tcg/translator: add parameter to translator_loop for current addr type target/arm/tcg/translate.c: replace TCGv with TCGv_va target/arm/tcg/translate-a64.c: use translator_ldl_end instead of arm_ldl_code target/arm/tcg/arm_ldst.h: merge in translate.c target/arm/tcg/translate.c: replace translator_ldl_swap with translator_ldl_end target/arm/cpu.c: simplify endianness handling in arm_disas_set_info target/arm/tcg/translate.c: remove target_ulong target/arm/tcg/translate.c: make compilation unit common MAINTAINERS | 52 +---- accel/tcg/translate-all.c | 1 - accel/tcg/translator.c | 4 +- hw/acpi/aml-build.c | 203 ++++++++++++++++- hw/arm/virt-acpi-build.c | 8 +- hw/arm/virt.c | 335 ++++++++++++++++++++++++++++- hw/core/machine-smp.c | 52 +++++ hw/loongarch/virt-acpi-build.c | 4 +- include/exec/translator.h | 4 +- include/hw/acpi/aml-build.h | 4 +- include/hw/acpi/cpu.h | 10 + include/hw/arm/virt.h | 17 +- include/hw/core/boards.h | 5 + include/hw/core/cpu.h | 12 ++ include/tcg/tcg-op-mem.h | 126 +++++++++++ include/tcg/tcg-op.h | 100 +-------- target/alpha/translate.c | 3 +- target/arm/cpregs-omap-stub.c | 10 + target/arm/cpregs-omap.c | 88 ++++++++ target/arm/cpu.c | 6 +- target/arm/helper.c | 79 +------ target/arm/hvf/hvf.c | 2 +- target/arm/internals.h | 4 + target/arm/meson.build | 2 + target/arm/tcg/arm_ldst.h | 47 ---- target/arm/tcg/cpu64.c | 10 + target/arm/tcg/helper-a64-defs.h | 2 +- target/arm/tcg/helper-a64.c | 4 +- target/arm/tcg/meson.build | 57 +++-- target/arm/tcg/op_helper.c | 1 - target/arm/tcg/stubs32.c | 24 +++ target/arm/tcg/translate-a64.c | 17 +- target/arm/tcg/translate-sme.c | 1 + target/arm/tcg/translate-sve.c | 1 + target/arm/tcg/translate.c | 73 ++++--- target/arm/tcg/translate.h | 14 +- target/avr/translate.c | 3 +- target/hexagon/translate.c | 3 +- target/hppa/translate.c | 3 +- target/i386/tcg/translate.c | 3 +- target/loongarch/tcg/translate.c | 3 +- target/m68k/translate.c | 3 +- target/microblaze/translate.c | 3 +- target/mips/tcg/translate.c | 3 +- target/or1k/translate.c | 3 +- target/ppc/translate.c | 3 +- target/riscv/translate.c | 3 +- target/rx/translate.c | 3 +- target/s390x/tcg/translate.c | 3 +- target/sh4/translate.c | 3 +- target/sparc/translate.c | 3 +- target/tricore/translate.c | 3 +- target/xtensa/translate.c | 3 +- tests/data/acpi/aarch64/virt/PPTT.topology | Bin 356 -> 516 bytes tests/qtest/bios-tables-test.c | 4 + 55 files changed, 1071 insertions(+), 366 deletions(-) create mode 100644 include/tcg/tcg-op-mem.h create mode 100644 target/arm/cpregs-omap-stub.c create mode 100644 target/arm/cpregs-omap.c create mode 100644 target/arm/tcg/stubs32.c From: Alireza Sanaee <alireza.sanaee@huawei.com> This patch addresses cache description in the `aarch64_max_tcg_initfn` function for cpu=max. It introduces three levels of caches and modifies the cache description registers accordingly. Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Message-id: 20260311160609.358-2-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/cpu64.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) uint64_t t; uint32_t u; + SET_IDREG(isar, CLIDR, 0x8200123); + /* 64KB L1 dcache */ + cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); + /* 1MB L2 unified cache */ + cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); + /* 2MB L3 unified cache */ + cpu->ccsidr[4] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 2 * MiB, 7); + /* * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default * to because we started with aarch64_a57_initfn(). A 'max' CPU might -- 2.43.0 From: Alireza Sanaee <alireza.sanaee@huawei.com> Add two functions one of which finds the lowest cache level defined in the cache description input, and the other checks if a given cache topology is defined at a particular cache level Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20260311160609.358-3-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/core/machine-smp.c | 52 ++++++++++++++++++++++++++++++++++++++++ include/hw/core/boards.h | 5 ++++ 2 files changed, 57 insertions(+) diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index XXXXXXX..XXXXXXX 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -XXX,XX +XXX,XX @@ bool machine_check_smp_cache(const MachineState *ms, Error **errp) return true; } + +/* + * This function assumes L3 and L2 have unified cache and L1 is split L1d and + * L1i. + */ +bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms, + int *lowest_cache_level, + CpuTopologyLevel topo_level) +{ + enum CacheLevelAndType cache_level; + enum CpuTopologyLevel t; + + for (cache_level = CACHE_LEVEL_AND_TYPE_L1D; + cache_level < CACHE_LEVEL_AND_TYPE__MAX; cache_level++) { + t = machine_get_cache_topo_level(ms, cache_level); + if (t == topo_level) { + /* Assume L1 is split into L1d and L1i caches. */ + if (cache_level == CACHE_LEVEL_AND_TYPE_L1D || + cache_level == CACHE_LEVEL_AND_TYPE_L1I) { + *lowest_cache_level = 1; /* L1 */ + } else { + /* Assume the other caches are unified. */ + *lowest_cache_level = cache_level; + } + + return true; + } + } + + return false; +} + +/* + * Check if there are caches defined at a particular level. It supports only + * L1, L2 and L3 caches, but this can be extended to more levels as needed. + * + * Return True on success, False otherwise. + */ +bool machine_defines_cache_at_topo_level(const MachineState *ms, + CpuTopologyLevel topology) +{ + enum CacheLevelAndType cache_level; + + for (cache_level = CACHE_LEVEL_AND_TYPE_L1D; + cache_level < CACHE_LEVEL_AND_TYPE__MAX; cache_level++) { + if (machine_get_cache_topo_level(ms, cache_level) == topology) { + return true; + } + } + + return false; +} diff --git a/include/hw/core/boards.h b/include/hw/core/boards.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/core/boards.h +++ b/include/hw/core/boards.h @@ -XXX,XX +XXX,XX @@ void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache, CpuTopologyLevel level); bool machine_check_smp_cache(const MachineState *ms, Error **errp); void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size); +bool machine_defines_cache_at_topo_level(const MachineState *ms, + CpuTopologyLevel topology); +bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms, + int *lowest_cache_level, + CpuTopologyLevel topo_level); /** * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices -- 2.43.0 From: Alireza Sanaee <alireza.sanaee@huawei.com> Specify which level (core/cluster/socket) caches found at in the CPU topology. Updating cache topology to device tree (spec v0.4). Example: For example, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads created, in aggregate 2*2*4*2 logical cores. In the smp-cache object, cores will have L1d and L1i. However, extending this is not difficult. The clusters will share a unified L2 level cache, and finally sockets will share L3. In this patch, threads will share L1 caches by default, but this can be adjusted if case required. Only three levels of caches are supported. The patch does not allow partial declaration of caches. In other words, the topology level of every cache must be specified if that of any level is. ./qemu-system-aarch64 \ -machine virt,\ smp-cache.0.cache=l1i,smp-cache.0.topology=core,\ smp-cache.1.cache=l1d,smp-cache.1.topology=core,\ smp-cache.2.cache=l2,smp-cache.2.topology=cluster,\ smp-cache.3.cache=l3,smp-cache.3.topology=socket\ -cpu max \ -m 2048 \ -smp sockets=2,clusters=2,cores=4,threads=1 \ -kernel ./Image.gz \ -append "console=ttyAMA0 root=/dev/ram rdinit=/init acpi=force" \ -initrd rootfs.cpio.gz \ -bios ./edk2-aarch64-code.fd \ -nographic For instance, following device tree will be generated for a scenario where we have 2 sockets, 2 clusters, 2 cores and 2 threads, in total 16 PEs. L1i and L1d are private to each thread, and L2 and L3 are shared at socket level as an example. Limitation: SMT cores cannot share L1 cache for now. This problem does not exist in PPTT tables. Co-developed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20260311160609.358-4-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt.c | 335 +++++++++++++++++++++++++++++++++++++++++- include/hw/arm/virt.h | 17 ++- include/hw/core/cpu.h | 12 ++ 3 files changed, 362 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -XXX,XX +XXX,XX @@ #include "hw/virtio/virtio-md-pci.h" #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" +#include "hw/core/cpu.h" #include "hw/cxl/cxl.h" #include "hw/cxl/cxl_host.h" #include "qemu/guest-random.h" @@ -XXX,XX +XXX,XX @@ static bool ns_el2_virt_timer_present(void) arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); } +void set_cpu_cache(CPUCoreCaches *cpu_cache, enum CacheType cache_type, + int cache_level, bool is_i_cache0) +{ + int bank_index = ((cache_level - 1) * 2) | is_i_cache0; + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); + bool ccidx = cpu_isar_feature(any_ccidx, armcpu); + + if (ccidx) { + *cpu_cache = (CPUCoreCaches){ + .linesize = 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, + CCIDX_LINESIZE) + 4), + .associativity = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, + CCIDX_ASSOCIATIVITY) + 1, + .sets = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, + CCIDX_NUMSETS) + 1, + }; + } else { + *cpu_cache = (CPUCoreCaches){ + .linesize = 1 << (FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, + LINESIZE) + 4), + .associativity = FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, + ASSOCIATIVITY) + 1, + .sets = + FIELD_EX64(armcpu->ccsidr[bank_index], CCSIDR_EL1, NUMSETS) + 1, + }; + } + cpu_cache->type = cache_type; + cpu_cache->level = cache_level; + cpu_cache->size = cpu_cache->associativity * + cpu_cache->sets * + cpu_cache->linesize; + + return; +} + +unsigned int virt_get_caches(const VirtMachineState *vms, CPUCoreCaches *caches) +{ + int num_cache = 0; + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0)); /* assume homogeneous CPUs */ + ARMISARegisters *isar = &armcpu->isar; + uint32_t clidr = GET_IDREG(isar, CLIDR); + + for (int cache_level = 1; cache_level <= CLIDR_CTYPE_MAX_CACHE_LEVEL; + cache_level++) { + uint8_t ctype = + (clidr >> (3 * (cache_level - 1))) & CLIDR_CTYPE_MAX_CACHE_LEVEL; + + if (ctype == CLIDR_CTYPE_NO_CACHE) { + /* + * If a "No cache" cache type is found it means no manageable caches + * exist at further-out levels of hierarchy, so ignore them. + */ + break; + } else if (ctype == CLIDR_CTYPE_SEPARATE_I_D_CACHES) { + /* + * Create separate D and I caches. D-cache is stored first. + */ + enum CacheType cache_type; + for (cache_type = DATA_CACHE; cache_type <= INSTRUCTION_CACHE; + cache_type++) { + set_cpu_cache(&caches[num_cache++], cache_type, cache_level, + cache_type == INSTRUCTION_CACHE ? true : false); + } + } else if (ctype == CLIDR_CTYPE_UNIFIED_CACHE) { + set_cpu_cache(&caches[num_cache++], UNIFIED_CACHE, cache_level, + false); + } else if (ctype == CLIDR_CTYPE_D_CACHE) { + set_cpu_cache(&caches[num_cache++], DATA_CACHE, cache_level, false); + } else if (ctype == CLIDR_CTYPE_I_CACHE) { + set_cpu_cache(&caches[num_cache++], INSTRUCTION_CACHE, cache_level, + true); + } else { + error_setg(&error_abort, "Unrecognized cache type"); + return 0; + } + } + + return num_cache; +} + static void create_fdt(VirtMachineState *vms) { MachineState *ms = MACHINE(vms); @@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) } } +static void add_cache_node(void *fdt, char *nodepath, CPUCoreCaches cache, + uint32_t *next_level) +{ + /* Assume L2/3 are unified caches. */ + + uint32_t phandle; + + qemu_fdt_add_path(fdt, nodepath); + phandle = qemu_fdt_alloc_phandle(fdt); + qemu_fdt_setprop_cell(fdt, nodepath, "phandle", phandle); + qemu_fdt_setprop_cell(fdt, nodepath, "cache-level", cache.level); + qemu_fdt_setprop_cell(fdt, nodepath, "cache-size", cache.size); + qemu_fdt_setprop_cell(fdt, nodepath, "cache-block-size", cache.linesize); + qemu_fdt_setprop_cell(fdt, nodepath, "cache-sets", cache.sets); + qemu_fdt_setprop(fdt, nodepath, "cache-unified", NULL, 0); + qemu_fdt_setprop_string(fdt, nodepath, "compatible", "cache"); + if (cache.level != 3) { + /* top level cache doesn't have next-level-cache property */ + qemu_fdt_setprop_cell(fdt, nodepath, "next-level-cache", *next_level); + } + + *next_level = phandle; +} + +static bool add_cpu_cache_hierarchy(void *fdt, CPUCoreCaches* cache, + uint32_t cache_cnt, + uint32_t top_level, + uint32_t bottom_level, + uint32_t cpu_id, + uint32_t *next_level) { + bool found_cache = false; + + for (int level = top_level; level >= bottom_level; level--) { + for (int i = 0; i < cache_cnt; i++) { + char *nodepath; + + if (i != level) { + continue; + } + + nodepath = g_strdup_printf("/cpus/cpu@%d/l%d-cache", + cpu_id, level); + add_cache_node(fdt, nodepath, cache[i], next_level); + found_cache = true; + g_free(nodepath); + + } + } + + return found_cache; +} + +static void set_cache_properties(void *fdt, const char *nodename, + const char *prefix, CPUCoreCaches cache) +{ + char prop_name[64]; + + snprintf(prop_name, sizeof(prop_name), "%s-block-size", prefix); + qemu_fdt_setprop_cell(fdt, nodename, prop_name, cache.linesize); + + snprintf(prop_name, sizeof(prop_name), "%s-size", prefix); + qemu_fdt_setprop_cell(fdt, nodename, prop_name, cache.size); + + snprintf(prop_name, sizeof(prop_name), "%s-sets", prefix); + qemu_fdt_setprop_cell(fdt, nodename, prop_name, cache.sets); +} + +static bool partial_cache_description(const MachineState *ms, int num_caches) +{ + assert(num_caches - 1 < CACHE_LEVEL_AND_TYPE__MAX); + enum CpuTopologyLevel topo_level; + enum CacheLevelAndType cache_level; + + for (cache_level = 0; cache_level < num_caches; cache_level++) { + topo_level = machine_get_cache_topo_level(ms, cache_level); + if (topo_level == CPU_TOPOLOGY_LEVEL_DEFAULT) { + /* No topology level described for this cache level. */ + return true; + } + } + + return false; +} + static void fdt_add_cpu_nodes(const VirtMachineState *vms) { int cpu; int addr_cells = 1; const MachineState *ms = MACHINE(vms); + const MachineClass *mc = MACHINE_GET_CLASS(ms); const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); int smp_cpus = ms->smp.cpus; + int socket_id, cluster_id, core_id; + uint32_t next_level = 0; + uint32_t socket_offset = 0; + uint32_t cluster_offset = 0; + uint32_t core_offset = 0; + int last_socket = -1; + int last_cluster = -1; + int last_core = -1; + int top_node = 3; + int top_cluster = 3; + int top_core = 3; + int bottom_node = 3; + int bottom_cluster = 3; + int bottom_core = 3; + unsigned int num_cache; + CPUCoreCaches caches[CPU_MAX_CACHES]; + bool cache_created = false; + bool cache_at_topo_level; + + num_cache = virt_get_caches(vms, caches); + + if (mc->smp_props.has_caches && + partial_cache_description(ms, num_cache)) { + error_setg(&error_fatal, "Missing cache description"); + return; + } /* * See Linux Documentation/devicetree/bindings/arm/cpus.yaml @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { + socket_id = cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); + cluster_id = cpu / (ms->smp.cores * ms->smp.threads) % ms->smp.clusters; + core_id = cpu / ms->smp.threads % ms->smp.cores; + char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu); ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); CPUState *cs = CPU(armcpu); + const char *prefix = NULL; qemu_fdt_add_subnode(ms->fdt, nodename); qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); @@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) qemu_fdt_alloc_phandle(ms->fdt)); } + if (!vmc->no_cpu_topology && num_cache) { + for (uint8_t i = 0; i < num_cache; i++) { + /* Only level 1 in the CPU entry. */ + if (caches[i].level > 1) { + continue; + } + + if (caches[i].type == INSTRUCTION_CACHE) { + prefix = "i-cache"; + } else if (caches[i].type == DATA_CACHE) { + prefix = "d-cache"; + } else if (caches[i].type == UNIFIED_CACHE) { + error_setg(&error_fatal, + "Unified type is not implemented at level %d", + caches[i].level); + return; + } else { + error_setg(&error_fatal, "Undefined cache type"); + return; + } + + set_cache_properties(ms->fdt, nodename, prefix, caches[i]); + } + } + + if (socket_id != last_socket) { + bottom_node = top_node; + /* This assumes socket as the highest topological level. */ + socket_offset = 0; + cluster_offset = 0; + cache_at_topo_level = + machine_find_lowest_level_cache_at_topo_level(ms, + &bottom_node, + CPU_TOPOLOGY_LEVEL_SOCKET); + if (cache_at_topo_level) { + if (bottom_node == 1 && !virt_is_acpi_enabled(vms)) + error_setg( + &error_fatal, + "Cannot share L1 at socket_id %d." + "DT limitation on sharing at cache level = 1", + socket_id); + + cache_created = add_cpu_cache_hierarchy(ms->fdt, caches, + num_cache, + top_node, + bottom_node, cpu, + &socket_offset); + + if (!cache_created) { + error_setg(&error_fatal, + "Socket: No caches at levels %d-%d", + top_node, bottom_node); + return; + } + + top_cluster = bottom_node - 1; + } + + last_socket = socket_id; + } + + if (cluster_id != last_cluster) { + bottom_cluster = top_cluster; + cluster_offset = socket_offset; + core_offset = 0; + cache_at_topo_level = + machine_find_lowest_level_cache_at_topo_level(ms, + &bottom_cluster, + CPU_TOPOLOGY_LEVEL_CLUSTER); + if (cache_at_topo_level) { + cache_created = add_cpu_cache_hierarchy(ms->fdt, caches, + num_cache, + top_cluster, + bottom_cluster, cpu, + &cluster_offset); + if (bottom_cluster == 1 && !virt_is_acpi_enabled(vms)) { + error_setg(&error_fatal, + "Cannot share L1 at socket_id %d, cluster_id %d. " + "DT limitation on sharing at cache level = 1.", + socket_id, cluster_id); + } + + if (!cache_created) { + error_setg(&error_fatal, + "Cluster: No caches at levels %d-%d.", + top_cluster, bottom_cluster); + return; + } + + top_core = bottom_cluster - 1; + } else if (top_cluster == bottom_node - 1) { + top_core = bottom_node - 1; + } + + last_cluster = cluster_id; + } + + if (core_id != last_core) { + bottom_core = top_core; + core_offset = cluster_offset; + cache_at_topo_level = + machine_find_lowest_level_cache_at_topo_level(ms, + &bottom_core, + CPU_TOPOLOGY_LEVEL_CORE); + if (cache_at_topo_level) { + if (bottom_core == 1 && top_core > 1) { + bottom_core++; + cache_created = add_cpu_cache_hierarchy(ms->fdt, + caches, + num_cache, + top_core, + bottom_core, cpu, + &core_offset); + + if (!cache_created) { + error_setg(&error_fatal, + "Core: No caches at levels %d-%d", + top_core, bottom_core); + return; + } + } + } + + last_core = core_id; + } + + next_level = core_offset; + qemu_fdt_setprop_cell(ms->fdt, nodename, "next-level-cache", + next_level); + g_free(nodename); } @@ -XXX,XX +XXX,XX @@ static void virt_set_oem_table_id(Object *obj, const char *value, } -bool virt_is_acpi_enabled(VirtMachineState *vms) +bool virt_is_acpi_enabled(const VirtMachineState *vms) { if (vms->acpi == ON_OFF_AUTO_OFF) { return false; @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, const void *data) hc->unplug = virt_machine_device_unplug_cb; mc->nvdimm_supported = true; mc->smp_props.clusters_supported = true; + + /* Supported caches */ + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; + mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; mc->auto_enable_numa_with_memhp = true; mc->auto_enable_numa_with_memdev = true; /* platform instead of architectural choice */ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -XXX,XX +XXX,XX @@ #include "system/kvm.h" #include "hw/intc/arm_gicv3_common.h" #include "qom/object.h" +#include "hw/core/cpu.h" #define NUM_GICV2M_SPIS 64 #define NUM_VIRTIO_TRANSPORTS 32 @@ -XXX,XX +XXX,XX @@ /* GPIO pins */ #define GPIO_PIN_POWER_BUTTON 3 +#define CPU_MAX_CACHES 16 + enum { VIRT_FLASH, VIRT_MEM, @@ -XXX,XX +XXX,XX @@ struct VirtMachineState { OBJECT_DECLARE_TYPE(VirtMachineState, VirtMachineClass, VIRT_MACHINE) void virt_acpi_setup(VirtMachineState *vms); -bool virt_is_acpi_enabled(VirtMachineState *vms); +bool virt_is_acpi_enabled(const VirtMachineState *vms); + +#define CLIDR_CTYPE_NO_CACHE 0x00 +#define CLIDR_CTYPE_I_CACHE 0x01 +#define CLIDR_CTYPE_D_CACHE 0x02 +#define CLIDR_CTYPE_SEPARATE_I_D_CACHES 0x03 +#define CLIDR_CTYPE_UNIFIED_CACHE 0x04 +#define CLIDR_CTYPE_MAX_CACHE_LEVEL 7 + +unsigned int virt_get_caches(const VirtMachineState *vms, + CPUCoreCaches *caches); +void set_cpu_cache(CPUCoreCaches *cpu_cache, enum CacheType cache_type, + int cache_level, bool is_i_cache); /* Return number of redistributors that fit in the specified region */ static uint32_t virt_redist_capacity(VirtMachineState *vms, int region) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -XXX,XX +XXX,XX @@ enum CacheType { UNIFIED_CACHE }; +struct CPUCoreCaches { + enum CacheType type; + uint32_t sets; + uint32_t size; + uint32_t level; + uint16_t linesize; + uint8_t attributes; /* write policy: 0x0 write back, 0x1 write through */ + uint8_t associativity; +}; + +typedef struct CPUCoreCaches CPUCoreCaches; + #endif -- 2.43.0 From: Alireza Sanaee <alireza.sanaee@huawei.com> Prepare to update `build_pptt` function to add cache description functionalities, thus add binaries in this patch. Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260311160609.358-5-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/PPTT", +"tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt", +"tests/data/acpi/aarch64/virt/PPTT.topology", -- 2.43.0 From: Alireza Sanaee <alireza.sanaee@huawei.com> Add optional parameters to pass cache descriptions to build_pptt(). Update ARM and Loongarch callers to pass none for now. Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Message-id: 20260311160609.358-6-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/acpi/aml-build.c | 3 ++- hw/arm/virt-acpi-build.c | 2 +- hw/loongarch/virt-acpi-build.c | 4 ++-- include/hw/acpi/aml-build.h | 4 +++- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -XXX,XX +XXX,XX @@ void build_spcr(GArray *table_data, BIOSLinker *linker, * 5.2.29 Processor Properties Topology Table (PPTT) */ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id) + const char *oem_id, const char *oem_table_id, + int num_caches, CPUCoreCaches *caches) { MachineClass *mc = MACHINE_GET_CLASS(ms); CPUArchIdList *cpus = ms->possible_cpus; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) if (!vmc->no_cpu_topology) { acpi_add_table(table_offsets, tables_blob); build_pptt(tables_blob, tables->linker, ms, - vms->oem_id, vms->oem_table_id); + vms->oem_id, vms->oem_table_id, 0, NULL); } acpi_add_table(table_offsets, tables_blob); diff --git a/hw/loongarch/virt-acpi-build.c b/hw/loongarch/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/loongarch/virt-acpi-build.c +++ b/hw/loongarch/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine) build_madt(tables_blob, tables->linker, lvms); acpi_add_table(table_offsets, tables_blob); - build_pptt(tables_blob, tables->linker, machine, - lvms->oem_id, lvms->oem_table_id); + build_pptt(tables_blob, tables->linker, machine, lvms->oem_id, + lvms->oem_table_id, 0, NULL); acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, machine); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -XXX,XX +XXX,XX @@ #include "hw/acpi/acpi-defs.h" #include "hw/acpi/bios-linker-loader.h" +#include "hw/core/cpu.h" #define ACPI_BUILD_APPNAME6 "BOCHS " #define ACPI_BUILD_APPNAME8 "BXPC " @@ -XXX,XX +XXX,XX @@ void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, const char *oem_id, const char *oem_table_id); void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id); + const char *oem_id, const char *oem_table_id, + int num_caches, CPUCoreCaches *caches); void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); -- 2.43.0 From: Alireza Sanaee <alireza.sanaee@huawei.com> Add cache topology to PPTT table. Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-id: 20260311160609.358-7-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/acpi/aml-build.c | 200 +++++++++++++++++++++++++++++++++++++-- hw/arm/virt-acpi-build.c | 8 +- include/hw/acpi/cpu.h | 10 ++ 3 files changed, 209 insertions(+), 9 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -XXX,XX +XXX,XX @@ #include "hw/pci/pci_bridge.h" #include "hw/acpi/acpi_aml_interface.h" #include "qemu/cutils.h" +#include "hw/core/cpu.h" static GArray *build_alloc_array(void) { @@ -XXX,XX +XXX,XX @@ void build_spcr(GArray *table_data, BIOSLinker *linker, } acpi_table_end(linker, &table); } + +/* + * ACPI spec, Revision 6.3 + * 5.2.29.2 Cache Type Structure (Type 1) + */ +static void build_cache_nodes(GArray *tbl, CPUCoreCaches *cache, + uint32_t next_offset) +{ + const uint8_t node_length = 24; + int start_len = tbl->len; + int val; + + build_append_byte(tbl, 1); /* Type 1 - cache */ + build_append_byte(tbl, node_length); /* Length */ + build_append_int_noprefix(tbl, 0, 2); /* Reserved */ + build_append_int_noprefix(tbl, 0x7f, 4); /* Flags */ + build_append_int_noprefix(tbl, next_offset, 4); /* Next Level of Cache */ + build_append_int_noprefix(tbl, cache->size, 4); /* Size */ + build_append_int_noprefix(tbl, cache->sets, 4); /* Number of sets */ + build_append_byte(tbl, cache->associativity); /* Associativity */ + val = 0x3; + switch (cache->type) { + case INSTRUCTION_CACHE: + val |= (1 << 2); /* Instruction Cache */ + break; + case DATA_CACHE: + val |= (0 << 2); /* Data Cache */ + break; + case UNIFIED_CACHE: + val |= (3 << 2); /* Unified */ + break; + } + build_append_byte(tbl, val); /* Attributes */ + build_append_int_noprefix(tbl, cache->linesize, 2); /* Line size */ + g_assert(tbl->len == start_len + node_length); +} + +/* + * Build PPTT Cache Type structures (Type 1) from cache level `level_high` + * down to `level_low` (both inclusive), appending them to the PPTT table. + * + * On output, `data_offset` and `instr_offset` hold the PPTT offsets of the + * lowest-level data and instruction cache nodes respectively. These offsets + * are referenced as private resources in the Processor Hierarchy Node (Type 0) + * that owns the caches. + */ +static bool build_caches(GArray *table_data, uint32_t pptt_start, + int num_caches, CPUCoreCaches *caches, + uint8_t level_high, /* Inclusive */ + uint8_t level_low, /* Inclusive */ + uint32_t *data_offset, + uint32_t *instr_offset) +{ + uint32_t next_level_offset_data = 0, next_level_offset_instruction = 0; + uint32_t this_offset, next_offset = 0; + int c, level; + bool found_cache = false; + + /* Walk caches from top to bottom */ + for (level = level_high; level >= level_low; level--) { + for (c = 0; c < num_caches; c++) { + if (caches[c].level != level) { + continue; + } + + /* Assume only unified above l1 for now */ + this_offset = table_data->len - pptt_start; + switch (caches[c].type) { + case INSTRUCTION_CACHE: + next_offset = next_level_offset_instruction; + break; + case DATA_CACHE: + next_offset = next_level_offset_data; + break; + case UNIFIED_CACHE: + /* Either is fine here */ + next_offset = next_level_offset_instruction; + break; + } + build_cache_nodes(table_data, &caches[c], next_offset); + switch (caches[c].type) { + case INSTRUCTION_CACHE: + next_level_offset_instruction = this_offset; + break; + case DATA_CACHE: + next_level_offset_data = this_offset; + break; + case UNIFIED_CACHE: + next_level_offset_instruction = this_offset; + next_level_offset_data = this_offset; + break; + } + *data_offset = next_level_offset_data; + *instr_offset = next_level_offset_instruction; + + found_cache = true; + } + } + + return found_cache; +} + /* * ACPI spec, Revision 6.3 * 5.2.29 Processor Properties Topology Table (PPTT) @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, { MachineClass *mc = MACHINE_GET_CLASS(ms); CPUArchIdList *cpus = ms->possible_cpus; - int64_t socket_id = -1, cluster_id = -1, core_id = -1; - uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0; + uint32_t core_data_offset = 0; + uint32_t core_instr_offset = 0; + uint32_t cluster_instr_offset = 0; + uint32_t cluster_data_offset = 0; + uint32_t node_data_offset = 0; + uint32_t node_instr_offset = 0; + int top_node = 3; + int top_cluster = 3; + int top_core = 3; + int bottom_node = 3; + int bottom_cluster = 3; + int bottom_core = 3; + int64_t socket_id = -1; + int64_t cluster_id = -1; + int64_t core_id = -1; + uint32_t socket_offset = 0; + uint32_t cluster_offset = 0; + uint32_t core_offset = 0; uint32_t pptt_start = table_data->len; uint32_t root_offset; int n; + uint32_t priv_rsrc[2]; + uint32_t num_priv = 0; + bool cache_at_topo_level; + AcpiTable table = { .sig = "PPTT", .rev = 2, .oem_id = oem_id, .oem_table_id = oem_table_id }; @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, socket_id = cpus->cpus[n].props.socket_id; cluster_id = -1; core_id = -1; + bottom_node = top_node; + num_priv = 0; + cache_at_topo_level = + machine_find_lowest_level_cache_at_topo_level( + ms, &bottom_node, CPU_TOPOLOGY_LEVEL_SOCKET); + if (cache_at_topo_level) { + build_caches(table_data, pptt_start, num_caches, caches, + top_node, bottom_node, &node_data_offset, + &node_instr_offset); + priv_rsrc[0] = node_instr_offset; + priv_rsrc[1] = node_data_offset; + if (node_instr_offset || node_data_offset) { + num_priv = node_instr_offset == node_data_offset ? 1 : 2; + } + + top_cluster = bottom_node - 1; + } + socket_offset = table_data->len - pptt_start; build_processor_hierarchy_node(table_data, (1 << 0) | /* Physical package */ (1 << 4), /* Identical Implementation */ - root_offset, socket_id, NULL, 0); + root_offset, socket_id, priv_rsrc, num_priv); } if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters) { @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, assert(cpus->cpus[n].props.cluster_id > cluster_id); cluster_id = cpus->cpus[n].props.cluster_id; core_id = -1; + bottom_cluster = top_cluster; + num_priv = 0; + cache_at_topo_level = + machine_find_lowest_level_cache_at_topo_level( + ms, &bottom_cluster, CPU_TOPOLOGY_LEVEL_CLUSTER); + + if (cache_at_topo_level) { + build_caches(table_data, pptt_start, num_caches, caches, + top_cluster, bottom_cluster, + &cluster_data_offset, &cluster_instr_offset); + priv_rsrc[0] = cluster_instr_offset; + priv_rsrc[1] = cluster_data_offset; + if (cluster_instr_offset || cluster_data_offset) { + num_priv = + cluster_instr_offset == cluster_data_offset ? 1 : 2; + } + top_core = bottom_cluster - 1; + } else if (top_cluster == bottom_node - 1) { + /* socket cache but no cluster cache */ + top_core = bottom_node - 1; + } + cluster_offset = table_data->len - pptt_start; build_processor_hierarchy_node(table_data, (0 << 0) | /* Not a physical package */ (1 << 4), /* Identical Implementation */ - socket_offset, cluster_id, NULL, 0); + socket_offset, cluster_id, priv_rsrc, num_priv); } } else { + if (machine_defines_cache_at_topo_level( + ms, CPU_TOPOLOGY_LEVEL_CLUSTER)) { + error_setg(&error_fatal, "Not clusters found for the cache"); + return; + } + cluster_offset = socket_offset; + top_core = bottom_node - 1; /* there is no cluster */ + } + + if (cpus->cpus[n].props.core_id != core_id) { + bottom_core = top_core; + num_priv = 0; + cache_at_topo_level = + machine_find_lowest_level_cache_at_topo_level( + ms, &bottom_core, CPU_TOPOLOGY_LEVEL_CORE); + if (cache_at_topo_level) { + build_caches(table_data, pptt_start, num_caches, caches, + top_core, bottom_core, &core_data_offset, + &core_instr_offset); + priv_rsrc[0] = core_instr_offset; + priv_rsrc[1] = core_data_offset; + num_priv = core_instr_offset == core_data_offset ? 1 : 2; + } } if (ms->smp.threads == 1) { build_processor_hierarchy_node(table_data, (1 << 1) | /* ACPI Processor ID valid */ - (1 << 3), /* Node is a Leaf */ - cluster_offset, n, NULL, 0); + (1 << 3), /* Node is a Leaf */ + cluster_offset, n, priv_rsrc, num_priv); } else { if (cpus->cpus[n].props.core_id != core_id) { assert(cpus->cpus[n].props.core_id > core_id); @@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, build_processor_hierarchy_node(table_data, (0 << 0) | /* Not a physical package */ (1 << 4), /* Identical Implementation */ - cluster_offset, core_id, NULL, 0); + cluster_offset, core_id, priv_rsrc, num_priv); } build_processor_hierarchy_node(table_data, diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) unsigned dsdt, xsdt; GArray *tables_blob = tables->table_data; MachineState *ms = MACHINE(vms); + CPUCoreCaches caches[CPU_MAX_CACHES]; + unsigned int num_caches; + + num_caches = virt_get_caches(vms, caches); table_offsets = g_array_new(false, true /* clear */, sizeof(uint32_t)); @@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) if (!vmc->no_cpu_topology) { acpi_add_table(table_offsets, tables_blob); - build_pptt(tables_blob, tables->linker, ms, - vms->oem_id, vms->oem_table_id, 0, NULL); + build_pptt(tables_blob, tables->linker, ms, vms->oem_id, + vms->oem_table_id, num_caches, caches); } acpi_add_table(table_offsets, tables_blob); diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -XXX,XX +XXX,XX @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list); +struct CPUPPTTCaches { + enum CacheType type; + uint32_t sets; + uint32_t size; + uint32_t level; + uint16_t linesize; + uint8_t attributes; /* write policy: 0x0 write back, 0x1 write through */ + uint8_t associativity; +}; + extern const VMStateDescription vmstate_cpu_hotplug; #define VMSTATE_CPU_HOTPLUG(cpuhp, state) \ VMSTATE_STRUCT(cpuhp, state, 1, \ -- 2.43.0 From: Alireza Sanaee <alireza.sanaee@huawei.com> Test new PPTT topolopy with cache representation. Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Message-id: 20260311160609.358-8-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/qtest/bios-tables-test.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -XXX,XX +XXX,XX @@ static void test_acpi_aarch64_virt_tcg_topology(void) }; test_acpi_one("-cpu cortex-a57 " + "-M virt,smp-cache.0.cache=l1i,smp-cache.0.topology=cluster," + "smp-cache.1.cache=l1d,smp-cache.1.topology=cluster," + "smp-cache.2.cache=l2,smp-cache.2.topology=cluster," + "smp-cache.3.cache=l3,smp-cache.3.topology=cluster " "-smp sockets=1,clusters=2,cores=2,threads=2", &data); free_test_data(&data); } -- 2.43.0 From: Alireza Sanaee <alireza.sanaee@huawei.com> The disassembled differences between actual and expected PPTT based on the following cache topology representation: - l1d and l1i shared at cluster level - l2 shared at cluster level - l3 shared at cluster level /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20230628 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * - * Disassembly of tests/data/acpi/aarch64/virt/PPTT.topology, Fri Aug 8 16:50:38 2025 + * Disassembly of /tmp/aml-JGBZA3, Fri Aug 8 16:50:38 2025 * * ACPI Data Table [PPTT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 0000 004h] Signature : "PPTT" [Processor Properties Topology Table] -[004h 0004 004h] Table Length : 00000164 +[004h 0004 004h] Table Length : 00000204 [008h 0008 001h] Revision : 02 -[009h 0009 001h] Checksum : 97 +[009h 0009 001h] Checksum : B8 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 001h] Subtable Type : 00 [Processor Hierarchy Node] [025h 0037 001h] Length : 14 [026h 0038 002h] Reserved : 0000 [028h 0040 004h] Flags (decoded below) : 00000011 Physical package : 1 ACPI Processor ID valid : 0 Processor is a thread : 0 Node is a leaf : 0 Identical Implementation : 1 @@ -XXX,XX +XXX,XX @@ [030h 0048 004h] ACPI Processor ID : 00000000 [034h 0052 004h] Private Resource Number : 00000000 [038h 0056 001h] Subtable Type : 00 [Processor Hierarchy Node] [039h 0057 001h] Length : 14 [03Ah 0058 002h] Reserved : 0000 [03Ch 0060 004h] Flags (decoded below) : 00000011 Physical package : 1 ACPI Processor ID valid : 0 Processor is a thread : 0 Node is a leaf : 0 Identical Implementation : 1 [040h 0064 004h] Parent : 00000024 [044h 0068 004h] ACPI Processor ID : 00000000 [048h 0072 004h] Private Resource Number : 00000000 -[04Ch 0076 001h] Subtable Type : 00 [Processor Hierarchy Node] -[04Dh 0077 001h] Length : 14 +[04Ch 0076 001h] Subtable Type : 01 [Cache Type] +[04Dh 0077 001h] Length : 18 [04Eh 0078 002h] Reserved : 0000 -[050h 0080 004h] Flags (decoded below) : 00000010 +[050h 0080 004h] Flags (decoded below) : 0000007F + Size valid : 1 + Number of Sets valid : 1 + Associativity valid : 1 + Allocation Type valid : 1 + Cache Type valid : 1 + Write Policy valid : 1 + Line Size valid : 1 + Cache ID valid : 0 +[054h 0084 004h] Next Level of Cache : 00000000 +[058h 0088 004h] Size : 00200000 +[05Ch 0092 004h] Number of Sets : 00000800 +[060h 0096 001h] Associativity : 10 +[061h 0097 001h] Attributes : 0F + Allocation Type : 3 + Cache Type : 3 + Write Policy : 0 +[062h 0098 002h] Line Size : 0040 + +[064h 0100 001h] Subtable Type : 01 [Cache Type] +[065h 0101 001h] Length : 18 +[066h 0102 002h] Reserved : 0000 +[068h 0104 004h] Flags (decoded below) : 0000007F + Size valid : 1 + Number of Sets valid : 1 + Associativity valid : 1 + Allocation Type valid : 1 + Cache Type valid : 1 + Write Policy valid : 1 + Line Size valid : 1 + Cache ID valid : 0 +[06Ch 0108 004h] Next Level of Cache : 0000004C +[070h 0112 004h] Size : 00008000 +[074h 0116 004h] Number of Sets : 00000080 +[078h 0120 001h] Associativity : 04 +[079h 0121 001h] Attributes : 03 + Allocation Type : 3 + Cache Type : 0 + Write Policy : 0 +[07Ah 0122 002h] Line Size : 0040 + +[07Ch 0124 001h] Subtable Type : 01 [Cache Type] +[07Dh 0125 001h] Length : 18 +[07Eh 0126 002h] Reserved : 0000 +[080h 0128 004h] Flags (decoded below) : 0000007F + Size valid : 1 + Number of Sets valid : 1 + Associativity valid : 1 + Allocation Type valid : 1 + Cache Type valid : 1 + Write Policy valid : 1 + Line Size valid : 1 + Cache ID valid : 0 +[084h 0132 004h] Next Level of Cache : 0000004C +[088h 0136 004h] Size : 0000C000 +[08Ch 0140 004h] Number of Sets : 00000100 +[090h 0144 001h] Associativity : 03 +[091h 0145 001h] Attributes : 07 + Allocation Type : 3 + Cache Type : 1 + Write Policy : 0 +[092h 0146 002h] Line Size : 0040 + +[094h 0148 001h] Subtable Type : 00 [Processor Hierarchy Node] +[095h 0149 001h] Length : 1C +[096h 0150 002h] Reserved : 0000 +[098h 0152 004h] Flags (decoded below) : 00000010 Physical package : 0 ACPI Processor ID valid : 0 Processor is a thread : 0 Node is a leaf : 0 Identical Implementation : 1 -[054h 0084 004h] Parent : 00000038 -[058h 0088 004h] ACPI Processor ID : 00000000 -[05Ch 0092 004h] Private Resource Number : 00000000 - -[060h 0096 001h] Subtable Type : 00 [Processor Hierarchy Node] -[061h 0097 001h] Length : 14 -[062h 0098 002h] Reserved : 0000 -[064h 0100 004h] Flags (decoded below) : 00000010 - Physical package : 0 - ACPI Processor ID valid : 0 - Processor is a thread : 0 - Node is a leaf : 0 - Identical Implementation : 1 -[068h 0104 004h] Parent : 0000004C -[06Ch 0108 004h] ACPI Processor ID : 00000000 -[070h 0112 004h] Private Resource Number : 00000000 - -[074h 0116 001h] Subtable Type : 00 [Processor Hierarchy Node] -[075h 0117 001h] Length : 14 -[076h 0118 002h] Reserved : 0000 -[078h 0120 004h] Flags (decoded below) : 0000000E - Physical package : 0 - ACPI Processor ID valid : 1 - Processor is a thread : 1 - Node is a leaf : 1 - Identical Implementation : 0 -[07Ch 0124 004h] Parent : 00000060 -[080h 0128 004h] ACPI Processor ID : 00000000 -[084h 0132 004h] Private Resource Number : 00000000 - -[088h 0136 001h] Subtable Type : 00 [Processor Hierarchy Node] -[089h 0137 001h] Length : 14 -[08Ah 0138 002h] Reserved : 0000 -[08Ch 0140 004h] Flags (decoded below) : 0000000E - Physical package : 0 - ACPI Processor ID valid : 1 - Processor is a thread : 1 - Node is a leaf : 1 - Identical Implementation : 0 -[090h 0144 004h] Parent : 00000060 -[094h 0148 004h] ACPI Processor ID : 00000001 -[098h 0152 004h] Private Resource Number : 00000000 - -[09Ch 0156 001h] Subtable Type : 00 [Processor Hierarchy Node] -[09Dh 0157 001h] Length : 14 -[09Eh 0158 002h] Reserved : 0000 -[0A0h 0160 004h] Flags (decoded below) : 00000010 - Physical package : 0 - ACPI Processor ID valid : 0 - Processor is a thread : 0 - Node is a leaf : 0 - Identical Implementation : 1 -[0A4h 0164 004h] Parent : 0000004C -[0A8h 0168 004h] ACPI Processor ID : 00000001 -[0ACh 0172 004h] Private Resource Number : 00000000 +[09Ch 0156 004h] Parent : 00000038 +[0A0h 0160 004h] ACPI Processor ID : 00000000 +[0A4h 0164 004h] Private Resource Number : 00000002 +[0A8h 0168 004h] Private Resource : 0000007C +[0ACh 0172 004h] Private Resource : 00000064 [0B0h 0176 001h] Subtable Type : 00 [Processor Hierarchy Node] [0B1h 0177 001h] Length : 14 [0B2h 0178 002h] Reserved : 0000 -[0B4h 0180 004h] Flags (decoded below) : 0000000E +[0B4h 0180 004h] Flags (decoded below) : 00000010 Physical package : 0 - ACPI Processor ID valid : 1 - Processor is a thread : 1 - Node is a leaf : 1 - Identical Implementation : 0 -[0B8h 0184 004h] Parent : 0000009C -[0BCh 0188 004h] ACPI Processor ID : 00000002 + ACPI Processor ID valid : 0 + Processor is a thread : 0 + Node is a leaf : 0 + Identical Implementation : 1 +[0B8h 0184 004h] Parent : 00000094 +[0BCh 0188 004h] ACPI Processor ID : 00000000 [0C0h 0192 004h] Private Resource Number : 00000000 [0C4h 0196 001h] Subtable Type : 00 [Processor Hierarchy Node] [0C5h 0197 001h] Length : 14 [0C6h 0198 002h] Reserved : 0000 [0C8h 0200 004h] Flags (decoded below) : 0000000E Physical package : 0 ACPI Processor ID valid : 1 Processor is a thread : 1 Node is a leaf : 1 Identical Implementation : 0 -[0CCh 0204 004h] Parent : 0000009C -[0D0h 0208 004h] ACPI Processor ID : 00000003 +[0CCh 0204 004h] Parent : 000000B0 +[0D0h 0208 004h] ACPI Processor ID : 00000000 [0D4h 0212 004h] Private Resource Number : 00000000 [0D8h 0216 001h] Subtable Type : 00 [Processor Hierarchy Node] [0D9h 0217 001h] Length : 14 [0DAh 0218 002h] Reserved : 0000 -[0DCh 0220 004h] Flags (decoded below) : 00000010 +[0DCh 0220 004h] Flags (decoded below) : 0000000E Physical package : 0 - ACPI Processor ID valid : 0 - Processor is a thread : 0 - Node is a leaf : 0 - Identical Implementation : 1 -[0E0h 0224 004h] Parent : 00000038 + ACPI Processor ID valid : 1 + Processor is a thread : 1 + Node is a leaf : 1 + Identical Implementation : 0 +[0E0h 0224 004h] Parent : 000000B0 [0E4h 0228 004h] ACPI Processor ID : 00000001 [0E8h 0232 004h] Private Resource Number : 00000000 [0ECh 0236 001h] Subtable Type : 00 [Processor Hierarchy Node] [0EDh 0237 001h] Length : 14 [0EEh 0238 002h] Reserved : 0000 [0F0h 0240 004h] Flags (decoded below) : 00000010 Physical package : 0 ACPI Processor ID valid : 0 Processor is a thread : 0 Node is a leaf : 0 Identical Implementation : 1 -[0F4h 0244 004h] Parent : 000000D8 -[0F8h 0248 004h] ACPI Processor ID : 00000000 +[0F4h 0244 004h] Parent : 00000094 +[0F8h 0248 004h] ACPI Processor ID : 00000001 [0FCh 0252 004h] Private Resource Number : 00000000 [100h 0256 001h] Subtable Type : 00 [Processor Hierarchy Node] [101h 0257 001h] Length : 14 [102h 0258 002h] Reserved : 0000 [104h 0260 004h] Flags (decoded below) : 0000000E Physical package : 0 ACPI Processor ID valid : 1 Processor is a thread : 1 Node is a leaf : 1 Identical Implementation : 0 [108h 0264 004h] Parent : 000000EC -[10Ch 0268 004h] ACPI Processor ID : 00000004 +[10Ch 0268 004h] ACPI Processor ID : 00000002 [110h 0272 004h] Private Resource Number : 00000000 [114h 0276 001h] Subtable Type : 00 [Processor Hierarchy Node] [115h 0277 001h] Length : 14 [116h 0278 002h] Reserved : 0000 [118h 0280 004h] Flags (decoded below) : 0000000E Physical package : 0 ACPI Processor ID valid : 1 Processor is a thread : 1 Node is a leaf : 1 Identical Implementation : 0 [11Ch 0284 004h] Parent : 000000EC -[120h 0288 004h] ACPI Processor ID : 00000005 +[120h 0288 004h] ACPI Processor ID : 00000003 [124h 0292 004h] Private Resource Number : 00000000 -[128h 0296 001h] Subtable Type : 00 [Processor Hierarchy Node] -[129h 0297 001h] Length : 14 +[128h 0296 001h] Subtable Type : 01 [Cache Type] +[129h 0297 001h] Length : 18 [12Ah 0298 002h] Reserved : 0000 -[12Ch 0300 004h] Flags (decoded below) : 00000010 +[12Ch 0300 004h] Flags (decoded below) : 0000007F + Size valid : 1 + Number of Sets valid : 1 + Associativity valid : 1 + Allocation Type valid : 1 + Cache Type valid : 1 + Write Policy valid : 1 + Line Size valid : 1 + Cache ID valid : 0 +[130h 0304 004h] Next Level of Cache : 00000000 +[134h 0308 004h] Size : 00200000 +[138h 0312 004h] Number of Sets : 00000800 +[13Ch 0316 001h] Associativity : 10 +[13Dh 0317 001h] Attributes : 0F + Allocation Type : 3 + Cache Type : 3 + Write Policy : 0 +[13Eh 0318 002h] Line Size : 0040 + +[140h 0320 001h] Subtable Type : 01 [Cache Type] +[141h 0321 001h] Length : 18 +[142h 0322 002h] Reserved : 0000 +[144h 0324 004h] Flags (decoded below) : 0000007F + Size valid : 1 + Number of Sets valid : 1 + Associativity valid : 1 + Allocation Type valid : 1 + Cache Type valid : 1 + Write Policy valid : 1 + Line Size valid : 1 + Cache ID valid : 0 +[148h 0328 004h] Next Level of Cache : 00000128 +[14Ch 0332 004h] Size : 00008000 +[150h 0336 004h] Number of Sets : 00000080 +[154h 0340 001h] Associativity : 04 +[155h 0341 001h] Attributes : 03 + Allocation Type : 3 + Cache Type : 0 + Write Policy : 0 +[156h 0342 002h] Line Size : 0040 + +[158h 0344 001h] Subtable Type : 01 [Cache Type] +[159h 0345 001h] Length : 18 +[15Ah 0346 002h] Reserved : 0000 +[15Ch 0348 004h] Flags (decoded below) : 0000007F + Size valid : 1 + Number of Sets valid : 1 + Associativity valid : 1 + Allocation Type valid : 1 + Cache Type valid : 1 + Write Policy valid : 1 + Line Size valid : 1 + Cache ID valid : 0 +[160h 0352 004h] Next Level of Cache : 00000128 +[164h 0356 004h] Size : 0000C000 +[168h 0360 004h] Number of Sets : 00000100 +[16Ch 0364 001h] Associativity : 03 +[16Dh 0365 001h] Attributes : 07 + Allocation Type : 3 + Cache Type : 1 + Write Policy : 0 +[16Eh 0366 002h] Line Size : 0040 + +[170h 0368 001h] Subtable Type : 00 [Processor Hierarchy Node] +[171h 0369 001h] Length : 1C +[172h 0370 002h] Reserved : 0000 +[174h 0372 004h] Flags (decoded below) : 00000010 + Physical package : 0 + ACPI Processor ID valid : 0 + Processor is a thread : 0 + Node is a leaf : 0 + Identical Implementation : 1 +[178h 0376 004h] Parent : 00000038 +[17Ch 0380 004h] ACPI Processor ID : 00000001 +[180h 0384 004h] Private Resource Number : 00000002 +[184h 0388 004h] Private Resource : 00000158 +[188h 0392 004h] Private Resource : 00000140 + +[18Ch 0396 001h] Subtable Type : 00 [Processor Hierarchy Node] +[18Dh 0397 001h] Length : 14 +[18Eh 0398 002h] Reserved : 0000 +[190h 0400 004h] Flags (decoded below) : 00000010 + Physical package : 0 + ACPI Processor ID valid : 0 + Processor is a thread : 0 + Node is a leaf : 0 + Identical Implementation : 1 +[194h 0404 004h] Parent : 00000170 +[198h 0408 004h] ACPI Processor ID : 00000000 +[19Ch 0412 004h] Private Resource Number : 00000000 + +[1A0h 0416 001h] Subtable Type : 00 [Processor Hierarchy Node] +[1A1h 0417 001h] Length : 14 +[1A2h 0418 002h] Reserved : 0000 +[1A4h 0420 004h] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 + Processor is a thread : 1 + Node is a leaf : 1 + Identical Implementation : 0 +[1A8h 0424 004h] Parent : 0000018C +[1ACh 0428 004h] ACPI Processor ID : 00000004 +[1B0h 0432 004h] Private Resource Number : 00000000 + +[1B4h 0436 001h] Subtable Type : 00 [Processor Hierarchy Node] +[1B5h 0437 001h] Length : 14 +[1B6h 0438 002h] Reserved : 0000 +[1B8h 0440 004h] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 + Processor is a thread : 1 + Node is a leaf : 1 + Identical Implementation : 0 +[1BCh 0444 004h] Parent : 0000018C +[1C0h 0448 004h] ACPI Processor ID : 00000005 +[1C4h 0452 004h] Private Resource Number : 00000000 + +[1C8h 0456 001h] Subtable Type : 00 [Processor Hierarchy Node] +[1C9h 0457 001h] Length : 14 +[1CAh 0458 002h] Reserved : 0000 +[1CCh 0460 004h] Flags (decoded below) : 00000010 Physical package : 0 ACPI Processor ID valid : 0 Processor is a thread : 0 Node is a leaf : 0 Identical Implementation : 1 -[130h 0304 004h] Parent : 000000D8 -[134h 0308 004h] ACPI Processor ID : 00000001 -[138h 0312 004h] Private Resource Number : 00000000 - -[13Ch 0316 001h] Subtable Type : 00 [Processor Hierarchy Node] -[13Dh 0317 001h] Length : 14 -[13Eh 0318 002h] Reserved : 0000 -[140h 0320 004h] Flags (decoded below) : 0000000E +[1D0h 0464 004h] Parent : 00000170 +[1D4h 0468 004h] ACPI Processor ID : 00000001 +[1D8h 0472 004h] Private Resource Number : 00000000 + +[1DCh 0476 001h] Subtable Type : 00 [Processor Hierarchy Node] +[1DDh 0477 001h] Length : 14 +[1DEh 0478 002h] Reserved : 0000 +[1E0h 0480 004h] Flags (decoded below) : 0000000E Physical package : 0 ACPI Processor ID valid : 1 Processor is a thread : 1 Node is a leaf : 1 Identical Implementation : 0 -[144h 0324 004h] Parent : 00000128 -[148h 0328 004h] ACPI Processor ID : 00000006 -[14Ch 0332 004h] Private Resource Number : 00000000 - -[150h 0336 001h] Subtable Type : 00 [Processor Hierarchy Node] -[151h 0337 001h] Length : 14 -[152h 0338 002h] Reserved : 0000 -[154h 0340 004h] Flags (decoded below) : 0000000E +[1E4h 0484 004h] Parent : 000001C8 +[1E8h 0488 004h] ACPI Processor ID : 00000006 +[1ECh 0492 004h] Private Resource Number : 00000000 + +[1F0h 0496 001h] Subtable Type : 00 [Processor Hierarchy Node] +[1F1h 0497 001h] Length : 14 +[1F2h 0498 002h] Reserved : 0000 +[1F4h 0500 004h] Flags (decoded below) : 0000000E Physical package : 0 ACPI Processor ID valid : 1 Processor is a thread : 1 Node is a leaf : 1 Identical Implementation : 0 -[158h 0344 004h] Parent : 00000128 -[15Ch 0348 004h] ACPI Processor ID : 00000007 -[160h 0352 004h] Private Resource Number : 00000000 +[1F8h 0504 004h] Parent : 000001C8 +[1FCh 0508 004h] ACPI Processor ID : 00000007 +[200h 0512 004h] Private Resource Number : 00000000 -Raw Table Data: Length 356 (0x164) +Raw Table Data: Length 516 (0x204) - 0000: 50 50 54 54 64 01 00 00 02 97 42 4F 43 48 53 20 // PPTTd.....BOCHS + 0000: 50 50 54 54 04 02 00 00 02 B8 42 4F 43 48 53 20 // PPTT......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 00 14 00 00 11 00 00 00 00 00 00 00 // ................ 0030: 00 00 00 00 00 00 00 00 00 14 00 00 11 00 00 00 // ................ - 0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $............... - 0050: 10 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8........... - 0060: 00 14 00 00 10 00 00 00 4C 00 00 00 00 00 00 00 // ........L....... - 0070: 00 00 00 00 00 14 00 00 0E 00 00 00 60 00 00 00 // ............`... - 0080: 00 00 00 00 00 00 00 00 00 14 00 00 0E 00 00 00 // ................ - 0090: 60 00 00 00 01 00 00 00 00 00 00 00 00 14 00 00 // `............... - 00A0: 10 00 00 00 4C 00 00 00 01 00 00 00 00 00 00 00 // ....L........... - 00B0: 00 14 00 00 0E 00 00 00 9C 00 00 00 02 00 00 00 // ................ - 00C0: 00 00 00 00 00 14 00 00 0E 00 00 00 9C 00 00 00 // ................ - 00D0: 03 00 00 00 00 00 00 00 00 14 00 00 10 00 00 00 // ................ - 00E0: 38 00 00 00 01 00 00 00 00 00 00 00 00 14 00 00 // 8............... - 00F0: 10 00 00 00 D8 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0100: 00 14 00 00 0E 00 00 00 EC 00 00 00 04 00 00 00 // ................ + 0040: 24 00 00 00 00 00 00 00 00 00 00 00 01 18 00 00 // $............... + 0050: 7F 00 00 00 00 00 00 00 00 00 20 00 00 08 00 00 // .......... ..... + 0060: 10 0F 40 00 01 18 00 00 7F 00 00 00 4C 00 00 00 // ..@.........L... + 0070: 00 80 00 00 80 00 00 00 04 03 40 00 01 18 00 00 // ..........@..... + 0080: 7F 00 00 00 4C 00 00 00 00 C0 00 00 00 01 00 00 // ....L........... + 0090: 03 07 40 00 00 1C 00 00 10 00 00 00 38 00 00 00 // ..@.........8... + 00A0: 00 00 00 00 02 00 00 00 7C 00 00 00 64 00 00 00 // ........|...d... + 00B0: 00 14 00 00 10 00 00 00 94 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 14 00 00 0E 00 00 00 B0 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 14 00 00 0E 00 00 00 // ................ + 00E0: B0 00 00 00 01 00 00 00 00 00 00 00 00 14 00 00 // ................ + 00F0: 10 00 00 00 94 00 00 00 01 00 00 00 00 00 00 00 // ................ + 0100: 00 14 00 00 0E 00 00 00 EC 00 00 00 02 00 00 00 // ................ 0110: 00 00 00 00 00 14 00 00 0E 00 00 00 EC 00 00 00 // ................ - 0120: 05 00 00 00 00 00 00 00 00 14 00 00 10 00 00 00 // ................ - 0130: D8 00 00 00 01 00 00 00 00 00 00 00 00 14 00 00 // ................ - 0140: 0E 00 00 00 28 01 00 00 06 00 00 00 00 00 00 00 // ....(........... - 0150: 00 14 00 00 0E 00 00 00 28 01 00 00 07 00 00 00 // ........(....... - 0160: 00 00 00 00 // .... + 0120: 03 00 00 00 00 00 00 00 01 18 00 00 7F 00 00 00 // ................ + 0130: 00 00 00 00 00 00 20 00 00 08 00 00 10 0F 40 00 // ...... .......@. + 0140: 01 18 00 00 7F 00 00 00 28 01 00 00 00 80 00 00 // ........(....... + 0150: 80 00 00 00 04 03 40 00 01 18 00 00 7F 00 00 00 // ......@......... + 0160: 28 01 00 00 00 C0 00 00 00 01 00 00 03 07 40 00 // (.............@. + 0170: 00 1C 00 00 10 00 00 00 38 00 00 00 01 00 00 00 // ........8....... + 0180: 02 00 00 00 58 01 00 00 40 01 00 00 00 14 00 00 // ....X...@....... + 0190: 10 00 00 00 70 01 00 00 00 00 00 00 00 00 00 00 // ....p........... + 01A0: 00 14 00 00 0E 00 00 00 8C 01 00 00 04 00 00 00 // ................ + 01B0: 00 00 00 00 00 14 00 00 0E 00 00 00 8C 01 00 00 // ................ + 01C0: 05 00 00 00 00 00 00 00 00 14 00 00 10 00 00 00 // ................ + 01D0: 70 01 00 00 01 00 00 00 00 00 00 00 00 14 00 00 // p............... + 01E0: 0E 00 00 00 C8 01 00 00 06 00 00 00 00 00 00 00 // ................ + 01F0: 00 14 00 00 0E 00 00 00 C8 01 00 00 07 00 00 00 // ................ + 0200: 00 00 00 00 // .... Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com> Message-id: 20260311160609.358-9-alireza.sanaee@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/data/acpi/aarch64/virt/PPTT.topology | Bin 356 -> 516 bytes tests/qtest/bios-tables-test-allowed-diff.h | 3 --- 2 files changed, 3 deletions(-) diff --git a/tests/data/acpi/aarch64/virt/PPTT.topology b/tests/data/acpi/aarch64/virt/PPTT.topology index XXXXXXX..XXXXXXX 100644 GIT binary patch literal 516 zcmZvXy$!-Z4255QAXNNF6ciL!P%r{zlr$7bL?T57U;qX{A_Gt|2qk4ohG7Wa3wP0p z#END6^S#(Ein5GDAbe%Ve19@oRpf>i08p-oC9qKR&9aThf)#M<Y6DDw`7DLw2leXq zLmd6_hCL38k`!1|$8txPaXnn=XBC{Q-b1-FvMKYYs}()g-e8&2`b^pnU2|HqTCvC? zcf+qVz1z0>Vcoy2<qdlSw@IRz6_Zp2=W4%;a%XmzJ6SxyMjmt8PHwetg0c5b_lhN! FeE|+Z9RUCU literal 356 zcmWFt2nk7HWME*L?&R<65v<@85#X!<1VAAM5F11@h%hh+f@ov_6;nYI69Dopu!#Af ziSYsX2{^>Sc7o)9c7V(S=|vU;>74__Oh60<Ky@%NW+X9~TafjF#BRXUfM}@RH$Wx} cOdLs!6-f-H7uh_Jy&6CPHY9a0F?OgJ00?&w0RR91 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/PPTT", -"tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt", -"tests/data/acpi/aarch64/virt/PPTT.topology", -- 2.43.0 From: Alessandro Ratti <alessandro@0x65c.net> The OMAP CP15 registers are only relevant to system-mode emulation of OMAP SoCs. Move them out of the monolithic helper.c into a dedicated file, following the pattern of cpregs-pmu.c and cpregs-gcs.c. This reduces the size of helper.c and compiles the OMAP-specific code out of CONFIG_USER_ONLY builds. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alessandro Ratti <alessandro@0x65c.net> Message-id: 20260405180826.729652-1-alessandro@0x65c.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpregs-omap-stub.c | 10 ++++ target/arm/cpregs-omap.c | 88 +++++++++++++++++++++++++++++++++++ target/arm/helper.c | 79 +------------------------------ target/arm/internals.h | 2 + target/arm/meson.build | 2 + 5 files changed, 103 insertions(+), 78 deletions(-) create mode 100644 target/arm/cpregs-omap-stub.c create mode 100644 target/arm/cpregs-omap.c diff --git a/target/arm/cpregs-omap-stub.c b/target/arm/cpregs-omap-stub.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/target/arm/cpregs-omap-stub.c @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "qemu/osdep.h" +#include "target/arm/cpu-qom.h" +#include "internals.h" + +void define_omap_cp_regs(ARMCPU *cpu) +{ + g_assert_not_reached(); +} diff --git a/target/arm/cpregs-omap.c b/target/arm/cpregs-omap.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/target/arm/cpregs-omap.c @@ -XXX,XX +XXX,XX @@ +/* + * QEMU ARM OMAP CP15 register definitions + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "target/arm/cpu.h" +#include "target/arm/cpregs.h" +#include "target/arm/internals.h" + +static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_ticonfig = value & 0xe7; + /* The OS_TYPE bit in this register changes the reported CPUID! */ + env->cp15.c0_cpuid = (value & (1 << 5)) ? + ARM_CPUID_TI915T : ARM_CPUID_TI925T; +} + +static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_threadid = value & 0xffff; +} + +static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Wait-for-interrupt (deprecated) */ + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); +} + +static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * On OMAP there are registers indicating the max/min index of dcache lines + * containing a dirty line; cache flush operations have to reset these. + */ + env->cp15.c15_i_max = 0x000; + env->cp15.c15_i_min = 0xff0; +} + +static const ARMCPRegInfo omap_cp_reginfo[] = { + { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, + .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, + .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), + .resetvalue = 0, }, + { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_NOP }, + { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, + .writefn = omap_ticonfig_write }, + { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, + { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0xff0, + .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, + { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, + .writefn = omap_threadid_write }, + { .name = "TI925T_STATUS", .cp = 15, .crn = 15, + .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, + .type = ARM_CP_NO_RAW, + .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, + /* + * TODO: Peripheral port remap register: + * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller + * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), + * when MMU is off. + */ + { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, + .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, + .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, + .writefn = omap_cachemaint_write }, + { .name = "C9", .cp = 15, .crn = 9, + .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, + .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, +}; + +void define_omap_cp_regs(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, omap_cp_reginfo); +} diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ttbcr2_reginfo = { }, }; -static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_ticonfig = value & 0xe7; - /* The OS_TYPE bit in this register changes the reported CPUID! */ - env->cp15.c0_cpuid = (value & (1 << 5)) ? - ARM_CPUID_TI915T : ARM_CPUID_TI925T; -} - -static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_threadid = value & 0xffff; -} - -static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ -#ifdef CONFIG_USER_ONLY - g_assert_not_reached(); -#else - /* Wait-for-interrupt (deprecated) */ - cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); -#endif -} - -static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * On OMAP there are registers indicating the max/min index of dcache lines - * containing a dirty line; cache flush operations have to reset these. - */ - env->cp15.c15_i_max = 0x000; - env->cp15.c15_i_min = 0xff0; -} - -static const ARMCPRegInfo omap_cp_reginfo[] = { - { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, - .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), - .resetvalue = 0, }, - { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .type = ARM_CP_NOP }, - { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, - .writefn = omap_ticonfig_write }, - { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, - { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, .resetvalue = 0xff0, - .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, - { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, - .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, - .writefn = omap_threadid_write }, - { .name = "TI925T_STATUS", .cp = 15, .crn = 15, - .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, - .type = ARM_CP_NO_RAW, - .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, - /* - * TODO: Peripheral port remap register: - * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller - * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), - * when MMU is off. - */ - { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, - .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, - .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, - .writefn = omap_cachemaint_write }, - { .name = "C9", .cp = 15, .crn = 9, - .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, - .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, -}; - static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { /* * RAZ/WI the whole crn=15 space, when we don't have a more specific @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_OMAPCP)) { - define_arm_cp_regs(cpu, omap_cp_reginfo); + define_omap_cp_regs(cpu); } if (arm_feature(env, ARM_FEATURE_STRONGARM)) { define_arm_cp_regs(cpu, strongarm_cp_reginfo); diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ void define_at_insn_regs(ARMCPU *cpu); void define_pm_cpregs(ARMCPU *cpu); /* Add the cpreg definitions for GCS cpregs */ void define_gcs_cpregs(ARMCPU *cpu); +/* Add the cpreg definitions for OMAP CP15 regs */ +void define_omap_cp_regs(ARMCPU *cpu); /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) diff --git a/target/arm/meson.build b/target/arm/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -XXX,XX +XXX,XX @@ arm_user_ss.add(files( 'helper.c', 'vfp_fpscr.c', 'el2-stubs.c', + 'cpregs-omap-stub.c', )) arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('common-semi-target.c')) @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add(files( 'arm-powerctl.c', 'cortex-regs.c', 'cpregs-gcs.c', + 'cpregs-omap.c', 'cpregs-pmu.c', 'cpu-irq.c', 'debug_helper.c', -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> This new header defines a new type for target virtual address, independent from TCGv and is parameterized by a new define TCG_ADDRESS_BITS (name was suggested by Paolo instead of TARGET_ADDRESS_BITS). By default, tcg-op.h include set this define to TARGET_LONG_BITS, but it's also possible to include only tcg-op-common.h and tcg-op-mem.h and set TCG_ADDRESS_BITS manually, which is what next commits will do. We preserve existing MIT license when extracting this new header. Implemented from: https://lore.kernel.org/qemu-devel/a68321f0-3d54-4909-864c-9793cda05b2a@linaro.org/ Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++++++++++ include/tcg/tcg-op.h | 100 +------------------------------ 2 files changed, 129 insertions(+), 97 deletions(-) create mode 100644 include/tcg/tcg-op-mem.h diff --git a/include/tcg/tcg-op-mem.h b/include/tcg/tcg-op-mem.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/tcg/tcg-op-mem.h @@ -XXX,XX +XXX,XX @@ +/* SPDX-License-Identifier: MIT */ +/* + * Target dependent memory related functions. + * + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TCG_TCG_OP_MEM_H +#define TCG_TCG_OP_MEM_H + +#ifndef TCG_ADDRESS_BITS +#error TCG_ADDRESS_BITS must be defined +#endif + +#if TCG_ADDRESS_BITS == 32 +typedef TCGv_i32 TCGv_va; +#define TCG_TYPE_VA TCG_TYPE_I32 +#define tcgv_va_temp tcgv_i32_temp +#define tcgv_va_temp_new tcg_temp_new_i32 +#elif TCG_ADDRESS_BITS == 64 +typedef TCGv_i64 TCGv_va; +#define TCG_TYPE_VA TCG_TYPE_I64 +#define tcgv_va_temp tcgv_i64_temp +#define tcgv_va_temp_new tcg_temp_new_i64 +#else +#error +#endif + +static inline void +tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_ld_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); +} + +static inline void +tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv_va a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_st_i32_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); +} + +static inline void +tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_ld_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); +} + +static inline void +tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv_va a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_st_i64_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); +} + +static inline void +tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_ld_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); +} + +static inline void +tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv_va a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_st_i128_chk(v, tcgv_va_temp(a), i, m, TCG_TYPE_VA); +} + +#define DEF_ATOMIC2(N, S) \ + static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S v, \ + TCGArg i, MemOp m) \ + { N##_##S##_chk(r, tcgv_va_temp(a), v, i, m, TCG_TYPE_VA); } + +#define DEF_ATOMIC3(N, S) \ + static inline void N##_##S(TCGv_##S r, TCGv_va a, TCGv_##S o, \ + TCGv_##S n, TCGArg i, MemOp m) \ + { N##_##S##_chk(r, tcgv_va_temp(a), o, n, i, m, TCG_TYPE_VA); } + +DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32) +DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64) +DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128) + +DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32) +DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64) +DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128) + +DEF_ATOMIC2(tcg_gen_atomic_xchg, i32) +DEF_ATOMIC2(tcg_gen_atomic_xchg, i64) +DEF_ATOMIC2(tcg_gen_atomic_xchg, i128) + +DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i128) +DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i128) +DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64) + +DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) + +#undef DEF_ATOMIC2 +#undef DEF_ATOMIC3 + +#endif /* TCG_TCG_OP_MEM_H */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index XXXXXXX..XXXXXXX 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -XXX,XX +XXX,XX @@ #error must include QEMU headers #endif +#define TCG_ADDRESS_BITS TARGET_LONG_BITS +#include "tcg/tcg-op-mem.h" + #if TARGET_LONG_BITS == 32 # define TCG_TYPE_TL TCG_TYPE_I32 #elif TARGET_LONG_BITS == 64 @@ -XXX,XX +XXX,XX @@ typedef TCGv_i64 TCGv; #error Unhandled TARGET_LONG_BITS value #endif -static inline void -tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) -{ - tcg_gen_qemu_ld_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); -} - -static inline void -tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) -{ - tcg_gen_qemu_st_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); -} - -static inline void -tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m) -{ - tcg_gen_qemu_ld_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); -} - -static inline void -tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m) -{ - tcg_gen_qemu_st_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); -} - -static inline void -tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) -{ - tcg_gen_qemu_ld_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); -} - -static inline void -tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) -{ - tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); -} - -#define DEF_ATOMIC2(N, S) \ - static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \ - TCGArg i, MemOp m) \ - { N##_##S##_chk(r, tcgv_tl_temp(a), v, i, m, TCG_TYPE_TL); } - -#define DEF_ATOMIC3(N, S) \ - static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S o, \ - TCGv_##S n, TCGArg i, MemOp m) \ - { N##_##S##_chk(r, tcgv_tl_temp(a), o, n, i, m, TCG_TYPE_TL); } - -DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32) -DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64) -DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128) - -DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32) -DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64) -DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128) - -DEF_ATOMIC2(tcg_gen_atomic_xchg, i32) -DEF_ATOMIC2(tcg_gen_atomic_xchg, i64) -DEF_ATOMIC2(tcg_gen_atomic_xchg, i128) - -DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32) -DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64) -DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32) -DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64) -DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i128) -DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32) -DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64) -DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i128) -DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32) -DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64) -DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32) -DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64) -DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32) -DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64) -DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32) -DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64) -DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32) -DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64) - -DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32) -DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64) -DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32) -DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64) -DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32) -DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64) -DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32) -DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64) -DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32) -DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64) -DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32) -DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64) -DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32) -DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64) -DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32) -DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) - -#undef DEF_ATOMIC2 -#undef DEF_ATOMIC3 - #if TARGET_LONG_BITS == 64 #define tcg_gen_movi_tl tcg_gen_movi_i64 #define tcg_gen_mov_tl tcg_gen_mov_i64 -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Include tcg-op-common.h instead, and include target specific tcg-op.h in files needing it. This intermediate step allows to clean up every file (TCGv, tcg_gen.*_tl.*) in separate commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/translate-sme.c | 1 + target/arm/tcg/translate-sve.c | 1 + target/arm/tcg/translate.c | 1 + target/arm/tcg/translate.h | 2 +- 5 files changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -XXX,XX +XXX,XX @@ #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" +#include "tcg/tcg-op.h" #include "qemu/log.h" #include "arm_ldst.h" #include "semihosting/semihost.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -XXX,XX +XXX,XX @@ #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" +#include "tcg/tcg-op.h" /* * Include the generated decoder. diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -XXX,XX +XXX,XX @@ #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" +#include "tcg/tcg-op.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ #include "translate.h" #include "translate-a32.h" +#include "tcg/tcg-op.h" #include "qemu/log.h" #include "arm_ldst.h" #include "semihosting/semihost.h" diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -XXX,XX +XXX,XX @@ #define TARGET_ARM_TRANSLATE_H #include "cpu.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg/tcg-op-gvec.h" #include "exec/translator.h" #include "exec/translation-block.h" -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Include tcg-op-gvec-common.h instead. No target/arm code rely on target specifics for gvec ops. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-4-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -XXX,XX +XXX,XX @@ #include "cpu.h" #include "tcg/tcg-op-common.h" -#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-op-gvec-common.h" #include "exec/translator.h" #include "exec/translation-block.h" #include "helper.h" -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> We need to stub a64_translate_init and gen_a64_update_pc. At this point, we don't need to do anything for aarch64_translator_ops since it's just an external symbol. We can now include target/arm/tcg/translate.h from common code, since all target specific bits have been removed, or can be specialized with specific defines. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/meson.build | 1 + target/arm/tcg/stubs32.c | 17 +++++++++++++++++ target/arm/tcg/translate.h | 10 ---------- 3 files changed, 18 insertions(+), 10 deletions(-) create mode 100644 target/arm/tcg/stubs32.c diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -XXX,XX +XXX,XX @@ gen_a32 = [ arm_ss.add(gen_a32) arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64) +arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs32.c')) arm_ss.add(files( 'cpu32.c', diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/target/arm/tcg/stubs32.c @@ -XXX,XX +XXX,XX @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "target/arm/tcg/translate.h" + + +void gen_a64_update_pc(DisasContext *s, int64_t diff) +{ + g_assert_not_reached(); +} + +void a64_translate_init(void) +{ + /* Don't initialize for 32 bits. Call site will be fixed later. */ +} diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -XXX,XX +XXX,XX @@ static inline int curr_insn_len(DisasContext *s) /* CPU state was modified dynamically; no need to exit, but do not chain. */ #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 -#ifdef TARGET_AARCH64 void a64_translate_init(void); void gen_a64_update_pc(DisasContext *s, int64_t diff); extern const TranslatorOps aarch64_translator_ops; -#else -static inline void a64_translate_init(void) -{ -} - -static inline void gen_a64_update_pc(DisasContext *s, int64_t diff) -{ -} -#endif void arm_test_cc(DisasCompare *cmp, int cc); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Generated decode files must be duplicated between user and system, as they are generated in private folders per libs, and can't be included otherwise, as meson does not give control on output folder. Indeed, meson generator is a different approach than custom_target, and this is a limitation by design. They were already duplicated between arch variants anyway, so nothing new here. They will now be compiled once for system binaries, and still per target for user binaries. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-6-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/meson.build | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -XXX,XX +XXX,XX @@ gen_a64 = [ decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'), ] +vfp_d = [ + decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), + decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), +] + gen_a32 = [ decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), - decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), - decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), decodetree.process('mve.decode', extra_args: '--decode=disas_mve'), decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( 'translate-m-nocp.c', 'translate-mve.c', 'translate-neon.c', - 'translate-vfp.c', 'm_helper.c', 'mve_helper.c', 'op_helper.c', @@ -XXX,XX +XXX,XX @@ arm_common_ss.add(files( 'crypto_helper.c', )) -arm_common_system_ss.add(files( +arm_common_system_ss.add( + vfp_d, + files( 'cpregs-at.c', 'debug.c', 'hflags.c', @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add(files( 'psci.c', 'tlb_helper.c', 'tlb-insns.c', + 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', )) -arm_user_ss.add(files( +arm_user_ss.add( + vfp_d, + files( 'debug.c', 'hflags.c', 'neon_helper.c', 'tlb_helper.c', + 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', )) -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-7-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/meson.build | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -XXX,XX +XXX,XX @@ vfp_d = [ decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), ] -gen_a32 = [ +neon_d = [ decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), +] + +gen_a32 = [ decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), decodetree.process('mve.decode', extra_args: '--decode=disas_mve'), decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( 'translate.c', 'translate-m-nocp.c', 'translate-mve.c', - 'translate-neon.c', 'm_helper.c', 'mve_helper.c', 'op_helper.c', @@ -XXX,XX +XXX,XX @@ arm_common_ss.add(files( )) arm_common_system_ss.add( + neon_d, vfp_d, files( 'cpregs-at.c', @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add( 'psci.c', 'tlb_helper.c', 'tlb-insns.c', + 'translate-neon.c', 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', )) arm_user_ss.add( + neon_d, vfp_d, files( 'debug.c', 'hflags.c', 'neon_helper.c', 'tlb_helper.c', + 'translate-neon.c', 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-8-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/meson.build | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -XXX,XX +XXX,XX @@ neon_d = [ decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), ] +mve_d = decodetree.process('mve.decode', extra_args: '--decode=disas_mve') + gen_a32 = [ decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), - decodetree.process('mve.decode', extra_args: '--decode=disas_mve'), decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( 'gengvec.c', 'translate.c', 'translate-m-nocp.c', - 'translate-mve.c', 'm_helper.c', 'mve_helper.c', 'op_helper.c', @@ -XXX,XX +XXX,XX @@ arm_common_ss.add(files( )) arm_common_system_ss.add( + mve_d, neon_d, vfp_d, files( @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add( 'psci.c', 'tlb_helper.c', 'tlb-insns.c', + 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', )) arm_user_ss.add( + mve_d, neon_d, vfp_d, files( @@ -XXX,XX +XXX,XX @@ arm_user_ss.add( 'hflags.c', 'neon_helper.c', 'tlb_helper.c', + 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', 'vec_helper.c', -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-9-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/meson.build | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -XXX,XX +XXX,XX @@ neon_d = [ mve_d = decodetree.process('mve.decode', extra_args: '--decode=disas_mve') +m_nocp_d = decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp') + gen_a32 = [ - decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( 'cpu32.c', 'gengvec.c', 'translate.c', - 'translate-m-nocp.c', 'm_helper.c', 'mve_helper.c', 'op_helper.c', @@ -XXX,XX +XXX,XX @@ arm_common_ss.add(files( )) arm_common_system_ss.add( + m_nocp_d, mve_d, neon_d, vfp_d, @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add( 'psci.c', 'tlb_helper.c', 'tlb-insns.c', + 'translate-m-nocp.c', 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add( 'vfp_helper.c', )) arm_user_ss.add( + m_nocp_d, mve_d, neon_d, vfp_d, @@ -XXX,XX +XXX,XX @@ arm_user_ss.add( 'hflags.c', 'neon_helper.c', 'tlb_helper.c', + 'translate-m-nocp.c', 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Remove unused header accel/tcg/cpu-ldst.h that has target specifics. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-10-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/meson.build | 3 ++- target/arm/tcg/op_helper.c | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( 'translate.c', 'm_helper.c', 'mve_helper.c', - 'op_helper.c', )) arm_ss.add(when: 'TARGET_AARCH64', if_true: files( @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add( 'debug.c', 'hflags.c', 'neon_helper.c', + 'op_helper.c', 'psci.c', 'tlb_helper.c', 'tlb-insns.c', @@ -XXX,XX +XXX,XX @@ arm_user_ss.add( 'debug.c', 'hflags.c', 'neon_helper.c', + 'op_helper.c', 'tlb_helper.c', 'translate-m-nocp.c', 'translate-mve.c', diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -XXX,XX +XXX,XX @@ #include "helper.h" #include "internals.h" #include "cpu-features.h" -#include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "cpregs.h" -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-11-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs32.c')) arm_ss.add(files( 'cpu32.c', - 'gengvec.c', 'translate.c', 'm_helper.c', 'mve_helper.c', @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add( 'cpregs-at.c', 'debug.c', 'hflags.c', + 'gengvec.c', 'neon_helper.c', 'op_helper.c', 'psci.c', @@ -XXX,XX +XXX,XX @@ arm_user_ss.add( vfp_d, files( 'debug.c', + 'gengvec.c', 'hflags.c', 'neon_helper.c', 'op_helper.c', -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> dc->be_data is already set just above in the same function: ``` dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; ``` Cc: qemu-stable@nongnu.org Fixes: a729a46b05a ("target/arm: Add wrapper macros for accessing tbflags") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-12-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled = 1; - dc->be_data = MO_TE; dc->v7m_handler_mode = EX_TBFLAG_M32(tb_flags, HANDLER); dc->v8m_secure = EX_TBFLAG_M32(tb_flags, SECURE); dc->v8m_stackcheck = EX_TBFLAG_M32(tb_flags, STACKCHECK); -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-13-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) * fields here. */ uint32_t condexec_bits; - target_ulong pc_arg = dc->base.pc_next; + uint32_t pc_arg = dc->base.pc_next; if (tb_cflags(dcbase->tb) & CF_PCREL) { pc_arg &= ~TARGET_PAGE_MASK; @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) bool is_16bit; /* TCG op to rewind to if this turns out to be an invalid ECI state */ TCGOp *insn_eci_rewind = NULL; - target_ulong insn_eci_pc_save = -1; + uint32_t insn_eci_pc_save = -1; /* Misaligned thumb PC is architecturally impossible. */ assert((dc->base.pc_next & 1) == 0); -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> This allows to get rid of TARGET_AARCH64, and helps with next patch which will define at runtime tcg address type, by adding a second entry point in a different source file. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-14-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/internals.h | 2 ++ target/arm/tcg/stubs32.c | 7 +++++++ target/arm/tcg/translate-a64.c | 9 +++++++++ target/arm/tcg/translate.c | 19 +++++++++---------- 4 files changed, 27 insertions(+), 10 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ void arm_init_cpreg_list(ARMCPU *cpu); void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb, + int *max_insns, vaddr pc, void *host_pc); void arm_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/stubs32.c +++ b/target/arm/tcg/stubs32.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" +#include "target/arm/internals.h" #include "target/arm/tcg/translate.h" @@ -XXX,XX +XXX,XX @@ void a64_translate_init(void) { /* Don't initialize for 32 bits. Call site will be fixed later. */ } + +void aarch64_translate_code(CPUState *cs, TranslationBlock *tb, + int *max_insns, vaddr pc, void *host_pc) +{ + g_assert_not_reached(); +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" #include "exec/target_page.h" +#include "exec/translator.h" #include "helper-a64.h" #include "helper-sme.h" #include "helper-sve.h" @@ -XXX,XX +XXX,XX @@ const TranslatorOps aarch64_translator_ops = { .translate_insn = aarch64_tr_translate_insn, .tb_stop = aarch64_tr_tb_stop, }; + +void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb, + int *max_insns, vaddr pc, void *host_pc) +{ + DisasContext dc = {}; + translator_loop(cpu, tb, max_insns, pc, host_pc, + &aarch64_translator_ops, &dc.base); +} diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ #include "semihosting/semihost.h" #include "cpregs.h" #include "exec/target_page.h" +#include "exec/translator.h" #include "helper.h" #include "helper-mve.h" @@ -XXX,XX +XXX,XX @@ static const TranslatorOps thumb_translator_ops = { void arm_translate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { - DisasContext dc = { }; - const TranslatorOps *ops = &arm_translator_ops; CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb); - if (EX_TBFLAG_AM32(tb_flags, THUMB)) { - ops = &thumb_translator_ops; - } -#ifdef TARGET_AARCH64 if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) { - ops = &aarch64_translator_ops; + aarch64_translate_code(cpu, tb, max_insns, pc, host_pc); + } else { + DisasContext dc = { }; + translator_loop(cpu, tb, max_insns, pc, host_pc, + (EX_TBFLAG_AM32(tb_flags, THUMB) + ? &thumb_translator_ops + : &arm_translator_ops), + &dc.base); } -#endif - - translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base); } -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> With TCG_ADDRESS_BITS mechanism, it's now possible to specify which variant every source file is written for. Compared to before, it means that addr_type will now vary per tb translation, where it was constant for a given target previously. Thus, we add new a parameter to translator_loop(). This will allow us to convert targets one by one. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260407222208.271838-15-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- accel/tcg/translate-all.c | 1 - accel/tcg/translator.c | 4 +++- include/exec/translator.h | 4 +++- target/alpha/translate.c | 3 ++- target/arm/tcg/translate-a64.c | 3 ++- target/arm/tcg/translate.c | 2 +- target/avr/translate.c | 3 ++- target/hexagon/translate.c | 3 ++- target/hppa/translate.c | 3 ++- target/i386/tcg/translate.c | 3 ++- target/loongarch/tcg/translate.c | 3 ++- target/m68k/translate.c | 3 ++- target/microblaze/translate.c | 3 ++- target/mips/tcg/translate.c | 3 ++- target/or1k/translate.c | 3 ++- target/ppc/translate.c | 3 ++- target/riscv/translate.c | 3 ++- target/rx/translate.c | 3 ++- target/s390x/tcg/translate.c | 3 ++- target/sh4/translate.c | 3 ++- target/sparc/translate.c | 3 ++- target/tricore/translate.c | 3 ++- target/xtensa/translate.c | 3 ++- 23 files changed, 45 insertions(+), 23 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index XXXXXXX..XXXXXXX 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s) } tcg_ctx->gen_tb = tb; - tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64; tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order; restart_translate: diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index XXXXXXX..XXXXXXX 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, vaddr dest) void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc, const TranslatorOps *ops, - DisasContextBase *db) + DisasContextBase *db, TCGType addr_type) { uint32_t cflags = tb_cflags(tb); TCGOp *icount_start_insn; TCGOp *first_insn_start = NULL; bool plugin_enabled; + tcg_ctx->addr_type = addr_type; + /* Initialize DisasContext */ db->tb = tb; db->pc_first = pc; diff --git a/include/exec/translator.h b/include/exec/translator.h index XXXXXXX..XXXXXXX 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -XXX,XX +XXX,XX @@ #include "exec/memop.h" #include "exec/vaddr.h" +#include "tcg/tcg.h" /** * DisasJumpType: @@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps { * @host_pc: host physical program counter address * @ops: Target-specific operations. * @db: Disassembly context. + * @addr_type: TCG Type for addresses (TCG_TYPE_VA). * * Generic translator loop. * @@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps { */ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc, const TranslatorOps *ops, - DisasContextBase *db); + DisasContextBase *db, TCGType addr_type); /** * translator_use_goto_tb diff --git a/target/alpha/translate.c b/target/alpha/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -XXX,XX +XXX,XX @@ void alpha_translate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { DisasContext dc; - translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base); + translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base, + TCG_TYPE_VA); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -XXX,XX +XXX,XX @@ void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb, { DisasContext dc = {}; translator_loop(cpu, tb, max_insns, pc, host_pc, - &aarch64_translator_ops, &dc.base); + &aarch64_translator_ops, &dc.base, + TCG_TYPE_VA); } diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ void arm_translate_code(CPUState *cpu, TranslationBlock *tb, (EX_TBFLAG_AM32(tb_flags, THUMB) ? &thumb_translator_ops : &arm_translator_ops), - &dc.base); + &dc.base, TCG_TYPE_VA); } } diff --git a/target/avr/translate.c b/target/avr/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -XXX,XX +XXX,XX @@ void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { DisasContext dc = { }; - translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base, + TCG_TYPE_VA); } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -XXX,XX +XXX,XX @@ void hexagon_translate_code(CPUState *cs, TranslationBlock *tb, DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, - &hexagon_tr_ops, &ctx.base); + &hexagon_tr_ops, &ctx.base, + TCG_TYPE_VA); } #define NAME_LEN 64 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -XXX,XX +XXX,XX @@ void hppa_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { DisasContext ctx = { }; - translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base, + TCG_TYPE_VA); } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -XXX,XX +XXX,XX @@ void x86_translate_code(CPUState *cpu, TranslationBlock *tb, { DisasContext dc; - translator_loop(cpu, tb, max_insns, pc, host_pc, &i386_tr_ops, &dc.base); + translator_loop(cpu, tb, max_insns, pc, host_pc, &i386_tr_ops, &dc.base, + TCG_TYPE_VA); } diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -XXX,XX +XXX,XX @@ void loongarch_translate_code(CPUState *cs, TranslationBlock *tb, DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, - &loongarch_tr_ops, &ctx.base); + &loongarch_tr_ops, &ctx.base, + TCG_TYPE_VA); } void loongarch_translate_init(void) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -XXX,XX +XXX,XX @@ void m68k_translate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { DisasContext dc; - translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base); + translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base, + TCG_TYPE_VA); } static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -XXX,XX +XXX,XX @@ void mb_translate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc) { DisasContext dc; - translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base); + translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base, + TCG_TYPE_VA); } void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -XXX,XX +XXX,XX @@ void mips_translate_code(CPUState *cs, TranslationBlock *tb, { DisasContext ctx; - translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base, + TCG_TYPE_VA); } void mips_tcg_init(void) diff --git a/target/or1k/translate.c b/target/or1k/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/or1k/translate.c +++ b/target/or1k/translate.c @@ -XXX,XX +XXX,XX @@ void openrisc_translate_code(CPUState *cs, TranslationBlock *tb, DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, - &openrisc_tr_ops, &ctx.base); + &openrisc_tr_ops, &ctx.base, + TCG_TYPE_VA); } void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -XXX,XX +XXX,XX @@ void ppc_translate_code(CPUState *cs, TranslationBlock *tb, { DisasContext ctx; - translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base, + TCG_TYPE_VA); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -XXX,XX +XXX,XX @@ void riscv_translate_code(CPUState *cs, TranslationBlock *tb, { DisasContext ctx; - translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base, + TCG_TYPE_VA); } void riscv_translate_init(void) diff --git a/target/rx/translate.c b/target/rx/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -XXX,XX +XXX,XX @@ void rx_translate_code(CPUState *cs, TranslationBlock *tb, { DisasContext dc; - translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base, + TCG_TYPE_VA); } #define ALLOC_REGISTER(sym, name) \ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -XXX,XX +XXX,XX @@ void s390x_translate_code(CPUState *cs, TranslationBlock *tb, { DisasContext dc; - translator_loop(cs, tb, max_insns, pc, host_pc, &s390x_tr_ops, &dc.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &s390x_tr_ops, &dc.base, + TCG_TYPE_VA); } void s390x_restore_state_to_opc(CPUState *cs, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -XXX,XX +XXX,XX @@ void sh4_translate_code(CPUState *cs, TranslationBlock *tb, { DisasContext ctx; - translator_loop(cs, tb, max_insns, pc, host_pc, &sh4_tr_ops, &ctx.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &sh4_tr_ops, &ctx.base, + TCG_TYPE_VA); } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -XXX,XX +XXX,XX @@ void sparc_translate_code(CPUState *cs, TranslationBlock *tb, { DisasContext dc = {}; - translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base); + translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base, + TCG_TYPE_VA); } void sparc_tcg_init(void) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -XXX,XX +XXX,XX @@ void tricore_translate_code(CPUState *cs, TranslationBlock *tb, { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, - &tricore_tr_ops, &ctx.base); + &tricore_tr_ops, &ctx.base, + TCG_TYPE_VA); } /* diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -XXX,XX +XXX,XX @@ void xtensa_translate_code(CPUState *cpu, TranslationBlock *tb, { DisasContext dc = {}; translator_loop(cpu, tb, max_insns, pc, host_pc, - &xtensa_translator_ops, &dc.base); + &xtensa_translator_ops, &dc.base, + TCG_TYPE_VA); } void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> We know this file is for 32-bit runtime target, so we can set TCG_ADDRESS_BITS. TCG_TYPE_VA is derived accordingly and is already passed to translator_loop. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260407222208.271838-16-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ #include "translate.h" #include "translate-a32.h" -#include "tcg/tcg-op.h" +#define TCG_ADDRESS_BITS 32 +#include "tcg/tcg-op-mem.h" #include "qemu/log.h" #include "arm_ldst.h" #include "semihosting/semihost.h" @@ -XXX,XX +XXX,XX @@ MemOp pow2_align(unsigned i) * that the address argument is TCGv_i32 rather than TCGv. */ -static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) +static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) { - TCGv addr = tcg_temp_new(); - tcg_gen_extu_i32_tl(addr, a32); + TCGv_va addr = tcgv_va_temp_new(); + tcg_gen_mov_i32(addr, a32); /* Not needed for user-mode BE32, where we use MO_BE instead. */ if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) { - tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE))); + tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE))); } return addr; } @@ -XXX,XX +XXX,XX @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr = gen_aa32_addr(s, a32, opc); + TCGv_va addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(val, addr, index, opc); } void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr = gen_aa32_addr(s, a32, opc); + TCGv_va addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(val, addr, index, opc); } void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr = gen_aa32_addr(s, a32, opc); + TCGv_va addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i64(val, addr, index, opc); @@ -XXX,XX +XXX,XX @@ void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr = gen_aa32_addr(s, a32, opc); + TCGv_va addr = gen_aa32_addr(s, a32, opc); /* Not needed for user-mode BE32, where we use MO_BE instead. */ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) { @@ -XXX,XX +XXX,XX @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, * architecturally 64-bit access, but instead do a 64-bit access * using MO_BE if appropriate and then split the two halves. */ - TCGv taddr = gen_aa32_addr(s, addr, opc); + TCGv_va taddr = gen_aa32_addr(s, addr, opc); tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc); tcg_gen_mov_i64(cpu_exclusive_val, t64); @@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, { TCGv_i32 t0, t1, t2; TCGv_i64 extaddr; - TCGv taddr; + TCGv_va taddr; TCGLabel *done_label; TCGLabel *fail_label; MemOp opc = size | MO_ALIGN | s->be_data; @@ -XXX,XX +XXX,XX @@ static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2) */ int mem_idx = get_mem_index(s); MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; - TCGv taddr = gen_aa32_addr(s, addr, opc); + TCGv_va taddr = gen_aa32_addr(s, addr, opc); TCGv_i64 t64 = tcg_temp_new_i64(); TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 tmp2 = tcg_temp_new_i32(); @@ -XXX,XX +XXX,XX @@ static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2) */ int mem_idx = get_mem_index(s); MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; - TCGv taddr = gen_aa32_addr(s, addr, opc); + TCGv_va taddr = gen_aa32_addr(s, addr, opc); TCGv_i32 t1 = load_reg(s, rt); TCGv_i32 t2 = load_reg(s, rt2); TCGv_i64 t64 = tcg_temp_new_i64(); @@ -XXX,XX +XXX,XX @@ DO_LDST(STRH, store, MO_UW) static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc) { TCGv_i32 addr, tmp; - TCGv taddr; + TCGv_va taddr; opc |= s->be_data; addr = load_reg(s, a->rn); -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Allows to reduce scope of target/arm/tcg/arm_ldst.h to aarch32 only. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-17-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -XXX,XX +XXX,XX @@ #include "translate-a64.h" #include "tcg/tcg-op.h" #include "qemu/log.h" -#include "arm_ldst.h" #include "semihosting/semihost.h" #include "cpregs.h" @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) if (pc & 3) { /* * PC alignment fault. This has priority over the instruction abort - * that we would receive from a translation fault via arm_ldl_code. + * that we would receive from a translation fault via translator_ldl_end. * This should only be possible after an indirect branch, at the * start of the TB. */ @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } s->pc_curr = pc; - insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); + /* Code is always little-endian on Aarch64 */ + insn = translator_ldl_end(env, &s->base, pc, MO_LE); s->insn = insn; s->base.pc_next = pc + 4; -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Only translate.c uses those functions, thus move them back to this file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260407222208.271838-18-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/arm_ldst.h | 47 -------------------------------------- target/arm/tcg/translate.c | 24 ++++++++++++++++++- 2 files changed, 23 insertions(+), 48 deletions(-) diff --git a/target/arm/tcg/arm_ldst.h b/target/arm/tcg/arm_ldst.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/arm_ldst.h +++ b/target/arm/tcg/arm_ldst.h @@ -XXX,XX +XXX,XX @@ -/* - * ARM load/store instructions for code (armeb-user support) - * - * Copyright (c) 2012 CodeSourcery, LLC - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef ARM_LDST_H -#define ARM_LDST_H - -#include "exec/translator.h" -#include "qemu/bswap.h" - -/* Load an instruction and return it in the standard little-endian order */ -static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s, - target_ulong addr, bool sctlr_b) -{ - return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b)); -} - -/* Ditto, for a halfword (Thumb) instruction */ -static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s, - target_ulong addr, bool sctlr_b) -{ -#ifndef CONFIG_USER_ONLY - /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped - within each word. Undo that now. */ - if (sctlr_b) { - addr ^= 2; - } -#endif - return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b)); -} - -#endif diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ #define TCG_ADDRESS_BITS 32 #include "tcg/tcg-op-mem.h" #include "qemu/log.h" -#include "arm_ldst.h" #include "semihosting/semihost.h" #include "cpregs.h" #include "exec/target_page.h" @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } } +/* Ditto, for a halfword (Thumb) instruction */ +static uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s, + target_ulong addr, bool sctlr_b) +{ +#ifndef CONFIG_USER_ONLY + /* + * In big-endian (BE32) mode, adjacent Thumb instructions have been swapped + * within each word. Undo that now. + */ + if (sctlr_b) { + addr ^= 2; + } +#endif + return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b)); +} + static bool insn_crosses_page(CPUARMState *env, DisasContext *s) { /* Return true if the insn at dc->base.pc_next might cross a page boundary. @@ -XXX,XX +XXX,XX @@ static void arm_post_translate_insn(DisasContext *dc) } } +/* Load an instruction and return it in the standard little-endian order */ +static uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s, + target_ulong addr, bool sctlr_b) +{ + return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b)); +} + static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260407222208.271838-19-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) static uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s, target_ulong addr, bool sctlr_b) { -#ifndef CONFIG_USER_ONLY - /* - * In big-endian (BE32) mode, adjacent Thumb instructions have been swapped - * within each word. Undo that now. - */ + MemOp end = MO_LE; if (sctlr_b) { + /* In BE32 mode, adjacent Thumb instructions are swapped. */ addr ^= 2; + end = MO_BE; } -#endif - return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b)); + return translator_lduw_end(env, s, addr, end); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) @@ -XXX,XX +XXX,XX @@ static void arm_post_translate_insn(DisasContext *dc) static uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s, target_ulong addr, bool sctlr_b) { - return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b)); + return translator_ldl_end(env, s, addr, sctlr_b ? MO_BE : MO_LE); } static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20260407222208.271838-20-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -XXX,XX +XXX,XX @@ static void arm_disas_set_info(const CPUState *cpu, disassemble_info *info) } info->endian = BFD_ENDIAN_LITTLE; - if (bswap_code(sctlr_b)) { - info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; - } info->flags &= ~INSN_ARM_BE32; -#ifndef CONFIG_USER_ONLY if (sctlr_b) { + info->endian |= BFD_ENDIAN_BIG; info->flags |= INSN_ARM_BE32; } -#endif } static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> We can replace it with uint32_t, because we know it's limited to 32-bit target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-21-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* Ditto, for a halfword (Thumb) instruction */ static uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s, - target_ulong addr, bool sctlr_b) + uint32_t addr, bool sctlr_b) { MemOp end = MO_LE; if (sctlr_b) { @@ -XXX,XX +XXX,XX @@ static void arm_post_translate_insn(DisasContext *dc) /* Load an instruction and return it in the standard little-endian order */ static uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s, - target_ulong addr, bool sctlr_b) + uint32_t addr, bool sctlr_b) { return translator_ldl_end(env, s, addr, sctlr_b ? MO_BE : MO_LE); } -- 2.43.0 From: Pierrick Bouvier <pierrick.bouvier@linaro.org> We removed all target specifics, and can finally compile this file only once. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20260407222208.271838-22-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/meson.build | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -XXX,XX +XXX,XX @@ mve_d = decodetree.process('mve.decode', extra_args: '--decode=disas_mve') m_nocp_d = decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp') -gen_a32 = [ +translate32_d = [ decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']), ] -arm_ss.add(gen_a32) arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64) arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs32.c')) arm_ss.add(files( 'cpu32.c', - 'translate.c', 'm_helper.c', 'mve_helper.c', )) @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add( m_nocp_d, mve_d, neon_d, + translate32_d, vfp_d, files( 'cpregs-at.c', @@ -XXX,XX +XXX,XX @@ arm_common_system_ss.add( 'psci.c', 'tlb_helper.c', 'tlb-insns.c', + 'translate.c', 'translate-m-nocp.c', 'translate-mve.c', 'translate-neon.c', @@ -XXX,XX +XXX,XX @@ arm_user_ss.add( m_nocp_d, mve_d, neon_d, + translate32_d, vfp_d, files( 'debug.c', @@ -XXX,XX +XXX,XX @@ arm_user_ss.add( 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', + 'translate.c', 'translate-m-nocp.c', 'translate-mve.c', 'translate-neon.c', -- 2.43.0 From: Philippe Mathieu-Daudé <philmd@linaro.org> Following commit 15500df3b3b ("target/arm/tcg/translate.h: replace target_ulong with vaddr") change, adapt guarded_page_br(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260401143456.79843-1-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/helper-a64-defs.h | 2 +- target/arm/tcg/helper-a64.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/helper-a64-defs.h +++ b/target/arm/tcg/helper-a64-defs.h @@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(cpyfm, void, env, i32, i32, i32) DEF_HELPER_4(cpyfe, void, env, i32, i32, i32) DEF_HELPER_FLAGS_1(guarded_page_check, TCG_CALL_NO_WG, void, env) -DEF_HELPER_FLAGS_2(guarded_page_br, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(guarded_page_br, TCG_CALL_NO_RWG, void, env, vaddr) DEF_HELPER_FLAGS_5(gvec_fdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) DEF_HELPER_FLAGS_5(gvec_fdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -XXX,XX +XXX,XX @@ void HELPER(cpyfe)(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, do_cpye(env, syndrome, wdesc, rdesc, false, GETPC()); } -static bool is_guarded_page(CPUARMState *env, target_ulong addr, uintptr_t ra) +static bool is_guarded_page(CPUARMState *env, vaddr addr, uintptr_t ra) { #ifdef CONFIG_USER_ONLY return page_get_flags(addr) & PAGE_BTI; @@ -XXX,XX +XXX,XX @@ void HELPER(guarded_page_check)(CPUARMState *env) } } -void HELPER(guarded_page_br)(CPUARMState *env, target_ulong pc) +void HELPER(guarded_page_br)(CPUARMState *env, vaddr pc) { /* * We have already checked for branch via x16 and x17. -- 2.43.0 From: Philippe Mathieu-Daudé <philmd@linaro.org> Similarly to commit 3580aa03547 ("target/arm/tcg/psci.c: make compilation unit common") which replaced the target_ulong use in arm_handle_psci_call(), replace the one in hvf_handle_psci_call. This could be vaddr, because entry is the start pc for the on-lining cpu, but we prefer uint64_t because this is what we get in param[] and pass to arm_set_cpu_on(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20260410194227.16357-1-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/hvf/hvf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu, int *excp_ret) bool target_aarch64 = true; CPUState *target_cpu_state; ARMCPU *target_cpu; - target_ulong entry; + uint64_t entry; int target_el = 1; int32_t ret = 0; -- 2.43.0 Ahmed Karaman has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the "Performance Tools and Tests" orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-2-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: rust/wrapper.h Miscellaneous ------------- Performance Tools and Tests -M: Ahmed Karaman <ahmedkhaledkaraman@gmail.com> -S: Maintained +S: Orphan F: scripts/performance/ Code Coverage Tools -- 2.43.0 Anup Patel has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-3-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: tests/functional/arm/test_canona1100.py F: docs/system/arm/digic.rst Goldfish RTC -M: Anup Patel <anup.patel@wdc.com> M: Alistair Francis <Alistair.Francis@wdc.com> L: qemu-riscv@nongnu.org S: Maintained -- 2.43.0 Beniamino Galvani has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-4-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: tests/functional/alpha/test_clipper.py ARM Machines ------------ Allwinner-a10 -M: Beniamino Galvani <b.galvani@gmail.com> M: Peter Maydell <peter.maydell@linaro.org> R: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> L: qemu-arm@nongnu.org -- 2.43.0 Jeff Cody has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the "VHDX" block driver orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-5-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ S: Supported F: block/rbd.c VHDX -M: Jeff Cody <codyprime@gmail.com> L: qemu-block@nongnu.org -S: Odd Fixes +S: Orphan F: block/vhdx* VDI -- 2.43.0 Coiby Xu has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the "Vhost-user block device backend server" orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-6-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ S: Supported F: tests/image-fuzzer/ Vhost-user block device backend server -M: Coiby Xu <Coiby.Xu@gmail.com> -S: Maintained +S: Orphan F: block/export/vhost-user-blk-server.c F: block/export/vhost-user-blk-server.h F: block/export/virtio-blk-handler.c -- 2.43.0 Damien Hedde has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-7-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: .gitlab-ci.d/opensbi/ Clock framework M: Luc Michel <luc@lmichel.fr> -R: Damien Hedde <damien.hedde@dahe.fr> S: Maintained F: include/hw/core/clock.h F: include/hw/core/qdev-clock.h -- 2.43.0 Ed Maste has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-8-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ W: https://gitlab.com/qemu-project/qemu/pipelines W: https://travis-ci.org/qemu/qemu FreeBSD Hosted Continuous Integration -M: Ed Maste <emaste@freebsd.org> M: Li-Wen Hsu <lwhsu@freebsd.org> S: Maintained F: .gitlab-ci.d/cirrus/freebsd* -- 2.43.0 Dongjiu Geng has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the "ACPI/HEST/GHES" section orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-9-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: tests/functional/x86_64/test_acpi_bits.py F: docs/devel/testing/acpi-bits.rst ACPI/HEST/GHES -R: Dongjiu Geng <gengdongjiu1@gmail.com> L: qemu-arm@nongnu.org -S: Maintained +S: Orphan F: hw/acpi/ghes.c F: include/hw/acpi/ghes.h F: docs/specs/acpi_hest_ghes.rst -- 2.43.0 Huai-Cheng Kuo has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes "PCIE DOE" orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-11-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: docs/specs/*pci* F: docs/system/sriov.rst PCIE DOE -M: Huai-Cheng Kuo <hchkuo@avery-design.com.tw> -S: Supported +S: Orphan F: include/hw/pci/pcie_doe.h F: hw/pci/pcie_doe.c -- 2.43.0 Bastian Koppelmann has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the Tricore TCG CPUs orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-12-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: include/hw/xtensa/xtensa-isa.h F: configs/devices/xtensa*/default.mak TriCore TCG CPUs -M: Bastian Koppelmann <kbastian@rumtueddeln.de> -S: Odd Fixes +S: Orphan F: target/tricore/ F: hw/tricore/ F: include/hw/tricore/ -- 2.43.0 Mahmoud Mandour has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-13-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ M: Alex Bennée <alex.bennee@linaro.org> M: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> T: git https://gitlab.com/stsquad/qemu plugins/next R: Alexandre Iooss <erdnaxe@crans.org> -R: Mahmoud Mandour <ma.mandourr@gmail.com> S: Maintained F: docs/devel/tcg-plugins.rst F: plugins/ -- 2.43.0 Magnus Damm has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-14-peter.maydell@linaro.org --- MAINTAINERS | 2 -- 1 file changed, 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ SH4 Machines ------------ R2D R: Yoshinori Sato <yoshinori.sato@nifty.com> -R: Magnus Damm <magnus.damm@gmail.com> S: Odd Fixes F: hw/char/sh_serial.c F: hw/sh4/r2d.c @@ -XXX,XX +XXX,XX @@ F: docs/*/*xive* Renesas peripherals R: Yoshinori Sato <yoshinori.sato@nifty.com> -R: Magnus Damm <magnus.damm@gmail.com> S: Odd Fixes F: hw/char/renesas_sci.c F: hw/char/sh_serial.c -- 2.43.0 Marcel Apfelbaum has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-15-peter.maydell@linaro.org --- MAINTAINERS | 3 --- 1 file changed, 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ X86 Machines ------------ PC M: Michael S. Tsirkin <mst@redhat.com> -M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> S: Supported F: include/hw/i386/ F: hw/i386/ @@ -XXX,XX +XXX,XX @@ F: include/hw/i386/nitro_enclave.h F: docs/system/i386/nitro-enclave.rst Machine core -M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> R: Philippe Mathieu-Daudé <philmd@linaro.org> R: Yanan Wang <wangyanan55@huawei.com> R: Zhao Liu <zhao1.liu@intel.com> @@ -XXX,XX +XXX,XX @@ F: hw/ipack/ PCI M: Michael S. Tsirkin <mst@redhat.com> -M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> S: Supported F: include/hw/pci/* F: hw/misc/pci-testdev.c -- 2.43.0 Aarushi Mehta has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-16-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: block/file-win32.c F: block/win32-aio.c Linux io_uring -M: Aarushi Mehta <mehta.aaru20@gmail.com> M: Julia Suvorova <jusual@redhat.com> M: Stefan Hajnoczi <stefanha@redhat.com> R: Stefano Garzarella <sgarzare@redhat.com> -- 2.43.0 Paul Burton has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-17-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: include/hw/intc/loongson_liointc.h F: tests/functional/mips64el/test_loongson3v.py Boston -M: Paul Burton <paulburton@kernel.org> R: Aleksandar Rikalo <arikalo@gmail.com> S: Odd Fixes F: hw/core/loader-fit.c -- 2.43.0 Jia Liu has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the or1k-sim OpenRISC machine orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-18-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: include/hw/pci-host/xilinx-pcie.h OpenRISC Machines ----------------- or1k-sim -M: Jia Liu <proljc@gmail.com> -S: Maintained +S: Orphan F: docs/system/or1k/or1k-sim.rst F: hw/intc/ompic.c F: hw/or1k/or1k-sim.c -- 2.43.0 Qiuhao Li has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-19-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ R: Paolo Bonzini <pbonzini@redhat.com> R: Stefan Hajnoczi <stefanha@redhat.com> R: Fabiano Rosas <farosas@suse.de> R: Darren Kenny <darren.kenny@oracle.com> -R: Qiuhao Li <Qiuhao.Li@outlook.com> S: Maintained F: tests/qtest/fuzz/ F: tests/qtest/fuzz-*test.c -- 2.43.0 Luigi Rizzo has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-20-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ T: git https://github.com/jasowang/qemu.git net F: qapi/net.json Netmap network backend -M: Luigi Rizzo <rizzo@iet.unipi.it> M: Giuseppe Lettieri <g.lettieri@iet.unipi.it> M: Vincenzo Maffione <v.maffione@gmail.com> W: http://info.iet.unipi.it/~luigi/netmap/ -- 2.43.0 Ronnie Sahlberg has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-21-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ S: Maintained F: block/blkio.c iSCSI -M: Ronnie Sahlberg <ronniesahlberg@gmail.com> M: Paolo Bonzini <pbonzini@redhat.com> M: Peter Lieven <pl@dlhnet.de> L: qemu-block@nongnu.org -- 2.43.0 Ryo ONODERA has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-22-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: include/qemu/*posix*.h NETBSD M: Reinoud Zandijk <reinoud@netbsd.org> -M: Ryo ONODERA <ryoon@netbsd.org> S: Maintained K: ^Subject:.*(?i)NetBSD -- 2.43.0 Shannon Zhao has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the "ARM ACPI Subsystem" orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-23-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: docs/specs/acpi_pci_hotplug.rst F: docs/specs/acpi_hw_reduced_hotplug.rst ARM ACPI Subsystem -M: Shannon Zhao <shannon.zhaosl@gmail.com> L: qemu-arm@nongnu.org -S: Maintained +S: Orphan F: hw/arm/virt-acpi-build.c RISC-V ACPI Subsystem -- 2.43.0 Su Hang has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the Intel Hexadecimal Object File Loader orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-24-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: docs/system/guest-loader.rst F: tests/functional/aarch64/test_xen.py Intel Hexadecimal Object File Loader -M: Su Hang <suhang16@mails.ucas.ac.cn> -S: Maintained +S: Orphan F: tests/qtest/hexloader-test.c F: tests/data/hex-loader/test.hex -- 2.43.0 Vijai Kumar K has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the Shakti C class RISC-V SoC orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-25-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: include/hw/misc/mchp_pfsoc_ioscb.h F: include/hw/misc/mchp_pfsoc_sysreg.h Shakti C class SoC -M: Vijai Kumar K <vijai@behindbytes.com> L: qemu-riscv@nongnu.org -S: Supported +S: Orphan F: docs/system/riscv/shakti-c.rst F: hw/riscv/shakti_c.c F: hw/char/shakti_uart.c -- 2.43.0 Yanan Wang has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20260416091654.316158-26-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: docs/system/i386/nitro-enclave.rst Machine core R: Philippe Mathieu-Daudé <philmd@linaro.org> -R: Yanan Wang <wangyanan55@huawei.com> R: Zhao Liu <zhao1.liu@intel.com> S: Supported F: hw/core/cpu-common.c -- 2.43.0 Wen Congyang has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Lukas Straub <lukasstraub2@web.de> Message-id: 20260416091654.316158-27-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: block/export/vduse-blk.c F: block/export/vduse-blk.h Replication -M: Wen Congyang <wencongyang2@huawei.com> M: Xie Changlong <xiechanglong.d@gmail.com> S: Supported F: replication* -- 2.43.0 Xiao Guangrong has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20260416091654.316158-28-peter.maydell@linaro.org --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: scripts/coccinelle/memory-region-housekeeping.cocci Memory devices M: David Hildenbrand <david@kernel.org> M: Igor Mammedov <imammedo@redhat.com> -R: Xiao Guangrong <xiaoguangrong.eric@gmail.com> S: Supported F: hw/mem/memory-device*.c F: hw/mem/nvdimm.c -- 2.43.0 Xie Changlong has not posted to qemu-devel in some years and did not respond to a query about whether they still wished to be listed in our MAINTAINERS file. Remove them, on the assumption that they are no longer active in QEMU. This makes the "Replication" block filter orphan. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Lukas Straub <lukasstraub2@web.de> Message-id: 20260416091654.316158-29-peter.maydell@linaro.org --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: block/export/vduse-blk.c F: block/export/vduse-blk.h Replication -M: Xie Changlong <xiechanglong.d@gmail.com> -S: Supported +S: Orphan F: replication* F: block/replication.c F: tests/unit/test-replication.c -- 2.43.0 v3->v4: Windows headers define an INT type which clashed with an enum value name in arm_gicv3_its.c... The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100) ---------------------------------------------------------------- target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running ---------------------------------------------------------------- Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Chris Rauer (1): hw/arm: Add support for kudo-bmc board. Marc Zyngier (1): hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell (5): target/arm: Take an exception if PSTATE.IL is set qdev: Support marking individual buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Richard Henderson (1): target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS docs/system/arm/nuvoton.rst | 1 + hw/intc/gicv3_internal.h | 188 ++++- include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- include/hw/qdev-core.h | 24 + target/arm/cpu.h | 1 + target/arm/kvm_arm.h | 4 +- target/arm/syndrome.h | 5 + target/arm/translate.h | 2 + hw/arm/mps2-tz.c | 92 ++- hw/arm/mps2.c | 12 +- hw/arm/npcm7xx_boards.c | 34 + hw/arm/virt.c | 29 +- hw/char/cadence_uart.c | 61 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 153 +++- hw/misc/zynq_slcr.c | 31 +- softmmu/qdev-monitor.c | 7 +- target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 + target/arm/kvm.c | 7 +- target/arm/translate-a64.c | 255 +++--- target/arm/translate.c | 21 + hw/intc/meson.build | 1 + tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 35 files changed, 2144 insertions(+), 210 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb