From nobody Sat May 30 20:12:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1776789078; cv=none; d=zohomail.com; s=zohoarc; b=G2vzdve0yXHTUKYHKbEFS3IxgZcHitt/g0clGHWHbP888TU9cwwu7E8AGbhUlMgjFQAvmFDyF0avy96OwxSBTqIirgjobRpuc9zI9/7mUjFa9heWVvL6R4wgjg92nzlPJamv/A8Pu9R8oJVLJoMMQhPJwDUtac+9BMhcGQ7zf+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776789078; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=s3dqOfFoIBWp7Cb7bNlLy2OEHohEiraa8UK2jGzmOpM=; b=EpDZmfZbcxzur6dMVN9LI/I+BEewItc5pIA0OUfvrmEwMqH/XGSzIoUOMKUd+h4Aqt56pGjs/dJhLnEYLyrh7xWZZQdgSz9Asd041ZGC6l/UHbYom0MlhLhx+wO7AqFtdUzm8ZfhUdVdvgbvteDkeQWJ3IrMxS4PxdUJk0rkYrQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776789078075642.1411986869831; Tue, 21 Apr 2026 09:31:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wFDyi-0008UK-69; Tue, 21 Apr 2026 12:29:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wFDyg-0008T1-Bf for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:29:34 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wFDyd-0005gu-50 for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:29:34 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-35fb16e56efso2929426a91.2 for ; Tue, 21 Apr 2026 09:29:30 -0700 (PDT) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36140ff2e1esm13529470a91.8.2026.04.21.09.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 09:29:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1776788969; x=1777393769; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s3dqOfFoIBWp7Cb7bNlLy2OEHohEiraa8UK2jGzmOpM=; b=idLIqPguOfAkAy5vRhlVPwUiRUT88pCX9nZNPp+M1dsYbpaydw+8gVbS4/X/UmWuAf 7Ibzn8kioceX3C+cM0bL+iAa83tlLY+fU0QPJwQrmDFMma+6j60scAjVz5JbHEgdATW+ g25RUMkpeR+dIuo5QvTXloC0O4NjYB3LKArwrXmCFHej2Jak3PJKUWL8v793BaBRFRvi dYP7wcT1WsRoiABRPMTtZZCV2CJVAW7BplQMHm0fJ3Z3mltQ8f/s4T5Dtz2f6cRC2iis ARY/26jRyBknvAmhTwiFgddggSmL1rbC49qaITHpZ0rwPun5C81YLrNDf/ZlWTEKh5ay 4PjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776788969; x=1777393769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=s3dqOfFoIBWp7Cb7bNlLy2OEHohEiraa8UK2jGzmOpM=; b=XapnrgY1I4S9KDFn/poSUXStSzCydEKt/qJ6tpY6hxk8eNHaJ1bkzNWC9WHBTldhtC cCBv5X5mmU+XYlRjcO+arzfGTIrvJ2H+5fvGBC+LVprqo96uthd/ChH+DipBke/mNp35 5Q7e3wIIxiau326tE0fiUdXnPv5lMYweMg22Bx0N0YWLQsov/GYJ1y65Hjelk0U2xpye JozKaCo3eeMsJ8MnFuBFK23/TaeQgW7RbCt5RepaBLYJKEOR2U0lrG5nuQf7TS1ZJMdj CRtVNcbyyfMme674bu75MVLtGoxxjDN111+FvZoP6q0583qh22Vc6goE4ba2LqhWnjnv LIxQ== X-Gm-Message-State: AOJu0YzcUCdarjV9MLtN0uP2RXW9Md4C8P/cpLk0nIR4m17FnX9ToixM MyMhxbYKGdrrB/8JKUEOrhc93ZXyIZI4045C/QuPdO+tyIhUnAhU8GI5B/zGm960599po63nM7a KyAzXlqPRXWmNpGu2eoOC+aTrwdrAwaSNH80qH/ZP0pdFlBYuAiEVXDI8JkLAwRviArghhB+Kax ofneu3neomWr6QWMeFtqjEaVYt+nAbkQXswXcqq96G X-Gm-Gg: AeBDieuYchfCT6norJUzcbPdX8WtOHcHt64b+w7xW36iyoj7wVCnz4+YkIoOaOOcJQc RjZtkKxi9GYcM9Fc4HlURSc9fGfNBegYbipPChpV1PwDmwOMGsTIFZvuoJcvtlt5hiI0Ffc3isI /NDqljysSRLXNWlhNQIxe06TikYUvyADXT6cM4WinnKLf8qNYUZwyEfRtpfg6cftnxIk0wzO/hX hWMQ7UDgPqjGWuln7gfaG/8M6i+iqfBXY9hMakGrBJa5GqICRzdxgcLDKfPnmEWl5HpGQ/G3Qum bSFSYnNiiihXRwMNifLyg4C9Q6Qsd5/GoNG3g4C+PCz5MqZrqLUjFJGwVDzTHwYGaCcdIVt8Uff YKOvEfFIuKwZNzI3j9pe40vD5tWU6espkqYWWr43ZWGsRy3xB53j03GWPtiPciv4jQ4NN4W0JBF EqvY7yRzav29WIratITPaq8gm5I/A6/093JyLIKwGwDmelVE044fvG7us= X-Received: by 2002:a17:90b:3d01:b0:35f:b75e:fff5 with SMTP id 98e67ed59e1d1-3614048b7admr20996157a91.22.1776788969271; Tue, 21 Apr 2026 09:29:29 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v2 1/5] accel/tcg: Pass access_type as an argument of tlb_set_page*() Date: Wed, 22 Apr 2026 00:29:08 +0800 Message-ID: <20260421162912.3295598-2-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260421162912.3295598-1-jim.shu@sifive.com> References: <20260421162912.3295598-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=jim.shu@sifive.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1776789080947158500 Content-Type: text/plain; charset="utf-8" Pass the access_type so that we could know CPU will do the read or write access. Then, CPU can fill the CPUTLBEntry[Full] of the specific permission (@prot). It is fine for address_space_translate*() to return different section of read and write access. tlb_set_page*() only sets 'CPUTLBEntry.addr_*' for specific @prot, so access from another @prot will only get TLB miss and start to overwrite 'CPUTLBEntry[Full]' with new @prot. It is the preliminary patch of next commit to pass the iommu_flags to IOMMUMemoryRegion from access_type. Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 14 ++++++++------ include/exec/cputlb.h | 11 +++++++---- target/alpha/helper.c | 2 +- target/avr/helper.c | 3 ++- target/hppa/mem_helper.c | 1 - target/i386/tcg/system/excp_helper.c | 3 ++- target/loongarch/tcg/tlb_helper.c | 2 +- target/m68k/helper.c | 10 +++++++--- target/microblaze/helper.c | 8 ++++---- target/mips/tcg/system/tlb_helper.c | 4 ++-- target/or1k/mmu.c | 2 +- target/ppc/mmu_helper.c | 2 +- target/riscv/cpu_helper.c | 2 +- target/rx/cpu.c | 3 ++- target/s390x/tcg/excp_helper.c | 2 +- target/sh4/helper.c | 3 ++- target/sparc/mmu_helper.c | 6 +++--- target/tricore/helper.c | 2 +- target/xtensa/helper.c | 3 ++- 19 files changed, 48 insertions(+), 35 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d6115bbb0a4..3bc951603dc 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1022,7 +1022,8 @@ static inline void tlb_set_compare(CPUTLBEntryFull *f= ull, CPUTLBEntry *ent, * critical section. */ void tlb_set_page_full(CPUState *cpu, int mmu_idx, - vaddr addr, CPUTLBEntryFull *full) + vaddr addr, MMUAccessType access_type, + CPUTLBEntryFull *full) { CPUTLB *tlb =3D &cpu->neg.tlb; CPUTLBDesc *desc =3D &tlb->d[mmu_idx]; @@ -1185,7 +1186,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, =20 void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, vaddr size) + MMUAccessType access_type, int mmu_idx, + vaddr size) { CPUTLBEntryFull full =3D { .phys_addr =3D paddr, @@ -1195,15 +1197,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr a= ddr, }; =20 assert(is_power_of_2(size)); - tlb_set_page_full(cpu, mmu_idx, addr, &full); + tlb_set_page_full(cpu, mmu_idx, addr, access_type, &full); } =20 void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, + hwaddr paddr, int prot, MMUAccessType access_type, int mmu_idx, vaddr size) { tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED, - prot, mmu_idx, size); + prot, access_type, mmu_idx, size); } =20 /** @@ -1245,7 +1247,7 @@ static bool tlb_fill_align(CPUState *cpu, vaddr addr,= MMUAccessType type, if (ops->tlb_fill_align) { if (ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, memop, size, probe, ra)) { - tlb_set_page_full(cpu, mmu_idx, addr, &full); + tlb_set_page_full(cpu, mmu_idx, addr, type, &full); return true; } } else { diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3a9603a6965..47fa4302a9a 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -41,6 +41,7 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr= _t length); * @cpu: CPU context * @mmu_idx: mmu index of the tlb to modify * @addr: virtual address of the entry to add + * @access_type: access was read/write/execute * @full: the details of the tlb entry * * Add an entry to @cpu tlb index @mmu_idx. All of the fields of @@ -56,6 +57,7 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr= _t length); * used by tlb_flush_page. */ void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, + MMUAccessType access_type, CPUTLBEntryFull *full); =20 /** @@ -65,6 +67,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr = addr, * @paddr: physical address of the page * @attrs: memory transaction attributes * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @access_type: access was read/write/execute * @mmu_idx: MMU index to insert TLB entry for * @size: size of the page in bytes * @@ -81,9 +84,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr = addr, * used by tlb_flush_page. */ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); - + hwaddr paddr, MemTxAttrs attrs, int prot, + MMUAccessType access_type, int mmu_idx, + vaddr size); /** * tlb_set_page: * @@ -92,7 +95,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, * as a convenience for CPUs which don't use memory transaction attributes. */ void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, + hwaddr paddr, int prot, MMUAccessType access_type, int mmu_idx, vaddr size); =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 179dc2dc7ae..7645ff27e20 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -328,7 +328,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int s= ize, } =20 tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); + prot, access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } =20 diff --git a/target/avr/helper.c b/target/avr/helper.c index 365c8c60e19..4f536f08676 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -143,7 +143,8 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, prot =3D PAGE_READ | PAGE_WRITE; } =20 - tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, paddr, prot, access_type, mmu_idx, + TARGET_PAGE_SIZE); return true; } =20 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index ffbad8acfd2..63606c19d07 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -482,7 +482,6 @@ bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryF= ull *out, vaddr addr, out->prot =3D prot; out->attrs =3D MEMTXATTRS_UNSPECIFIED; out->lg_page_size =3D TARGET_PAGE_BITS; - return true; } =20 diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index d7ea77c8558..0fdae83f0a2 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -628,7 +628,8 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int siz= e, tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK, out.paddr & TARGET_PAGE_MASK, cpu_get_mem_attrs(env), - out.prot, mmu_idx, out.page_size); + out.prot, access_type, mmu_idx, + out.page_size); return true; } =20 diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index c0fd8527fe9..f84a62e2861 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -669,7 +669,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address= , int size, prot =3D context.prot; tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); qemu_log_mask(CPU_LOG_MMU, "%s address=3D%" VADDR_PRIx " physical " HWADDR_FMT_= plx " prot %d\n", __func__, address, physical, prot); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bab1843892..0de0a7dd248 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -969,7 +969,7 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, tlb_set_page(cs, address & TARGET_PAGE_MASK, address & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); + qemu_access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } =20 @@ -989,7 +989,8 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, address, access_type, &page_size); if (likely(ret =3D=3D 0)) { tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, mmu_idx, page_size= ); + physical & TARGET_PAGE_MASK, prot, qemu_access_type, + mmu_idx, page_size); return true; } =20 @@ -1461,6 +1462,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, = uint32_t is_read) int prot; int ret; target_ulong page_size; + MMUAccessType qemu_access_type; =20 access_type =3D ACCESS_PTEST; if (env->dfc & 4) { @@ -1468,9 +1470,11 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr,= uint32_t is_read) } if ((env->dfc & 3) =3D=3D 2) { access_type |=3D ACCESS_CODE; + qemu_access_type =3D MMU_INST_FETCH; } if (!is_read) { access_type |=3D ACCESS_STORE; + qemu_access_type =3D MMU_DATA_STORE; } =20 env->mmu.mmusr =3D 0; @@ -1480,7 +1484,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, = uint32_t is_read) if (ret =3D=3D 0) { tlb_set_page(env_cpu(env), addr & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, - prot, access_type & ACCESS_SUPER ? + prot, qemu_access_type, access_type & ACCESS_SUPER ? MMU_KERNEL_IDX : MMU_USER_IDX, page_size); } } diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a1857b72172..2bdf8c3ea03 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -101,8 +101,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, /* MMU disabled or not available. */ address &=3D TARGET_PAGE_MASK; prot =3D PAGE_RWX; - tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, - TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, address, address, attrs, prot, access_= type, + mmu_idx, TARGET_PAGE_SIZE); return true; } =20 @@ -113,8 +113,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, =20 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x prot=3D= %x\n", mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, - TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, access_t= ype, + mmu_idx, TARGET_PAGE_SIZE); return true; } =20 diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/t= lb_helper.c index 566924b079e..bf08ba29d02 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -934,7 +934,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } #if !defined(TARGET_MIPS64) @@ -952,7 +952,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } } diff --git a/target/or1k/mmu.c b/target/or1k/mmu.c index 315debaf3e5..c14f03081e1 100644 --- a/target/or1k/mmu.c +++ b/target/or1k/mmu.c @@ -127,7 +127,7 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, in= t size, if (likely(excp =3D=3D 0)) { tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys_addr & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } if (probe) { diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ac607054027..8b55a9e4ddf 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1369,7 +1369,7 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int = size, if (ppc_xlate(cpu, eaddr, access_type, &raddr, &page_size, &prot, mmu_idx, !probe)) { tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - prot, mmu_idx, 1UL << page_size); + prot, access_type, mmu_idx, 1UL << page_size); return true; } if (probe) { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index dd6c861a90e..ee0292e3423 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1874,7 +1874,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 if (ret =3D=3D TRANSLATE_SUCCESS) { tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), - prot, mmu_idx, tlb_size); + prot, access_type, mmu_idx, tlb_size); return true; } else if (probe) { return false; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index b5284199e6d..6114e345e65 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -194,7 +194,8 @@ static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, i= nt size, /* Linear mapping */ address =3D physical =3D addr & TARGET_PAGE_MASK; prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page(cs, address, physical, prot, access_type, + mmu_idx, TARGET_PAGE_SIZE); return true; } =20 diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 41b0017d767..6d89a8c328e 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -182,7 +182,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, (uint64_t)vaddr, (uint64_t)raddr, prot); tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot, - mmu_idx, TARGET_PAGE_SIZE); + access_type, mmu_idx, TARGET_PAGE_SIZE); return true; } if (probe) { diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5d6295618f5..2542d3d88f5 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -812,7 +812,8 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (ret =3D=3D MMU_OK) { address &=3D TARGET_PAGE_MASK; physical &=3D TARGET_PAGE_MASK; - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZ= E); + tlb_set_page(cs, address, physical, prot, access_type, mmu_idx, + TARGET_PAGE_SIZE); return true; } if (probe) { diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a6f76a1ab76..316f4182848 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -236,7 +236,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, "Translate at %" VADDR_PRIx " -> " HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n", address, full.phys_addr, vaddr); - tlb_set_page_full(cs, mmu_idx, vaddr, &full); + tlb_set_page_full(cs, mmu_idx, vaddr, access_type, &full); return true; } =20 @@ -252,7 +252,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ full.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page_full(cs, mmu_idx, vaddr, &full); + tlb_set_page_full(cs, mmu_idx, vaddr, access_type, &full); return true; } else { if (access_type =3D=3D MMU_INST_FETCH) { @@ -777,7 +777,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->= tl, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page_full(cs, mmu_idx, address, &full); + tlb_set_page_full(cs, mmu_idx, address, access_type, &full); return true; } if (probe) { diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7ee8c7fd699..a7173dc73f0 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -86,7 +86,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (ret =3D=3D TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); + rw, mmu_idx, TARGET_PAGE_SIZE); return true; } else { assert(ret < 0); diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 2d93b45036d..2cd51ba0cb7 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -282,7 +282,8 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, tlb_set_page(cs, address & TARGET_PAGE_MASK, paddr & TARGET_PAGE_MASK, - access, mmu_idx, page_size); + access, access_type, mmu_idx, + page_size); return true; } else if (probe) { return false; --=20 2.43.0 From nobody Sat May 30 20:12:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1776789076; cv=none; d=zohomail.com; s=zohoarc; b=RVKLL/aJ600fNzUZHN3gpyTnxvDt8UrK0EZpVxyDvoD7K2c6l7LbpZa7N+N7CPzNrEnSdeenQZwv1UzKw70dtaDDoNS84iJ7TqJx3+LNBMnMQP07dir0eHMSkRQJdErVar29ImnaywDA3O7dWa67C1RSzvF06KcmG6IddDzlPPc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776789076; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hp611hD/fc7KenUYYrcLNqv5irQqbGpyxYBnGHFQNeU=; b=IwwckSJgPtSv/d11ozWZHKpeXn7o5jVLKgxGOTkXt6zxAtUx+XDAweJoUXFzdtGJe2Lva7MnLpiYLCw5DPzqiSiYngW/8XJaa3y6RCRq5xWfPwgBphuxDmkXKyc4nhnvoOh/3ib5ThWairpAF5cBg0uds6460gfh114Rknr7b8w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776789076909616.3328832677347; Tue, 21 Apr 2026 09:31:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wFDzC-0000Fo-M8; Tue, 21 Apr 2026 12:30:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wFDyv-0008Vm-UN for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:29:55 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wFDyk-0005ig-Pi for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:29:43 -0400 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-35fc258aaa4so2857781a91.2 for ; Tue, 21 Apr 2026 09:29:37 -0700 (PDT) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36140ff2e1esm13529470a91.8.2026.04.21.09.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 09:29:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1776788976; x=1777393776; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hp611hD/fc7KenUYYrcLNqv5irQqbGpyxYBnGHFQNeU=; b=IbfLGVPnELUUEgrvbuxaicS0JS1dE/lOi0wY9IWU8/laiI/qHkQ5MzEcEd1fJfc27J NzMp4kj8mpdNTNGcZZiplgWxxXJxmWO22jJ+wxfUXwI+a4H4CSFnMWqDfl1EbPZEzyaI Tq7UiIHI6OVRHmzlXZ5I2vlh9OAkAtvBWVOxFVXDKgWjC8WHAjfa6qHAYBvJpHsK2HL6 iHSsPqlyUBzSsAy/3NujVJDq/Iv3TcluqQlpg9mzSE9TctK6wUs3bODWkJFxaIGRo1zx mvjXoRFY6RthIFei3D7mX08+YPvYKexWJsM5LTvegw13fnpcunY9AjBmYMPdzW+/MK4o eRrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776788976; x=1777393776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=hp611hD/fc7KenUYYrcLNqv5irQqbGpyxYBnGHFQNeU=; b=INGJCKYZ2X+5ntF+P4YOJ1oMDdqM8KVz2tXd1ALcIAKLecawWT3fU6thL0fy7aKVWR SkHtjOc812/Ey+/qaGdvmVp54BvKmB+hCfOvFwHs0A5sKvcRIXGkN5xD5hMYvbxKcuOl PhrOEH8qLbPG9Wi6GEju1BMbmrKW8f/nNB2XhSvlvhsPLa8MRJbQZGKa6XAbz91rSjSZ tNzA70QpVXlE+Lp5isTVehQwXSXCuBz0ErXK7J1O3wAJgdOsq9sxUMWif+ue1rtGhMzd awuFKX/DeHlZAuheFjpf5cGJ0heW6631wLxBEeyP0HgFfqJ4zK+zJInrc+Xj3mlXLJnq ofPg== X-Gm-Message-State: AOJu0YyLXrFMQG3KCU3OfGq+gpLHAfM8KS0Tch4Ppbi0ZH5ZkTH3Vy6s JlOC2ZpMrtW0OnwG4WBOpLQKcYwv+Uzu36A2UMAtUxsSqz0AUP0HlWh7duxZsAbyXMx37DrEss8 AUcTQwGa9LazpYlxJRU6Szsj8+U79EBQ3mH2YMVqJGzYi+fZHYX5rrseOrz/biPEO8SN6p1gGsy l6ABXGmLYJYLU7tvvfhB7titpMpE40f2P1IxAw8Dqw X-Gm-Gg: AeBDieu9JMlPyBMXAnfMoNdwOaZvaloUA+8bftRwjRL/0C6RVJEx9Y4oGN5e3QY3BLT AP/kK7mkT0YUN+fvdg76MtE2Dh9xlsWNenK79sSRFKPtO5ZLedzc1yrYrfFeJienu6nxafbMvq5 ITZ8W112XoMPfrIHA0oqXUkL9k/bhcQBxa6PHHWjciBizZi2VKjfSOLeqNmnEDnKDfr6OPCrsV/ e1O8YOzlnWUQlFkIHZSCwUGi55x601emgxTPxJqpF9xqe8ElBf+TxQi4rtUYIfjdzO5OuyElrdu ks+TQWmustGcaUYGQTd49DdPgmmT2zmJv5qRLKRz2PnojIfx2ZNJcd7Q5tySPxGJcbu/Gwnzt6q 8TFO1S5ASUz+X/B4wKlHs690homHNRZwaz0qVzhTkO4c8SA9O11EcNXBN7iIPzTW5flzLiP2V+9 d4V0+J92TnzSS98DqZ8s/YozsTC/ondtCAbCF0BM2qzPxMxZ7bdPIoSbI= X-Received: by 2002:a17:90b:55cc:b0:35e:30bc:804d with SMTP id 98e67ed59e1d1-3614048adcdmr18348774a91.15.1776788975797; Tue, 21 Apr 2026 09:29:35 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v2 2/5] accel/tcg: address_space_translate*() will pass the correct iommu_flags Date: Wed, 22 Apr 2026 00:29:09 +0800 Message-ID: <20260421162912.3295598-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260421162912.3295598-1-jim.shu@sifive.com> References: <20260421162912.3295598-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=jim.shu@sifive.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1776789078720154100 Content-Type: text/plain; charset="utf-8" Instead of IOMMU_NONE, address_space_translate_for_iotlb() now can pass the correct iommu_flags to the IOMMU translate function from the access_type. Since RISC-V wgChecker [1] could permit access in RO or WO permission only, the IOMMUMemoryRegion could return different section for read and write access. To support this kind of IOMMUMemoryRegion in the path of CPU access, we should pass correct iommu_flags here. [1] RISC-V WG: https://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/ Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 3 ++- include/accel/tcg/iommu.h | 12 +++++------- system/physmem.c | 16 +++++++++++----- 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3bc951603dc..4ca4152579b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1050,7 +1050,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, full->attrs, &= prot); + &xlat, &sz, full->attrs, &= prot, + access_type); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx diff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h index 547f8ea0ef0..30655aab4ba 100644 --- a/include/accel/tcg/iommu.h +++ b/include/accel/tcg/iommu.h @@ -14,13 +14,11 @@ #include "exec/hwaddr.h" #include "exec/memattrs.h" =20 -MemoryRegionSection *address_space_translate_for_iotlb(CPUState *cpu, - int asidx, - hwaddr addr, - hwaddr *xlat, - hwaddr *plen, - MemTxAttrs attrs, - int *prot); +MemoryRegionSection * +address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot, + MMUAccessType access_type); =20 #endif =20 diff --git a/system/physmem.c b/system/physmem.c index 4e26f1a1d42..d3d111392c1 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -685,12 +685,14 @@ void tcg_iommu_init_notifier_list(CPUState *cpu) MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_ad= dr, hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, int *prot) + MemTxAttrs attrs, int *prot, + MMUAccessType access_type) { MemoryRegionSection *section; IOMMUMemoryRegion *iommu_mr; IOMMUMemoryRegionClass *imrc; IOMMUTLBEntry iotlb; + IOMMUAccessFlags iommu_flags; int iommu_idx; hwaddr addr =3D orig_addr; AddressSpaceDispatch *d =3D address_space_to_dispatch(cpu->cpu_ases[as= idx].as); @@ -707,10 +709,14 @@ address_space_translate_for_iotlb(CPUState *cpu, int = asidx, hwaddr orig_addr, =20 iommu_idx =3D imrc->attrs_to_index(iommu_mr, attrs); tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); - /* We need all the permissions, so pass IOMMU_NONE so the IOMMU - * doesn't short-cut its translation table walk. - */ - iotlb =3D imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); + + if (access_type =3D=3D MMU_DATA_STORE) { + iommu_flags =3D IOMMU_WO; + } else { + iommu_flags =3D IOMMU_RO; + } + + iotlb =3D imrc->translate(iommu_mr, addr, iommu_flags, iommu_idx); addr =3D ((iotlb.translated_addr & ~iotlb.addr_mask) | (addr & iotlb.addr_mask)); /* Update the caller's prot bits to remove permissions the IOMMU --=20 2.43.0 From nobody Sat May 30 20:12:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1776789119; cv=none; d=zohomail.com; s=zohoarc; b=YXfGRdLBHKhumvUnsgFYMn8L9PoTkDPmSBK4iPdkXYtL8x1VglH1YHIYe0IOg7P/8/SgguU6iflp6IS/fXLd5oD5x3qoD3m+0wxUrQrYM+5CfC3F8xO6gCHodT2ttbPPKifMefbghTVcrunAwd7OA1jgHEblCKRfPDu9uSXe4Z4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776789119; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=++ZGjXwMqfSingAg7xdviV4c5zJjqE5XGviD8tj3+/Q=; b=iwo3K2fAuhB6ByTcUUDuXZcqt/H7BXmi3zQieUPYdV44Ir6sR3JdaBhfGg0YGsgoesRd9E3Feod3P85wbpCKAvbhpBV86w1xUzasi7r10JM10vHlOUzeywKL8gWIw9lr6OEN3CaBzqYov1NGlBDCuVwHxfyk3c9NmETiiFz3x0w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776789119238616.0443889679244; Tue, 21 Apr 2026 09:31:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wFDzE-0000Mq-6i; Tue, 21 Apr 2026 12:30:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wFDz4-00005P-3i for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:30:01 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wFDyw-0005jR-50 for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:29:55 -0400 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-35da2d35eccso3204140a91.0 for ; Tue, 21 Apr 2026 09:29:43 -0700 (PDT) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36140ff2e1esm13529470a91.8.2026.04.21.09.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 09:29:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1776788982; x=1777393782; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=++ZGjXwMqfSingAg7xdviV4c5zJjqE5XGviD8tj3+/Q=; b=PkFTKG8xDuDmPDC9/CB01/h7Deu793FTb+rcmCbAj1r87Q6LjnTWjUAcOx45KA/d6P /JFxdmgec9TLPchquSLFD6jSfAg09rvpOxPUGjQgvxLQKSO8JbmNwltrr9GVfGBdyaAX 4Jvi6o/8oeapX8PGVeVoHRExSG6c+CzNqOdWgMRgX7jdAj+bH3FYWrE8fy5Vmaz5jgCR 9HMOiEBVhsnyWbB7A0kT2xlcgxkjmqQ1j7jXLA2eZmLJq4U5dPTRVeUCb8EVhI3UHP1f WP5k3yoWnM7WlPc/PCHQLaWdSl0Z1YKak23mPSPkK2KWo166oQBHl8uudSibBsW/DBQd mUNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776788982; x=1777393782; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=++ZGjXwMqfSingAg7xdviV4c5zJjqE5XGviD8tj3+/Q=; b=lhKJsfO4YhT4b2QXflGfAkOkxjgU5pBMY6o6uYCk/7ylMz0VT2nqacCdvywjNNXkxZ h7slJOh+obPs9IJNl8VcaXVT1R2WwcnGwJrU+BEddr6UUqIHwY9eFm1He7mA8eKuoiK9 rx2epKUosiZFBCojQiXeQoyYGeqBykd2p/WgGV2dX/DmIHFzMjiwCAuWs0G1lOZgkPZQ DCero46IgEtbfJgCWNr/V2ylqCx3eZrvpbAswK7+ciPMVn8/e2vjNti/IqvamEyCbY6E ULT725539WIGEYwsszoiqwL6lp89KuWqipiEVeexLf7II0ngtyjebClG/rbZM+oCAZSP eGJw== X-Gm-Message-State: AOJu0YwJyV3rctfX3k4PMnKiGqSYA1aS5lwzUoemqah52SZflgQVNt4a IWAgTTh5emW6oo8nbrTNoLyY/EPXlC9ysRZ5hg5MS14J3cywqdfi0Xv/b7cGnCbPrsrQuU51WUn 5Tmx4nJ5UkAOK1L3sXPT6Ob8zDp2y5pGyL4/fypS+tYz/zfWiL2Wq+sda2aYCnFpZpQC341wwOq KtRJafaOrSbYr0zQpXBLP/achDmPiMcz+CxUoLgFF8 X-Gm-Gg: AeBDieuaTNQ55stklJvaHRMdfM538xjJZnscTVhvjP1cMzva9IV4zKZgOuhjIADrmHA 0zmU4q6QqM4COh4QuR9f9zxYuRBbWfcbImGXeRCp/xT4ZV+qt1uODIsvRydFlWIw93+HB/rt2R/ vymeNCGyTG8lPSpvJB4xc1ySOv8Jrr0BJVAc5d8KnwBRGWNHyFMZhSqXn0/Rizj3glZ1W37NcwV LF1d0LvBdtsO+TrSgxxY2SINaC4XwFtZeLnS41g3jHpJQ4UUa8ETrClqTJ/2lNlR2/hql1NGPAy JPWPpTyPAIjK6lqzoHG3nJAX+J5MtxK9qJ4fXNN+7sKOnNqhSYs1Tmdhin6LgffsHCBcRMqrsYQ aq5Z3Ofv0loGxNZQnmtdYii5Kt2/JgCIyxR+bzFZzM0Nzb94oKs2mCSzLDuoLB1Mst54oQCN3o9 gSD3r7c2NbPky6Cl/E8ujnD2TPev9NtFv6IKXy9SRSh4Wrqm7vMTPpToQ= X-Received: by 2002:a17:90b:3f8f:b0:35c:30a8:341 with SMTP id 98e67ed59e1d1-3614046cd3amr19271795a91.13.1776788982053; Tue, 21 Apr 2026 09:29:42 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v2 3/5] accel/tcg: Provide early AS translate function Date: Wed, 22 Apr 2026 00:29:10 +0800 Message-ID: <20260421162912.3295598-4-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260421162912.3295598-1-jim.shu@sifive.com> References: <20260421162912.3295598-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=jim.shu@sifive.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1776789120863158500 Content-Type: text/plain; charset="utf-8" New early AS translate function will skip IOMMU translation. It will return IOMMU region if finding it. Original function is renamed to the late translate function. It is preparation commit of IOMMU lazy translation. Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 6 ++--- include/accel/tcg/iommu.h | 13 +++++++---- system/physmem.c | 46 ++++++++++++++++++++++++++++++++++++--- 3 files changed, 55 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4ca4152579b..f0c049e1551 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1049,9 +1049,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, =20 prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); - section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, full->attrs, &= prot, - access_type); + section =3D address_space_translate_for_iotlb_late(cpu, asidx, paddr_p= age, + &xlat, &sz, full->att= rs, + &prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx diff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h index 30655aab4ba..11e3d63d798 100644 --- a/include/accel/tcg/iommu.h +++ b/include/accel/tcg/iommu.h @@ -15,10 +15,15 @@ #include "exec/memattrs.h" =20 MemoryRegionSection * -address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, - hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, int *prot, - MMUAccessType access_type); +address_space_translate_for_iotlb_early(CPUState *cpu, int asidx, hwaddr a= ddr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot); + +MemoryRegionSection * +address_space_translate_for_iotlb_late(CPUState *cpu, int asidx, hwaddr ad= dr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot, + MMUAccessType access_type); =20 #endif =20 diff --git a/system/physmem.c b/system/physmem.c index d3d111392c1..72c564b94a5 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -682,11 +682,11 @@ void tcg_iommu_init_notifier_list(CPUState *cpu) } =20 /* Called from RCU critical section */ -MemoryRegionSection * +static MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_ad= dr, hwaddr *xlat, hwaddr *plen, MemTxAttrs attrs, int *prot, - MMUAccessType access_type) + MMUAccessType access_type, bool early_tr= ans) { MemoryRegionSection *section; IOMMUMemoryRegion *iommu_mr; @@ -710,6 +710,11 @@ address_space_translate_for_iotlb(CPUState *cpu, int a= sidx, hwaddr orig_addr, iommu_idx =3D imrc->attrs_to_index(iommu_mr, attrs); tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); =20 + /* Defer the iommu translation */ + if (early_trans) { + break; + } + if (access_type =3D=3D MMU_DATA_STORE) { iommu_flags =3D IOMMU_WO; } else { @@ -737,7 +742,8 @@ address_space_translate_for_iotlb(CPUState *cpu, int as= idx, hwaddr orig_addr, d =3D flatview_to_dispatch(address_space_to_flatview(iotlb.target_= as)); } =20 - assert(!memory_region_is_iommu(section->mr)); + /* For late translation, IOMMU region translation should be finished */ + assert(early_trans || !memory_region_is_iommu(section->mr)); *xlat =3D addr; return section; =20 @@ -755,6 +761,40 @@ translate_fail: return &d->map.sections[PHYS_SECTION_UNASSIGNED]; } =20 +/* + * address_space_translate_for_iotlb_early: translate address without + * performing IOMMU translation. This is used for CPU TLB setup. + * + * Called from RCU critical section. + */ +MemoryRegionSection * +address_space_translate_for_iotlb_early(CPUState *cpu, int asidx, + hwaddr orig_addr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot) +{ + /* access_type doesn't matter for early translation */ + return address_space_translate_for_iotlb(cpu, asidx, orig_addr, xlat, = plen, + attrs, prot, MMU_DATA_LOAD, t= rue); +} + +/* + * address_space_translate_for_iotlb_late: translate address with + * performing IOMMU translation. This is used for lazy IOMMU translation. + * + * Called from RCU critical section. + */ +MemoryRegionSection * +address_space_translate_for_iotlb_late(CPUState *cpu, int asidx, + hwaddr orig_addr, + hwaddr *xlat, hwaddr *plen, + MemTxAttrs attrs, int *prot, + MMUAccessType access_type) +{ + return address_space_translate_for_iotlb(cpu, asidx, orig_addr, xlat, = plen, + attrs, prot, access_type, fal= se); +} + #endif /* CONFIG_TCG */ =20 void cpu_address_space_init(CPUState *cpu, int asidx, --=20 2.43.0 From nobody Sat May 30 20:12:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1776789123; cv=none; d=zohomail.com; s=zohoarc; b=kcombIhu4vDtCbV64XOrDqVr53GVIvlsnICMsyiuXqmrFWXhRX6N2lhFaS1MG/iA/3Wjg0OXRWNQCO7UTA2K/LO+k0EkPLtXasOI6JlzeZo3tYvGWHXtZYpWqxjhi15v1ZGU+Kgg4jNRTRa8iT7I6vMtpCFlu+tOF7ljQP9uesg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776789123; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=APky2fuLBKI2WECyMzceROTH37228n1Vh/hCfj/U6G4=; b=HSSKEem6WQyBLSkMYl86VmZvKae0b9LhHTbSf9aqmFQCfS5FA34ue3u4vanzt95JtWqNusgul1vcEkgJSdRY9bazgR/lQrHG6+/lwjbxBH8ZVY/mEdBkVO6iQoakkNZm5qlAx+F4qxhsCLzd4sAOh7P+9ODE8kseAqqRfHMzaf4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776789123044889.8603067494803; Tue, 21 Apr 2026 09:32:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wFDzE-0000NM-Jn; Tue, 21 Apr 2026 12:30:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wFDz4-00005S-4B for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:30:02 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wFDyz-0005kC-Nh for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:29:56 -0400 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-35fb7c1a455so1795896a91.3 for ; Tue, 21 Apr 2026 09:29:50 -0700 (PDT) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36140ff2e1esm13529470a91.8.2026.04.21.09.29.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 09:29:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1776788989; x=1777393789; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=APky2fuLBKI2WECyMzceROTH37228n1Vh/hCfj/U6G4=; b=C+LELdZC8QEdqIZKXRfz1JIFDFuG0IqsPl9lyu6cF84qkQeEnpanuLWFZF9gnAj9+G quRFGfCKrQg7FM3Nua1hR2A3659WbH+mYtOkhrScuKPVmjyM5u9+wAiqVb+96BQfBieN dOedK5UnDUpa3kJ+OXR5IVGLeCCYKrV+cv8AB36clNohIfG/YO/RCIpBC0AoXWjUsDxx qIQRqaYeBWRH1Xm4Ia5IAxJfw7D0r9U+vSXvCqfMjVtAGeRVILR+HQLN6E8Kez35FFMx EQ8capYjVi+j1NETDMcHZ5KLFzp4zEqab0iIM3uv1jYC6Y9SPekuZowXlYPBkiBVhTBV Bt6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776788989; x=1777393789; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=APky2fuLBKI2WECyMzceROTH37228n1Vh/hCfj/U6G4=; b=hyHCQnTgrbOTh/p+CEbAL0lW5RJ19YTQZ+V/UThQiG2+WyFF1ZNcGFLkAgkpQGnw5b ixKiYGcdXDRfZP0hZfCSGBBJPLNzaFxxzzaVpHJ0TnZ5gqdEMwWSWKh1iOKYj67asEfE zDpJyHDGLkZC+f0A9uLj4qbtQGGIZ/kXzp7qWoLBVCCraEertaBmUX+RkLhYJm7orHmX vAvnC+/iQ9m8IJyUOYx+AxFYJkBaVI+jxtUobUiIcxxc09Id7FH6puNsFUFDWg/S1oT9 leo/lj4g4pztmrYXkmumZSn2wSBlvKQBdxw2ekhTOd7P4gdlw2o0+ZSerLNmJ7P3qIsw Yw2g== X-Gm-Message-State: AOJu0YzLKGO1Mvk4Unm8VOMKF1jdQXohVofaPEH9pUF7HstQD2BxuQ2r 0HO1Uq0WczwG48gouESId3M6nZf7gThORxSe8iVsmN2QNASDb3pqE2jLpwNj4pnrAD7tkjroxnk RLgbmRplLvgQw/WtYCVlI76Kech1C2NaywuY+MD32m75Yk71VMuwn1wVWv8zsUpdySK6I5y9sYr aDk8ibtyXnD969wKTuAbh2LiiKvcyvpyVqJVWc2kWR X-Gm-Gg: AeBDiesGjVGQxYfkUQ7s5lOxTu56qZ0T932fkU+KypIqDCZ0Rn+AeTuoa5umVME0wyA BO81otsccqGO+ZQ3tD1YF80d10aipfNXXDluxBmnjaLx+qV2VbSuQkSwf6MsEhXjCgGTfqh18pP 89R4Nh6hLQk4NUDPt90a1K2qXwwFOZvPzaAVH5uMpRjyduK3TYGmyDepObaYrjDG/7WxdYHxRD6 zAQk89ctnqYOSiyu85KLEXrYZpXv5oiw6QiN6OMzMEvNJZdIG0h9Uwn00jN4Az0nX3dYiqUBeXe /zOpJiQecz4JEbfkFq9kQE6220+20IjQ5J8rxsOm3EoQN58A1Mdz4HuePqUHIOs/HOA5yl84vDR LHoP49cAX0VIkW5QAMXmzbeM5qeSno4dufBCT0OCoNCdDcfNjf1GIcQBM1U0U3GB1LD4CUmROc/ ea7VXkoTmQgwjUQwfVV9qJ46v6jJaj5lSyip+EYyDQnF+ld9T+bDSCJlZbpLwh09DhZg== X-Received: by 2002:a17:90b:2891:b0:359:fd9a:c50c with SMTP id 98e67ed59e1d1-361404ae963mr17422285a91.22.1776788988528; Tue, 21 Apr 2026 09:29:48 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v2 4/5] accel/tcg: Add IOMMU lazy translation function Date: Wed, 22 Apr 2026 00:29:11 +0800 Message-ID: <20260421162912.3295598-5-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260421162912.3295598-1-jim.shu@sifive.com> References: <20260421162912.3295598-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=jim.shu@sifive.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1776789125291158500 Content-Type: text/plain; charset="utf-8" The lazy translation will translate IOMMU regions of the specific access_type and store the result into the CPUTLBEntryFull. For CPUTLBEntry, lazy translation may update 'addend' and 'addr_idx' array. We restrict IOMMU region to have a single non-zero 'addend' across all permissions. Also, lazy translation only updates the 'addr_idx' for the permissions specified in @prot. Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 168 ++++++++++++++++++++++++++++++++++++++++++ include/hw/core/cpu.h | 15 ++++ 2 files changed, 183 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f0c049e1551..5735f632896 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1272,6 +1272,174 @@ static inline void cpu_unaligned_access(CPUState *c= pu, vaddr addr, mmu_idx, retaddr); } =20 +/* + * Perform lazy IOMMU translation for a CPUTLBEntry/CPUTLBEntryFull. + * This is called when CPU utilize the TLB entry in the slow path. + * Updates both entry and full entry to IOMMU translated data for the + * specific access type. + */ +static void +tlb_translate_iommu(CPUState *cpu, int mmu_idx, + vaddr addr, MMUAccessType access_type, + CPUTLBEntryFull *full) +{ + CPUTLB *tlb =3D &cpu->neg.tlb; + MemoryRegionSection *section; + unsigned int read_flags, write_flags; + uintptr_t addend; + CPUTLBEntry *te; + hwaddr iotlb, xlat, sz, paddr_page; + vaddr addr_page; + int asidx, wp_flags, prot; + bool is_ram, is_romd; + + if (!full->is_iommu || (full->iommu_last_at =3D=3D access_type)) { + return; + } + + assert_cpu_is_self(cpu); + + if (full->lg_page_size <=3D TARGET_PAGE_BITS) { + sz =3D TARGET_PAGE_SIZE; + } else { + sz =3D (hwaddr)1 << full->lg_page_size; + tlb_add_large_page(cpu, mmu_idx, addr, sz); + } + addr_page =3D addr & TARGET_PAGE_MASK; + paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; + + prot =3D full->prot; + asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); + + section =3D address_space_translate_for_iotlb_late(cpu, asidx, paddr_p= age, + &xlat, &sz, full->att= rs, + &prot, access_type); + + assert(sz >=3D TARGET_PAGE_SIZE); + + tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx + " prot=3D%x idx=3D%d\n", + addr, full->phys_addr, prot, mmu_idx); + + is_ram =3D memory_region_is_ram(section->mr); + is_romd =3D memory_region_is_romd(section->mr); + + read_flags =3D full->tlb_fill_flags; + if (full->lg_page_size < TARGET_PAGE_BITS) { + /* Repeat the MMU check and TLB fill on every access. */ + read_flags |=3D TLB_INVALID_MASK; + } + + if (is_ram || is_romd) { + /* RAM and ROMD both have associated host memory. */ + addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + xla= t; + } else { + /* I/O and IOMMU does not; force the host address to NULL. */ + addend =3D 0; + } + + write_flags =3D read_flags; + + if (is_ram) { + iotlb =3D memory_region_get_ram_addr(section->mr) + xlat; + assert(!(iotlb & ~TARGET_PAGE_MASK)); + /* + * Computing is_clean is expensive; avoid all that unless + * the page is actually writable. + */ + if (prot & PAGE_WRITE) { + if (section->readonly) { + write_flags |=3D TLB_DISCARD_WRITE; + } else if (physical_memory_is_clean(iotlb)) { + write_flags |=3D TLB_NOTDIRTY; + } + } + } else { + /* I/O or ROMD */ + iotlb =3D xlat; + /* + * Writes to romd devices must go through MMIO to enable write. + * Reads to romd devices go through the ram_ptr found above, + * but of course reads to I/O must go through MMIO. + */ + write_flags |=3D TLB_MMIO; + if (!is_romd) { + read_flags =3D write_flags; + } + } + + wp_flags =3D cpu_watchpoint_address_matches(cpu, addr_page, + TARGET_PAGE_SIZE); + + /* Update the CPUTLBEntryFull for this access type. */ + full->iommu_last_at =3D access_type; + full->xlat_offset =3D iotlb - addr_page; + full->section =3D section; + full->phys_addr =3D paddr_page; + + /* Update the CPUTLBEntry: addend and addr_idx */ + tlb =3D &cpu->neg.tlb; + te =3D tlb_entry(cpu, mmu_idx, addr_page); + + qemu_spin_lock(&tlb->c.lock); + + /* + * If IOMMU region is translated to the memories (has associated + * host memory), it will update the 'addend' to access memories in the + * fast path. Otherwise, IO region do not update the 'addend' because + * it might be already used by memory region from the other permission= s. + * It is fine since IO region do not use addend. + */ + if (is_ram || is_romd) { + if (te->addend + addr_page) { + /* addend of untranslated IOMMU region is 0 - addr_page. */ + + /* + * CPUTLBEntry only has 1 addend across all permissions. + * We don't support the IOMMUMemoryRegion to be translated to + * 2 different host memories from the different permissions. + * QEMU will trigger an assertion for such case. + */ + g_assert(addend =3D=3D te->addend + addr_page); + } else { + te->addend =3D addend - addr_page; + } + } + + /* + * In the IOMMU lazy translation, we only update TLB flags for the + * permissions specified in @prot. For other permissions, we still + * keep the original TLB flags (e.g. TLB_IOMMU if not translated). + */ + if (prot & PAGE_EXEC) { + tlb_set_compare(full, te, addr_page, read_flags, + MMU_INST_FETCH, prot & PAGE_EXEC); + } + + if (wp_flags & BP_MEM_READ) { + read_flags |=3D TLB_WATCHPOINT; + } + if (prot & PAGE_READ) { + tlb_set_compare(full, te, addr_page, read_flags, + MMU_DATA_LOAD, prot & PAGE_READ); + } + + if (prot & PAGE_WRITE_INV) { + write_flags |=3D TLB_INVALID_MASK; + } + if (wp_flags & BP_MEM_WRITE) { + write_flags |=3D TLB_WATCHPOINT; + } + if (prot & PAGE_WRITE) { + tlb_set_compare(full, te, addr_page, write_flags, + MMU_DATA_STORE, prot & PAGE_WRITE); + } + + qemu_spin_unlock(&tlb->c.lock); + + return; +} + static MemoryRegionSection * io_prepare(hwaddr *out_offset, CPUState *cpu, CPUTLBEntryFull *full, vaddr addr, uintptr_t retaddr) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 04e1f970caf..465614c5d9a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -254,6 +254,21 @@ struct CPUTLBEntryFull { */ uint8_t slow_flags[MMU_ACCESS_COUNT]; =20 + /* + * @is_iommu indicates if the MemoryRegion is an IOMMU. + * When true, IOMMU translation is deferred until the entry is used. + */ + bool is_iommu; + + /* + * @iommu_last_at contains the access_type of last IOMMU translation. + * It means that this entry currently stores the translated data of + * IOMMU region with this access_type. + * When it is MMU_ACCESS_COUNT, the entry stores untranslated data of + * IOMMU region. + */ + MMUAccessType iommu_last_at; + /* * Allow target-specific additions to this structure. * This may be used to cache items from the guest cpu --=20 2.43.0 From nobody Sat May 30 20:12:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1776789077; cv=none; d=zohomail.com; s=zohoarc; b=JwwSGcflUZOCUsfjFKNXBujT7vrEYx4kX/h+w1Xw6t0BqZnJzoHT6yf/bHwdpP8B+Qz5MJu+Lw80jID6HnafydwGqQv7eL11qDzkVbif6bPzslZXMrhJQW1dKojOrgJzjB8oTbNK79NN8wbEBpTt9ihvHbpc7692Uy1eK19jM+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776789077; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=W9nxX3vo27aPKXMM9uM/grMyQNuhei9Pxu0QSoOCOso=; b=NbD0jOaeTVph+P8guCxThCAEshiUfJs+ha5nwbUOY+25ti82VaIxZhQykL4xtrQCpeDWAn9txNjyqeIZcvWx+DC7u+ZcRLnvQjsJMHhYzlHed7VnOYuCb6q4PdjVcs9Q9ijiqkrSyauC/fXkIVjPRYB0MEiNP1NnbFu2B0QjKtg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776789077487683.4436147794855; Tue, 21 Apr 2026 09:31:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wFDzG-0000S1-3A; Tue, 21 Apr 2026 12:30:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wFDzA-0000Da-BO for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:30:05 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wFDz6-0005lV-Uf for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:30:03 -0400 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-35fb0bb27e7so2900387a91.1 for ; Tue, 21 Apr 2026 09:29:57 -0700 (PDT) Received: from hsinchu26.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36140ff2e1esm13529470a91.8.2026.04.21.09.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 09:29:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1776788995; x=1777393795; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W9nxX3vo27aPKXMM9uM/grMyQNuhei9Pxu0QSoOCOso=; b=HCRV6hRE+TZv4rGgPHHAbwA+0bffRitB503IP08HgkdJIUA3/ndxg1y5D2Fa4tdoZF DTQcnp5UhO7E0MMqfPunjVJven5g+Gf1Vb8KlbF65+0B6d06/5Kudl3cC5ddBeSLtEnw rPtbfUY+t68g5pOJqs1qvoA0a0so6/Exa6GjTpDw6YZFu+kkR4/NJBJX+oRd0OfdjqMn eD89o0JoO1fjExfTIm1Ohe/evlrPc1ueWiesaXnFbf5br2Uw5xqNkE0VRat4NHXz/Rgv 8haedtXMhNta8WyI17KMpbmXRFcG5ccpHIbyjYEw75tUq2H7iV13U4GZ/E/vb8KyXNjX CB/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776788995; x=1777393795; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=W9nxX3vo27aPKXMM9uM/grMyQNuhei9Pxu0QSoOCOso=; b=fJ6PwLUA3XhCj3qvQHIW9iVE262llqtsIhtMzIau6CIwVDZ1g+pOI4nYjxqGnNS952 OrSrO7dcYwDHTmBO1M21xxMniaehzykbXlLh3AVckxHKPjCKo+WgyIZovXjhpbrjACj0 Um+lAB6063T0MCVQy1Eo5taZkr4wiYCaU/UopczPny+ySqmJ2FmzraElDNc/74ZS+M22 F2uvIf+N4NRJMcWHrZOB9iOO2wMAwhgmz3MXGRwuWiPjFfN8G1D7wfdk+pOJh5FIMwzO m3noGZq4RSCAKs4mRJhBJo2ka1sUrPxZItVhlst2KQySdOuAwf3Cfof9LumtmvcnoY1h xyvQ== X-Gm-Message-State: AOJu0YzZ2oOojF89JTmb1L1JYEpvuBz8UJK8+B8iMrswkxXCjuiJUaEq dDPVj7te0JCSUWbK4ICO8JpSNPzIHTzCgpkvGF67IDLsmalGeLu+e4hx7svpHVw+yTtqKyhZGTE U/fRxRZ+sleCEf+tW5fm2UUl+31BcvZtzP0Ljox1JHLiOrrT9i8nTRlLclmyG6C2ywFZJQPIneg 4fDiztXeB/ZqnrePD2cQ0iPMijo4umF4aPrlU/dPQ0 X-Gm-Gg: AeBDieu6FMfbRQ+jZIn+5ECoRf2OgDQq49hQXP+UlOZRhEtQFbZRcIdz1vkJZofX0j5 qK+iOck36Safa3OpVPkKsUn1/KCRGXVtil7T7y3Ue6k/qWxVmxrqPdzSXJKqmQxwqGGrlhILr6S wfAUyy4TMzmhp22DzY9Yn0hY7jSIr/jYs+KnNw5OcdwiS7mIAh627qruU/wgqwiPPVEJR/XhBSp bCpUyyGYVP0e9rbvljm8TmZ4RTzLkS/jk/rNFTgf0UYBN0LOo4w/B3fiZIZkXxpvV2J17Ec7jpM Efag7OsRKsvIYi8k6zIQUIlhoAg5hDhDDM9xrlWi2U53L9FU77SWnU4GbLPEEX7adjqIL4tH0dt PNh9qy0qr5R4n+eZc3Lpk9C1JhS+dL9Rfd+ToO47maA2fZErp1zWH5CyVxcPHt8SazLtzszvVF3 SdWJgpdcEQgd9m/1+sYxtgxtyjD/KbPoJFI65YDPdSgvif88EQ8dBh2qE= X-Received: by 2002:a17:90b:4ecc:b0:35b:e553:9cc2 with SMTP id 98e67ed59e1d1-361404b9802mr18174499a91.26.1776788994782; Tue, 21 Apr 2026 09:29:54 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Peter Xu , Michael Rolnik , Helge Deller , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH v2 5/5] accel/tcg: Support IOMMU lazy translation in CPU TLB Date: Wed, 22 Apr 2026 00:29:12 +0800 Message-ID: <20260421162912.3295598-6-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260421162912.3295598-1-jim.shu@sifive.com> References: <20260421162912.3295598-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=jim.shu@sifive.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1776789079208158500 Content-Type: text/plain; charset="utf-8" tlb_set_page_full() no longer translates IOMMU region, but only stores untranslated IOMMU region in the CPUTLBEntryFull. Then, when CPU uses CPUTLBEntryFull in the slow path. it should perform the lazy translation via tlb_translate_iommu(). The untranslated IOMMU region in TLB always requires to run in the slow path to trigger the lazy translation, so the IOMMU region will contain a new TLB flag, TLB_IOMMU, to force the slow path. Lazy translation will overwrite the TLB flags to the flags of the translated region. The host memory region from IOMMU region can still run in the fast path to accelerate the performance. Signed-off-by: Jim Shu Acked-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 66 ++++++++++++++++++++++++++++++++++------ include/exec/tlb-flags.h | 4 ++- 2 files changed, 60 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5735f632896..7a44ae8238b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1034,7 +1034,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, hwaddr iotlb, xlat, sz, paddr_page; vaddr addr_page; int asidx, wp_flags, prot; - bool is_ram, is_romd; + bool is_ram, is_romd, is_iommu; =20 assert_cpu_is_self(cpu); =20 @@ -1049,29 +1049,38 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, =20 prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); - section =3D address_space_translate_for_iotlb_late(cpu, asidx, paddr_p= age, - &xlat, &sz, full->att= rs, - &prot); + + /* + * Use the early translation to check if it is an IOMMU region. + * This function stops at IOMMU regions without translating through th= em. + */ + section =3D address_space_translate_for_iotlb_early(cpu, asidx, paddr_= page, + &xlat, &sz, full->at= trs, + &prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx " prot=3D%x idx=3D%d\n", addr, full->phys_addr, prot, mmu_idx); =20 + is_iommu =3D memory_region_is_iommu(section->mr); + is_ram =3D memory_region_is_ram(section->mr); + is_romd =3D memory_region_is_romd(section->mr); + + full->is_iommu =3D is_iommu; + full->iommu_last_at =3D MMU_ACCESS_COUNT; + read_flags =3D full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |=3D TLB_INVALID_MASK; } =20 - is_ram =3D memory_region_is_ram(section->mr); - is_romd =3D memory_region_is_romd(section->mr); - if (is_ram || is_romd) { /* RAM and ROMD both have associated host memory. */ addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + xla= t; } else { - /* I/O does not; force the host address to NULL. */ + /* I/O and IOMMU does not; force the host address to NULL. */ addend =3D 0; } =20 @@ -1090,6 +1099,15 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, write_flags |=3D TLB_NOTDIRTY; } } + } else if (is_iommu) { + /* IOMMU */ + iotlb =3D xlat; + /* + * If IOMMU region is not translated, any access will go to + * the slow path and do the lazy IOMMU translation. + */ + read_flags |=3D TLB_IOMMU; + write_flags |=3D TLB_IOMMU; } else { /* I/O or ROMD */ iotlb =3D xlat; @@ -1568,6 +1586,11 @@ static int probe_access_internal(CPUState *cpu, vadd= r addr, flags &=3D tlb_addr; =20 *pfull =3D full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + + if (full->is_iommu) { + tlb_translate_iommu(cpu, mmu_idx, addr, access_type, full); + } + flags |=3D full->slow_flags[access_type]; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ @@ -1760,6 +1783,11 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, in= t mmu_idx, } =20 full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + + if (full->is_iommu) { + tlb_translate_iommu(cpu, mmu_idx, addr, access_type, full); + } + data->phys_addr =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); =20 /* We must have an iotlb entry for MMIO */ @@ -1833,6 +1861,11 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPage= Data *data, MemOp memop, } =20 full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + + if (full->is_iommu) { + tlb_translate_iommu(cpu, mmu_idx, addr, access_type, full); + } + flags =3D tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); flags |=3D full->slow_flags[access_type]; =20 @@ -1944,6 +1977,11 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, Me= mOpIdx oi, if (mmu_lookup1(cpu, &l->page[1], 0, l->mmu_idx, type, ra)) { uintptr_t index =3D tlb_index(cpu, l->mmu_idx, addr); l->page[0].full =3D &cpu->neg.tlb.d[l->mmu_idx].fulltlb[index]; + + if (l->page[0].full->is_iommu) { + tlb_translate_iommu(cpu, l->mmu_idx, addr, type, + l->page[0].full); + } } =20 flags =3D l->page[0].flags | l->page[1].flags; @@ -2001,6 +2039,17 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr = addr, MemOpIdx oi, tlb_addr =3D tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } =20 + full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; + + if (full->is_iommu) { + /* + * Do IOMMU lazy translation before accessing addr_idx and TLB fla= gs. + * Generate TLB flags for both read and write. + */ + tlb_translate_iommu(cpu, mmu_idx, addr, MMU_DATA_LOAD, full); + tlb_translate_iommu(cpu, mmu_idx, addr, MMU_DATA_STORE, full); + } + /* * Let the guest notice RMW on a write-only page. * We have just verified that the page is writable. @@ -2035,7 +2084,6 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr a= ddr, MemOpIdx oi, } =20 /* Finish collecting tlb flags for both read and write. */ - full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; tlb_addr |=3D tlbe->addr_read; tlb_addr &=3D TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; tlb_addr |=3D full->slow_flags[MMU_DATA_STORE]; diff --git a/include/exec/tlb-flags.h b/include/exec/tlb-flags.h index 357e79095c9..d78f1c3dc64 100644 --- a/include/exec/tlb-flags.h +++ b/include/exec/tlb-flags.h @@ -52,10 +52,12 @@ #define TLB_DISCARD_WRITE (1 << 3) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << 4) +/* Set if TLB entry is a IOMMU region which requires lazy translation. */ +#define TLB_IOMMU (1 << 5) =20 #define TLB_SLOW_FLAGS_MASK \ (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED | \ - TLB_DISCARD_WRITE | TLB_MMIO) + TLB_DISCARD_WRITE | TLB_MMIO | TLB_IOMMU) =20 /* * Flags stored in CPUTLBEntry.addr_idx[x]. --=20 2.43.0