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Tue, 21 Apr 2026 00:59:15 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Max Chou Subject: [PATCH v3 1/2] target/riscv: Update MISA.C for Zc* extensions Date: Tue, 21 Apr 2026 15:59:05 +0800 Message-ID: <20260421075906.2928317-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260421075906.2928317-1-frank.chang@sifive.com> References: <20260421075906.2928317-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1776758452500154100 Content-Type: text/plain; charset="utf-8" From: Frank Chang MISA.C is set if the following extensions are selected: * Zca and not F. * Zca, Zcf and F (but not D) is specified (RV32 only). * Zca, Zcf and Zcd if D is specified (RV32 only). * Zca, Zcd if D is specified (RV64 only). Therefore, we need to set MISA.C according to the rules for Zc* extensions. Signed-off-by: Frank Chang Reviewed-by: Max Chou --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f3f78088956..0f68560bac1 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1163,6 +1163,37 @@ static void riscv_cpu_enable_implied_rules(RISCVCPU = *cpu) } } =20 +/* + * MISA.C is set if the following extensions are selected: + * - Zca and not F. + * - Zca, Zcf and F (but not D) is specified on RV32. + * - Zca, Zcf and Zcd if D is specified on RV32. + * - Zca, Zcd if D is specified on RV64. + */ +static void riscv_cpu_update_misa_c(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + + if (cpu->cfg.ext_zca && !riscv_has_ext(env, RVF)) { + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC); + return; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32 && + cpu->cfg.ext_zca && cpu->cfg.ext_zcf && + (riscv_has_ext(env, RVD) ? cpu->cfg.ext_zcd : + riscv_has_ext(env, RVF))) { + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC); + return; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64 && + cpu->cfg.ext_zca && cpu->cfg.ext_zcd) { + riscv_cpu_set_misa_ext(env, env->misa_ext | RVC); + return; + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; @@ -1170,6 +1201,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, E= rror **errp) =20 riscv_cpu_init_implied_exts_rules(); riscv_cpu_enable_implied_rules(cpu); + riscv_cpu_update_misa_c(cpu); =20 riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1776758430; cv=none; d=zohomail.com; s=zohoarc; b=ET22MTKqW4BBw6PAu2EFtLR/imVu5MzIeYi9317itVUWZuJWlbMTmTU4JePuwyuHhdIzNsm6y3sE5k8H6s1YwQqa65CsqVXKzk4yGvAmVwwu9w3te7cUWwDvvNkNNGFMern4kyERl1ij9bGYpgajknQfVRNaI6qXvFlNXQr8xrw= ARC-Message-Signature: i=1; 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Tue, 21 Apr 2026 00:59:18 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang , Max Chou , Daniel Henrique Barboza Subject: [PATCH v3 2/2] target/riscv: Update MISA.X for non-standard extensions Date: Tue, 21 Apr 2026 15:59:06 +0800 Message-ID: <20260421075906.2928317-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260421075906.2928317-1-frank.chang@sifive.com> References: <20260421075906.2928317-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1776758432267154100 Content-Type: text/plain; charset="utf-8" From: Frank Chang MISA.X is set if there are any non-standard extensions. We should set MISA.X when any of the vendor extensions is enabled. Signed-off-by: Frank Chang Reviewed-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4c0676ed53b..175e877f90a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState; #define RVH RV('H') #define RVG RV('G') #define RVB RV('B') +#define RVX RV('X') =20 extern const uint32_t misa_bits[]; const char *riscv_get_misa_ext_name(uint32_t bit); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 0f68560bac1..44d948b5dca 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1194,6 +1194,20 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu) } } =20 +/* MISA.X is set when any of the non-standard extensions is enabled. */ +static void riscv_cpu_update_misa_x(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + const RISCVCPUMultiExtConfig *arr =3D riscv_cpu_vendor_exts; + + for (int i =3D 0; arr[i].name !=3D NULL; i++) { + if (isa_ext_is_enabled(cpu, arr[i].offset)) { + riscv_cpu_set_misa_ext(env, env->misa_ext | RVX); + break; + } + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; @@ -1202,6 +1216,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, E= rror **errp) riscv_cpu_init_implied_exts_rules(); riscv_cpu_enable_implied_rules(cpu); riscv_cpu_update_misa_c(cpu); + riscv_cpu_update_misa_x(cpu); =20 riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { --=20 2.43.0