From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447197; cv=none; d=zohomail.com; s=zohoarc; b=Ww3jkE/UICedmkmwLLkn6G1RbUMAbfqc498EzfrIAMRoxOUBmvxaZiBSDB/ItoWpKwYhXUYI2ItvHYeGGcoca3s/Scww04NFidFXs59XSBkUkFWyaPV8ILVGnilZVd5uRYDy7nhOXDt0s+oeFQXo2mZNJblF4C7Q9GxQ74CXH4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447197; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EmOVB5IZY29iVKWcgfaipTD5+/SR627N344UoUCnzG0=; b=Ta1sJEr0fXAAGOOf41/ncTZiHNNiYJWraelYz80ShaGqR9WbQYShsRtRNmJopChQbZdztbjAoI/6tfDcLHdjEPomn40v9yDgeJySyYgovsz3y6ytc7jeveXx0rYxSXFVJk1XqYnPotnrtLId+NpUPeF8jEGQWAkUqsM/WfbdeWI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447197694767.2248082470892; Fri, 17 Apr 2026 10:33:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn2u-00078o-TO; Fri, 17 Apr 2026 13:32:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2B-0006it-JJ for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:30 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn27-00020O-4o for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:14 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-43d7650202fso802500f8f.2 for ; Fri, 17 Apr 2026 10:31:10 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e4ffa8sm5819650f8f.35.2026.04.17.10.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 10:31:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1776447070; x=1777051870; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EmOVB5IZY29iVKWcgfaipTD5+/SR627N344UoUCnzG0=; b=azfnU0aXN70ysqfyU80GuL3fTfOuOK1XaWrCc2LiI4Nklvp7PU+amYjSWcyCSk/kN9 TFEFhv0Qunqi576v0nARKgb7ittiZE4x2JKCzUzBLxD2EuxXjQvcuFXw5TZl9/Dg9ggX 4NI+asxUMd0n4pNe3TShPmCjlLlvAH+4IbeK70b5QKhr2GeUC/cUNHJIw/yj3CLnx6Ag Vc80x9hs5B18tngbNAF+xU8N5ID8NqxvWev0Mg0sbmACJzM0StI3R5ZcjL6Yml/FqMEn LXN9hnFve88N6oVW7KYvm1ZAWx0dz9AnYWTqj/wcPFd5xTujzK3NHPqdW9sRQ0w4FgOK 82tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776447070; x=1777051870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=EmOVB5IZY29iVKWcgfaipTD5+/SR627N344UoUCnzG0=; b=B8qSGBZ81LtzAtL2PyBNIIKaCRJK9oayjYIeI3U+PZsMuw5JCVbunN1g5v6PzrU+/U Evv1uT04ShwxcQ8wrtvm+zfw7YC7mrwLrzwuznNXClDIk9UEvKSnB/Zls7w+0NTdnQes IC4twhC9uqn0oUhOjP77qBiKo2nBm6frvve3Lc8v3fgdUKo6M7WnGwasFWlwZMVK1y0R DyuRKhTmbTRMVtqVA8czYAvEYlZcaqEgYpi/GDQKtiQIXys0VmOEDvpOXifcpwGsDoLu mwLcWygZJ0wxPi2Q/iX8SlCrOwAcHLPuX5f5iVqWI4mWBvXqERbCwJd88q8Sx9JyoVDt 5FKw== X-Forwarded-Encrypted: i=1; AFNElJ+pKwtJqTWpqTEEPSyLG19FArMhsIgI+/xhJArhADWkrTFcE8SNw0qVSRZii7oqdujyvi4fMPqAtbw5@nongnu.org X-Gm-Message-State: AOJu0YwfQA0EcGw+m0zf/g+x5EKVBma1K+M0IbHi/eNDOPe5SR3K5neS FbycNjNa17ZZWDGzLrmfIjbrKHUCeA4pnjXgFh89UKsvWPcZ+xY/N5Rgq2xfQF+njrw= X-Gm-Gg: AeBDieuZWX2LmSWYZb6HqwLIwNDKxrF50UUrEUu04pe6x+utduxc7L6ny8RWxW1bKB7 x1F/w5XwWanK2I//oYhPicGB8RKC3EcJGW8vkq5Z8uWlIWFs8JL1gg1+P2IPOExiuaUSWxtj4wr EhrKBKbHIIzQF84/BcCBS8M9LgLw41gsvwuMV49gTSaDDmXwK/3KyqwuqFzEPcsKFrJ/z+1Exe1 A0zYpBECFgIkytfnXRi2ct1kCJxqDyywUtkEn/RdlVH1wybUHy2+5OjA6zM1gs/OHpaQh+HJ9fO VzzECNEqbs0okoHdSQ95s6n+4/PWKeFpXnEvPfYkOLfN0B61YlnP5tc2EyHX3NAtzSkfjXKRAxD P+lJVwqDVChBGLa6mWJqW7veELdRV3avd8fdThS50K+bBLC0rb5YDO4S4yNIPDlQbojja2lR1Y5 Et6m0hxxvx8JCGVev20kJ01mUVSZ4ePXqNqW9Mi7ZUoSWklGkrbaW5n/vUV4QlcvBDj54ASKz98 RUgbq0tMfGEmlgY3TMPRKudxzOt/94A9gQjLub8NA== X-Received: by 2002:a05:6000:250f:b0:43d:1df7:ed24 with SMTP id ffacd0b85a97d-43fe3ddffffmr6124966f8f.21.1776447069526; Fri, 17 Apr 2026 10:31:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Paolo Bonzini , Richard Henderson , "Dr. David Alan Gilbert" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour , Peter Xu , "Edgar E. Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 01/17] target/riscv: Make get_phys_page_debug handle non-page-aligned addrs Date: Fri, 17 Apr 2026 18:30:49 +0100 Message-ID: <20260417173105.1648172-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447198404158500 Content-Type: text/plain; charset="utf-8" Currently our implementations of SysemuCPUOps::get_phys_page_debug and SysemuCPUOps::get_phys_page_attrs_debug are a mix of "accepts a non-page-aligned virtual address and returns the corresponding non-page-aligned physical address" and "only returns a page-aligned physical address". This is awkward for callsites, which in practice all want the physical address for an arbitrary virtual address and have to work around the possibility of getting a page-aligned address, and it doesn't account for protection being possibly on a sub-page-sized granularity. We want to standardize on the implementation having to handle non-page-aligned addresses. The only thing in the riscv implementation that we need to fix is the place where we explicitly round the return value down to a page boundary before returning it. Drop that. Signed-off-by: Peter Maydell Reviewed-by: Chao Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index dd6c861a90..475e9cfd57 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1677,7 +1677,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, va= ddr addr) } } =20 - return phys_addr & TARGET_PAGE_MASK; + return phys_addr; } =20 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447261; cv=none; d=zohomail.com; s=zohoarc; b=Wei7wNQjBeAdIkhHP3NkMm2pbMnknv7aprvKaz8jy1VrlQZ9XQd//9tytGaiYZ7X9tPG8ppkvQOhA1FakE6bnKnrhDVkneV3tFevEQsvVlehMWQEt84a9rV20N8SxbLie3fkC3f8vxFuIWUcNYOYtVj8370BQSFMjoypdD5qwiA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447261; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pqdYb2Ac9eVKgwfgrSKBf0XMUR0VWrhwweydT8/TgLI=; b=nkY24VMB1eyHGbzQ9yJeUCY0XQS7Zpynnn7+7ar2BE8G1e9K7nAbVF8s8+EN6GAz3d2ShLAajN4PZDXeuStTrUkcLKU+QG0dcZqNsUWpCvelkAuptxtK8Pnk0gN8sux/HocBlpJOvbIWVF/cy5h3Z+vjo+VnLD7z5PUOmA1V8tM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447261894972.1767599857344; Fri, 17 Apr 2026 10:34:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn2v-0007Ao-Jo; Fri, 17 Apr 2026 13:32:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2G-0006jK-8Y for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:30 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2B-000218-9d for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:17 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-43fe608cb92so559956f8f.2 for ; Fri, 17 Apr 2026 10:31:12 -0700 (PDT) Received: from lanath.. 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 02/17] target/alpha: Make get_phys_page_debug handle non-page-aligned addrs Date: Fri, 17 Apr 2026 18:30:50 +0100 Message-ID: <20260417173105.1648172-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447262735158500 Content-Type: text/plain; charset="utf-8" Currently our implementations of SysemuCPUOps::get_phys_page_debug and SysemuCPUOps::get_phys_page_attrs_debug are a mix of "accepts a non-page-aligned virtual address and returns the corresponding non-page-aligned physical address" and "only returns a page-aligned physical address". This is awkward for callsites, which in practice all want the physical address for an arbitrary virtual address and have to work around the possibility of getting a page-aligned address, and it doesn't account for protection being possibly on a sub-page-sized granularity. We want to standardize on the implementation having to handle non-page-aligned addresses. For alpha, the get_physical_address() function accepts arbitrary input addresses but may return an output rounded down to a page boundary, so in alpha_cpu_get_phys_page_debug() we OR the within-page offset into it before returning it. Signed-off-by: Peter Maydell --- target/alpha/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 179dc2dc7a..af6d7847d5 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -301,6 +301,7 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) int prot, fail; =20 fail =3D get_physical_address(cpu_env(cs), addr, 0, 0, &phys, &prot); + phys |=3D addr & ~TARGET_PAGE_MASK; return (fail >=3D 0 ? -1 : phys); } =20 --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447157; cv=none; d=zohomail.com; s=zohoarc; b=jy527RspID7fI3o4rQaUXMhTDvdEX8flQnuAC5J/bI2VGPUg0IhcavtvKB3BmibUwjSF/KuvjgvjjEEPoMPA4QF4q2/qyqPl4Q+6Et4MLYa0pWlhl6rNQcKgR4vQEKSI44FTz6Ow68t51/xmkwozhFFJ6v0CO3p9VrnknGff/ZQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447157; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KQYrrv1L4J6sS80hNKRy6gThlptUiC2z7DTgSRrd8fY=; b=Eu92N3l68A2wqaLtjr7eWjVfzgsmg4aVgWc8zWtpeOwTScvNoEE8p3G46Cbi5bnT9b3mwl8EEGC4uXzQqzzH/KovjpW+m8JLoE5pweuE/sH9IsixmYuE56NWhYJAdtvVdaW2SNEixjN7v11Enl2tqeDNzVTbkFaltIy+tMtzw/E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177644715773056.55032067784339; Fri, 17 Apr 2026 10:32:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn2s-0006z2-EH; Fri, 17 Apr 2026 13:31:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2G-0006jR-AM for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:30 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2B-00021a-AQ for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:17 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-43d73422431so706773f8f.2 for ; Fri, 17 Apr 2026 10:31:13 -0700 (PDT) Received: from lanath.. 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 03/17] target/microblaze: Make get_phys_page_attrs_debug handle non-page-aligned addrs Date: Fri, 17 Apr 2026 18:30:51 +0100 Message-ID: <20260417173105.1648172-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447159985154100 Content-Type: text/plain; charset="utf-8" Currently our implementations of SysemuCPUOps::get_phys_page_debug and SysemuCPUOps::get_phys_page_attrs_debug are a mix of "accepts a non-page-aligned virtual address and returns the corresponding non-page-aligned physical address" and "only returns a page-aligned physical address". This is awkward for callsites, which in practice all want the physical address for an arbitrary virtual address and have to work around the possibility of getting a page-aligned address, and it doesn't account for protection being possibly on a sub-page-sized granularity. We want to standardize on the implementation having to handle non-page-aligned addresses. For microblaze, we just need to remove the explicit rounding down to the page boundary that we were doing in mb_cpu_get_phys_page_attrs_debug() when calculating the output physaddr from the results of the MMU lookup. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index a1857b7217..da8abe063e 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -284,7 +284,6 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, v= addr addr, MemTxAttrs *attrs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); - vaddr vaddr; hwaddr paddr =3D 0; MicroBlazeMMULookup lu; int mmu_idx =3D cpu_mmu_index(cs, false); @@ -297,12 +296,12 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs,= vaddr addr, if (mmu_idx !=3D MMU_NOMMU_IDX) { hit =3D mmu_translate(cpu, &lu, addr, 0, 0); if (hit) { - vaddr =3D addr & TARGET_PAGE_MASK; - paddr =3D lu.paddr + vaddr - lu.vaddr; + paddr =3D lu.paddr + addr - lu.vaddr; } else paddr =3D 0; /* ???. */ - } else - paddr =3D addr & TARGET_PAGE_MASK; + } else { + paddr =3D addr; + } =20 return paddr; } --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447358; cv=none; d=zohomail.com; s=zohoarc; b=ZUePsdBBWB5Y6R/0EMrGDifbUDG8bmMASuv7Azc9hhwUdocILxMyS4UZBZcJ9VcxXuObvxeiYFWevv/RPdXGDgDeViK5bz00okGwUawMyRGJVYlp/qNBVTKLAf7Awvumyx3vBzyFZE3aiVWniGIz7rXCpg2bnfiXIh98ZTtNSkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447358; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hx5mHEmjy/ymmHAzveA8k8qKhyafNUszJu+T9FqcJ2Y=; b=Pv7sVIbSoMIx1rX6kFWI/CINMzSuPUu1a14DcxLAOE7ZeZ6bq/wzQeF7Bva+OSE023YDgr8AVAN7v0aARWZXi1t6CeAJIvu+tRIklaelq2/lZ/jHPQ3NMnXs9vrSTup1NKI2wjknJu4mKMXKC7BuuR3h/2CD6EkGEJHKCJyX7/Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447358845817.4965843178703; Fri, 17 Apr 2026 10:35:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn2v-0007At-QU; Fri, 17 Apr 2026 13:32:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2G-0006jS-AV for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:31 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2B-00022V-Sw for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:19 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-488a4bc360bso5895495e9.0 for ; Fri, 17 Apr 2026 10:31:15 -0700 (PDT) Received: from lanath.. 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 04/17] target/sparc: Make get_phys_page_debug handle non-page-aligned addrs Date: Fri, 17 Apr 2026 18:30:52 +0100 Message-ID: <20260417173105.1648172-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447360721154100 Content-Type: text/plain; charset="utf-8" Currently our implementations of SysemuCPUOps::get_phys_page_debug and SysemuCPUOps::get_phys_page_attrs_debug are a mix of "accepts a non-page-aligned virtual address and returns the corresponding non-page-aligned physical address" and "only returns a page-aligned physical address". This is awkward for callsites, which in practice all want the physical address for an arbitrary virtual address and have to work around the possibility of getting a page-aligned address, and it doesn't account for protection being possibly on a sub-page-sized granularity. We want to standardize on the implementation having to handle non-page-aligned addresses. The sparc TLB lookup code can handle non-aligned input addresses but will return page-aligned results. Rather than attempting to change the internals of the lookup code, we take the simple approach of ORing the page offset back into the phys_addr result. Signed-off-by: Peter Maydell --- target/sparc/mmu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index a6f76a1ab7..25f8a85fae 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -913,7 +913,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) return -1; } } - return phys_addr; + return phys_addr | (addr & ~TARGET_PAGE_MASK); } =20 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447316; cv=none; d=zohomail.com; s=zohoarc; b=SQMEFbMnGp8fviGv4wmiBJQj9ZG0HfYfCin+h49D2b36CmE3E4QAK6dsnBRLhH7HZ/HUf1DNQ41c+i3nOyBDp0189NDuixIavpWCUQLn55/j4RCid3T8grG4fZMsZMdmyQLB3jRRr2AOygM4wPXO2LicSJwVcknCnQFrJF2j6mo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447316; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zwAS7ZT+4GzIr0Ax+jfMns5onR8BsHM96TfH2Ah3gOw=; b=AXQ0XPxE/cDlL39+UXkRNGbaL9IPQFHve/K+Nrfc+1Q+zpPzbjpg8oAMRgMa7t+2R/98AG99BOvW37rSOLp7ZCt42U3IxNBvJIuoQPbROzoGPeoFGxQ1tWnqzymYn3Q9rzgChOD6tYRvyYiZcKbIwi2gydioL4eGwRO9ySUqQn8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447316570231.4347878574962; Fri, 17 Apr 2026 10:35:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn2w-0007BO-T8; Fri, 17 Apr 2026 13:32:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2L-0006kC-16 for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:30 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2F-00023T-Rl for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:22 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-488afb0427eso11675735e9.1 for ; Fri, 17 Apr 2026 10:31:18 -0700 (PDT) Received: from lanath.. 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 05/17] target/x86: Make get_phys_page_attrs_debug handle non-page-aligned addrs Date: Fri, 17 Apr 2026 18:30:53 +0100 Message-ID: <20260417173105.1648172-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447318064154100 Content-Type: text/plain; charset="utf-8" Currently our implementations of SysemuCPUOps::get_phys_page_debug and SysemuCPUOps::get_phys_page_attrs_debug are a mix of "accepts a non-page-aligned virtual address and returns the corresponding non-page-aligned physical address" and "only returns a page-aligned physical address". This is awkward for callsites, which in practice all want the physical address for an arbitrary virtual address and have to work around the possibility of getting a page-aligned address, and it doesn't account for protection being possibly on a sub-page-sized granularity. We want to standardize on the implementation having to handle non-page-aligned addresses. For x86 this is simple: we just need to stop rounding down the input address to a TARGET_PAGE boundary when calculating the result to return. Signed-off-by: Peter Maydell --- target/i386/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index c397a6fde5..108b02396d 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -372,7 +372,7 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, = vaddr addr, out: #endif pte &=3D PG_ADDRESS_MASK & ~(page_size - 1); - page_offset =3D (addr & TARGET_PAGE_MASK) & (page_size - 1); + page_offset =3D addr & (page_size - 1); return pte | page_offset; } =20 --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447160; cv=none; d=zohomail.com; s=zohoarc; b=aNdZGE+W+jxheH4X3lkNCHEhMAYRQeOAg54ineD1vHufQiF1bwohfR+iNPhFaPj7jiuYrIKuBFGnijtz7iCsqoDhyiPJ2UCJ3cmBowaoDreHhO07Jz2X2Rw1TxpVz9WuiOwbvRYhnYMbuUVB6OWQ2DxnionZzgRT8qC4g5mRnmo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447160; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dnIJ3EmNqXbziGIQGEMV/q/0xOD9YQRq2D+dL5Z773s=; b=PwxxpIzMXu+q52+3sSi3WD62E9WEUH0LvI5BcGSJJXCMQGjfldu6u9xNHpS13K79SedbUhbkJCGJoX4WS24ZtHaiXGYKNOocRsAb7nlcDNq1dTQbX5AAfOLDVnlSnheLtp+9cEjlsynHk28kHC2Nzbug1tQjCcExJC+Fk3g5JDg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447160055123.38124942152206; Fri, 17 Apr 2026 10:32:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn2z-0007Fz-7B; Fri, 17 Apr 2026 13:32:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2P-0006kj-6l for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:31 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2K-000259-Py for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:27 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-482f454be5bso20229515e9.0 for ; Fri, 17 Apr 2026 10:31:22 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e4ffa8sm5819650f8f.35.2026.04.17.10.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 10:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1776447082; x=1777051882; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dnIJ3EmNqXbziGIQGEMV/q/0xOD9YQRq2D+dL5Z773s=; b=ohf+deQWd2ed5G8KdTvZpzMjE7hsOEPXk5Scs0bgj168ou2eVGmiG8HIp9R4zND4Gd EYpyM1alqL2K55Im4cfvC7togpJXZd/fvwJkmB4chFwwT1MZKF46Lr3jEFRW+OGml9Ou 2/XtYX2w3k6ce7euJvIY2AsOujLM/0t2v2dYnfWpkDdYiX/h5GtKfLaT1ktkxWU2t0/e k1exrbo+nV3AJsI+CB4orN/wi/lXzyWfUKgl5GI7J4J9SpmSLn7mQ5q3sN/oQGi3vBG4 Y35qH/7XGNBun/1K9px8qcNG0gKF2N/fglSd0HPQU7/rPzHUSzbAjBEQ6wh52BsMb/ay VOvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776447082; x=1777051882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dnIJ3EmNqXbziGIQGEMV/q/0xOD9YQRq2D+dL5Z773s=; b=XIEH0klzcpDVd6OYcGZFf1maRbwE1Im1wnKbYR+mYVavXJvknaShwImzqmyn8dscwT XgmswVuWhdQcSEYRn7h+ftmo7lbE+pBv/poCXsIACcY6kql7RNHYxX0gnzEUtnxKLUX5 qGcyMRNXC447GTGg/AyzILNwFMkpdoRMnIYtNCev6Xzuq1DfjJa8JsTaTZio6mbOZwSe 8PkrO5VQQxmXcxr9ziEJfop9reMLPra0Xhd+QvtrCu/tOSoGD+10OdCHY75g3X0/WtVu pk5Ar7VSVIN8NcWqsr1Y9ir/L/+6hvJKyqo8+D2SI86e2SKoN9uY6+JBOabQdbFUFaV1 1NlQ== X-Forwarded-Encrypted: i=1; AFNElJ/sqRlPKc5+TRccFGQQs6Vf+pdD2Mikp1N0bCOlyYbRgpbV7eDGxZMKJdnyh/mXTMogZ8JJp/VbN2N7@nongnu.org X-Gm-Message-State: AOJu0Yz9WtIRQbT3IKIZ9/xmxMYAyXzo+YSXYQF3GxIgQnuQRO3pj4DQ vy3wCtwkK+xNvxUnznM1Y29ztwe6NeilP3iDhqTzNTkhh+VAFPy99zRrs3jK/+UhlNs= X-Gm-Gg: AeBDiesfy6TufcqIKB70QMjq7+d4K/sQXdzOC+xKX8abbB8s9hyGXG5AOuat5AZUavq SOvCODWXbAwLKpH0tTtjjGhER2aopPmAPnBTNd9O9cPR96PMVzGp4P/hOhjwvkgkWPLK8aAHApr FqZbIXemQTJ6ggpLQnyDoh7O00ZeiAgB7GvFCTXfhmomWKMVfbV/hh0FHiRamDhysK4I11RI2b3 iaw9Ip9gdFUuM6//ScTf6Rdjs+AeZ++G2u2uqsLenq9/kxwrGqzJi4dn3PGFvGhVRuH53f2aKlf dBKMSw03rYuzBQbpqjgcUsWkrMFtvJIkVC2OQMsWB00AbsqQmHA92fcM+cV83NKj9Wg98YvPPFD ZwVZmTmmofojd7MUIrQPR+3kMcxG1siZQenhqm4qTiHU6AeVdfrIw122h/fbTLivoy3CoGCEV8w AMrYr/pxu1iuKqtWVO3ogk2oVTVYQdc42YtRfM1a4E7thUyOCSNLbSfXWkJU3EjWsXCsK9yZGyX EX6xjALHUmoEsax68kIGue9VzWOHfVWm9/ziSvWaw== X-Received: by 2002:a5d:6e66:0:b0:43d:7cc0:dac2 with SMTP id ffacd0b85a97d-43fe409de50mr4168195f8f.30.1776447081616; Fri, 17 Apr 2026 10:31:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Paolo Bonzini , Richard Henderson , "Dr. David Alan Gilbert" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour , Peter Xu , "Edgar E. Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 06/17] target/s390x: Make get_phys_page_debug handle non-page-aligned addrs Date: Fri, 17 Apr 2026 18:30:54 +0100 Message-ID: <20260417173105.1648172-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447162536158500 Content-Type: text/plain; charset="utf-8" Currently our implementations of SysemuCPUOps::get_phys_page_debug and SysemuCPUOps::get_phys_page_attrs_debug are a mix of "accepts a non-page-aligned virtual address and returns the corresponding non-page-aligned physical address" and "only returns a page-aligned physical address". This is awkward for callsites, which in practice all want the physical address for an arbitrary virtual address and have to work around the possibility of getting a page-aligned address, and it doesn't account for protection being possibly on a sub-page-sized granularity. We want to standardize on the implementation having to handle non-page-aligned addresses. s390x already has an implementation of "give me the actual physical address, not rounded down", in s390_get_phys_addr_debug(), so we can use this for the SysemuCPUOps::get_phys_page_debug method, and merge the s390_cpu_get_phys_page_debug() function into s390_get_phys_addr_debug() which is now its only caller. This leaves the function implementing the method with a name that doesn't match the method name, but we will fix that shortly by renaming the method to *_addr_* for all targets. Signed-off-by: Peter Maydell Reviewed-by: Ilya Leoshkevich --- target/s390x/cpu-system.c | 2 +- target/s390x/helper.c | 20 +++++--------------- target/s390x/s390x-internal.h | 1 - 3 files changed, 6 insertions(+), 17 deletions(-) diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index 881171d71a..c133b0c262 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -176,7 +176,7 @@ void s390_cpu_finalize(Object *obj) =20 static const struct SysemuCPUOps s390_sysemu_ops =3D { .has_work =3D s390_cpu_has_work, - .get_phys_page_debug =3D s390_cpu_get_phys_page_debug, + .get_phys_page_debug =3D s390_cpu_get_phys_addr_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .legacy_vmsd =3D &vmstate_s390_cpu, diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 667d4a0da7..1a2658eaf9 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -39,7 +39,7 @@ void s390x_cpu_timer(void *opaque) cpu_inject_cpu_timer((S390CPU *) opaque); } =20 -hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) +hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { S390CPU *cpu =3D S390_CPU(cs); CPUS390XState *env =3D &cpu->env; @@ -47,10 +47,11 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr= vaddr) int prot; uint64_t asc =3D env->psw.mask & PSW_MASK_ASC; uint64_t tec; + vaddr page =3D addr & TARGET_PAGE_MASK; =20 /* 31-Bit mode */ if (!(env->psw.mask & PSW_MASK_64)) { - vaddr &=3D 0x7fffffff; + page &=3D 0x7fffffff; } =20 /* We want to read the code (e.g., see what we are single-stepping).*/ @@ -62,24 +63,13 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr= vaddr) * We want to read code even if IEP is active. Use MMU_DATA_LOAD inste= ad * of MMU_INST_FETCH. */ - if (mmu_translate(env, vaddr, MMU_DATA_LOAD, asc, &raddr, &prot, &tec)= ) { + if (mmu_translate(env, page, MMU_DATA_LOAD, asc, &raddr, &prot, &tec))= { return -1; } + raddr +=3D (addr & ~TARGET_PAGE_MASK); return raddr; } =20 -hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr v_addr) -{ - hwaddr phys_addr; - vaddr page; - - page =3D v_addr & TARGET_PAGE_MASK; - phys_addr =3D cpu_get_phys_page_debug(cs, page); - phys_addr +=3D (v_addr & ~TARGET_PAGE_MASK); - - return phys_addr; -} - static inline bool is_special_wait_psw(uint64_t psw_addr) { /* signal quiesce */ diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 40850bcdc4..e7e4f2b45d 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -321,7 +321,6 @@ void do_restart_interrupt(CPUS390XState *env); void s390x_tod_timer(void *opaque); void s390x_cpu_timer(void *opaque); void s390_handle_wait(S390CPU *cpu); -hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); LowCore *cpu_map_lowcore(CPUS390XState *env); void cpu_unmap_lowcore(CPUS390XState *env, LowCore *lowcore); --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447339; cv=none; d=zohomail.com; s=zohoarc; b=HYcz8mMVHW6lKp/iyzb7Pbdk/mmRs7YuYbVZEMJ5cFpl4sw68fPwS3FA5Me4cyOf2ImPkP7l+Aw05uBydbqg3vXwXpTPQ90ZwSiHDLIJhgvHmaYtTsewu7HvmJoZuhMUSR37rQQLUDivfRmI6CE/7nKX8044uxxD6TSro+dJiZg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447339; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eHyMHLlx5igXR+yw1MChRiibsNdSLH75zIK4yP1cYmM=; b=geEruwbp8F3HpUYuqBA+b5T00bFceJE2kxKy9SAF5HqOXQA07DfjgDfv6kxNbf9T1+PR1uxGOIdKpurwREYZr0iQ6ygF5b+ujhoCBDoRpq8KmFwYrFmKEmOw3D9ktdGA7Zdv4mhjmlQIPNl7e1CUhjM0/A7VCbcMXBWoylv5BtE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447339855325.81976176007265; Fri, 17 Apr 2026 10:35:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn33-0007JC-DN; Fri, 17 Apr 2026 13:32:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2P-0006kl-73 for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:35 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2L-00025T-2F for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:27 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-43d01d6b50cso949960f8f.1 for ; Fri, 17 Apr 2026 10:31:24 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e4ffa8sm5819650f8f.35.2026.04.17.10.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 10:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1776447083; x=1777051883; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eHyMHLlx5igXR+yw1MChRiibsNdSLH75zIK4yP1cYmM=; b=f7eWhYaL58Mnvl++MAJq/aeAT7dimrHLdd609H2Va3sNYb6+8ssYAmRUcE6wao6uaj muXd5M90sUF7lLPlOD17Z9FnpZgOz/r1ubqqjPBtB6qO6OdkpGHu72wtngYgdEEUxKLm XmaePfYy2Nud7fQbTBaL7Tpl9QQuMjROt42dfBwIPiz3dHLLZTosGFAqM5MeCQqQ/fgm 68yy1yislmxItWdjf2xtMdTcwjPSLWIQZrT6bjkxaxW3vuVq4jDByNro/Ao4bTkVWEHJ wemPOAFtgXr0YEWlhW+6lEBwTiEuHa/GYeIobk3yClsRnxdMs4Evc9MnyFiiiEsam7nz nEPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776447083; x=1777051883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=eHyMHLlx5igXR+yw1MChRiibsNdSLH75zIK4yP1cYmM=; b=GTDyotIXP2EQlAYntj+/UvlOPAGYhRC0L1klnWQDAKJUPNPgDScPEywQSk1oASm5lo BcQ39HGv3lAnD8HpPOUVu/SUq6l75v6hMhcCL56ppjT/SEhpqc2FEZOsPvQD5DT81+Ys JpVDXj/NIiwW54FigOYMGS4s2udLkSlf5RuHr2U9TDc5LL+++dT7Grmo8VAbhj5ApsCr sXBNI/rBWVE3AUn58bUdAOHIE1Kjke9GV8IIgVVny/7P/AYZrc1m4vUwUI+IRdrGqfCz 1KgyRaMLcmJIOjuT2ns/X+vmgZNAPEkMWB+d2lJCL/97AHp6VFl7H26pdTr/ZevAtr4F 1wFw== X-Forwarded-Encrypted: i=1; AFNElJ8Yg1L/xLxpffu+j0KQYFg4DBBIQLhjiVs9tHlxvyimJByiTuMPq/vLnRqDtP2sqSqG0k9piEVjl1aL@nongnu.org X-Gm-Message-State: AOJu0Yykxowggmd+axsTnjduBc00onOVkoWxPAoQER+b4B8b/qM4z4a8 l+bNAvmINxzZ3S0BMPzizizLHycddxFgapmmBfDuau2UgOdBP2U3Lldp8B3siH3f7Wc= X-Gm-Gg: AeBDieupj6mzCrgxoLZRncLXDlbjpQoGcvsck/cW6ym7RnTaKKH6Kl6rPMqxero9hAY BBnmR163Q8xr+Xd0KfIiQHHzgZ0PJDfEVPfkg4H6dirbf4+guLnGLtWn+gg3411qPZSdxNhYjva Ed8iGITv3XA7Pl4SIEOJUsV04Dx0JcbBmCwGPYmNYrdHTh2O5dMn1OdPGoZiWXhvEHW/eeLN51E 1hL3bIAh6Xiyl8tblmZ1bTFXFgRdkc78FlxafGd2BEldxM/tYkMtsYOerJLrOGu7PcoubdQHmRf Pqjw2YsglbzW/BgZFMYXrR2ouRXuCxQE9RjFYP8i1TZdwW4lVuMDTpGnwXE6DAfdXcwYrhsNI1v rDDSzZ+EK0C1QW3/BkE6gKRT4uk/NuZ7315ltVtGjg1gHMg4Exq2Jd7YWCS/L/eJDJSMg6y8PqO XhfrntB6fY01p/PzAQpJW4QQBJwBhsmv+sHOSzMAOxFqHO+e1S1CVXlHvnh+CsxfFK7QcaBn7MK 61Va6vTpADNSTTSTWkGryRpzU+XDlMu/UIOUfUosw== X-Received: by 2002:a05:6000:186c:b0:43e:a703:3665 with SMTP id ffacd0b85a97d-43fe3e0c6femr5984589f8f.25.1776447083356; Fri, 17 Apr 2026 10:31:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Paolo Bonzini , Richard Henderson , "Dr. David Alan Gilbert" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour , Peter Xu , "Edgar E. Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 07/17] target/ppc: Make get_phys_page_debug handle non-page-aligned addrs Date: Fri, 17 Apr 2026 18:30:55 +0100 Message-ID: <20260417173105.1648172-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447342519154100 Content-Type: text/plain; charset="utf-8" Currently our implementations of SysemuCPUOps::get_phys_page_debug and SysemuCPUOps::get_phys_page_attrs_debug are a mix of "accepts a non-page-aligned virtual address and returns the corresponding non-page-aligned physical address" and "only returns a page-aligned physical address". This is awkward for callsites, which in practice all want the physical address for an arbitrary virtual address and have to work around the possibility of getting a page-aligned address, and it doesn't account for protection being possibly on a sub-page-sized granularity. We want to standardize on the implementation having to handle non-page-aligned addresses. The ppc_xlate() function can accept a non-page-aligned input but may return a page-aligned output; we take the simple approach of ORing the page offset back into the result address after calling it. Signed-off-by: Peter Maydell --- target/ppc/mmu_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 52d48615ac..a1345df716 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -863,7 +863,7 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr = addr) ppc_env_mmu_index(&cpu->env, false), false) || ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, ppc_env_mmu_index(&cpu->env, true), false)) { - return raddr & TARGET_PAGE_MASK; + return raddr | (addr & ~TARGET_PAGE_MASK); } return -1; } --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447318; cv=none; d=zohomail.com; s=zohoarc; b=fA0mpu5CoMAdiTt5GE1O9GMRip0GW61v8s3ABuX1LLYB7kQRwncYWKld4YZ0bh3tGlXYtj6BpFXS6K/Nk415cva6nfxU0qi8Wl/00XYIH7UjjXSeAiMPKWHCwGa3vUZhyrEvDn7nmiuAlqJxXYxkL0rzLD/ed0NEuSrl8TsimEk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447318; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MkwtueKO2HhcMpMXUls5Zclcah8lgf1lAzMKkQHSvo8=; b=m1gI7XFHKksEOFjJbEij5kJon0oi/Pid6sETL3hkfK9NZ9GGZrfXXTQJwIdBTBy+fVH0iCJvqiTVo6vKsMDQTHLj5WozYfteEdUEZDHeE1nIQTMi09ONe4TPNGX+gx7irBYmgWqF7ExDl/DIpV4n9b88xV9l/AXxeljWzZyidqk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447318447922.2594641585163; Fri, 17 Apr 2026 10:35:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn36-0007Ot-Ut; Fri, 17 Apr 2026 13:32:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2X-0006pb-IZ for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:42 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2O-00026F-Pb for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:35 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-43fe608cb92so560097f8f.2 for ; Fri, 17 Apr 2026 10:31:27 -0700 (PDT) Received: from lanath.. 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 08/17] target: Rename get_phys_page_debug to get_phys_addr_debug Date: Fri, 17 Apr 2026 18:30:56 +0100 Message-ID: <20260417173105.1648172-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447320390154100 Content-Type: text/plain; charset="utf-8" Now that we have ensured that all implementations of the get_phys_page_debug method handle a non-page-aligned input and return the corresponding non-page-aligned output, the name of the method is somewhat misleading. Rename it to get_phys_addr_debug. This commit was produced with the commands sed -i -e 's/_cpu_get_phys_page_debug/_cpu_get_phys_addr_debug/g;s/\/get_phys_addr_debug/g' $(git grep -l get_phys_page_debug) sed -i -e 's/_cpu_get_phys_page_attrs_debug/_cpu_get_phys_addr_attrs_debug= /g;s/\/get_phys_addr_attrs_debug/g' $(git grep = -l get_phys_page_attrs_debug) which catches all references to the method name itself plus the functions which each target uses as the method implementation, but (deliberately) not the cpu_phys_get_page_debug() and cpu_phys_get_page_attrs_debug() wrapper functions or their callers. (We'll deal with those in the next commit.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu-system.c | 6 +++--- include/hw/core/sysemu-cpu-ops.h | 10 +++++----- target/alpha/cpu.c | 2 +- target/alpha/cpu.h | 2 +- target/alpha/helper.c | 2 +- target/arm/cpu.c | 2 +- target/arm/cpu.h | 2 +- target/arm/ptw.c | 2 +- target/avr/cpu.c | 2 +- target/avr/cpu.h | 2 +- target/avr/helper.c | 2 +- target/hppa/cpu.c | 2 +- target/hppa/cpu.h | 2 +- target/hppa/mem_helper.c | 2 +- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 +- target/i386/helper.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- target/loongarch/cpu-mmu.h | 2 +- target/loongarch/cpu.c | 2 +- target/loongarch/cpu_helper.c | 2 +- target/m68k/cpu.c | 2 +- target/m68k/cpu.h | 2 +- target/m68k/helper.c | 2 +- target/microblaze/cpu.c | 2 +- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 2 +- target/mips/cpu.c | 2 +- target/mips/internal.h | 2 +- target/mips/system/physaddr.c | 2 +- target/or1k/cpu.c | 2 +- target/or1k/cpu.h | 2 +- target/or1k/mmu.c | 2 +- target/ppc/cpu.h | 2 +- target/ppc/cpu_init.c | 2 +- target/ppc/mmu-hash32.c | 2 +- target/ppc/mmu_common.c | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 2 +- target/rx/cpu.c | 2 +- target/rx/cpu.h | 2 +- target/rx/helper.c | 2 +- target/s390x/cpu-system.c | 2 +- target/sh4/cpu.c | 2 +- target/sh4/cpu.h | 2 +- target/sh4/helper.c | 2 +- target/sparc/cpu.c | 2 +- target/sparc/cpu.h | 2 +- target/sparc/mmu_helper.c | 2 +- target/tricore/cpu.c | 2 +- target/tricore/cpu.h | 2 +- target/tricore/helper.c | 2 +- target/xtensa/cpu.c | 2 +- target/xtensa/cpu.h | 2 +- target/xtensa/mmu_helper.c | 2 +- 56 files changed, 62 insertions(+), 62 deletions(-) diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 273b9b7c22..93dc861083 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -60,13 +60,13 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { hwaddr paddr; =20 - if (cpu->cc->sysemu_ops->get_phys_page_attrs_debug) { - paddr =3D cpu->cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, + if (cpu->cc->sysemu_ops->get_phys_addr_attrs_debug) { + paddr =3D cpu->cc->sysemu_ops->get_phys_addr_attrs_debug(cpu, addr, attrs); } else { /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - paddr =3D cpu->cc->sysemu_ops->get_phys_page_debug(cpu, addr); + paddr =3D cpu->cc->sysemu_ops->get_phys_addr_debug(cpu, addr); } /* Indicate that this is a debug access. */ attrs->debug =3D 1; diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 7b2d2d2610..a4fc330bea 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -30,17 +30,17 @@ typedef struct SysemuCPUOps { */ bool (*get_paging_enabled)(const CPUState *cpu); /** - * @get_phys_page_debug: Callback for obtaining a physical address. + * @get_phys_addr_debug: Callback for obtaining a physical address. */ - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + hwaddr (*get_phys_addr_debug)(CPUState *cpu, vaddr addr); /** - * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * @get_phys_addr_attrs_debug: Callback for obtaining a physical addre= ss * and the associated memory transaction attributes to use for t= he * access. * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. + * instead of get_phys_addr_debug. */ - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + hwaddr (*get_phys_addr_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ff053043a3..0c35067b20 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -242,7 +242,7 @@ static void alpha_cpu_initfn(Object *obj) =20 static const struct SysemuCPUOps alpha_sysemu_ops =3D { .has_work =3D alpha_cpu_has_work, - .get_phys_page_debug =3D alpha_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D alpha_cpu_get_phys_addr_debug, }; #endif =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 45944e46b5..e49ebca578 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -283,7 +283,7 @@ extern const VMStateDescription vmstate_alpha_cpu; =20 void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); -hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr alpha_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); #endif /* !CONFIG_USER_ONLY */ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/alpha/helper.c b/target/alpha/helper.c index af6d7847d5..33fed0c746 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -295,7 +295,7 @@ static int get_physical_address(CPUAlphaState *env, vad= dr addr, return ret; } =20 -hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr alpha_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { hwaddr phys; int prot, fail; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ccc47c8a9a..f28c74a94b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2295,7 +2295,7 @@ static vaddr aarch64_untagged_addr(CPUState *cs, vadd= r x) =20 static const struct SysemuCPUOps arm_sysemu_ops =3D { .has_work =3D arm_cpu_has_work, - .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, + .get_phys_addr_attrs_debug =3D arm_cpu_get_phys_addr_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 657ff4ab20..917e4668da 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1231,7 +1231,7 @@ extern const VMStateDescription vmstate_arm_cpu; void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); =20 -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, +hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); =20 typedef struct ARMGranuleProtectionConfig { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7b993bb5b3..f5f624c7c3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3943,7 +3943,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env,= vaddr addr, return res.f.phys_addr; } =20 -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, +hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8579a7283b..3591219212 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -233,7 +233,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { .has_work =3D avr_cpu_has_work, - .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D avr_cpu_get_phys_addr_debug, }; =20 static const TCGCPUOps avr_tcg_ops =3D { diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 518e243d81..7ebdc7b953 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -178,7 +178,7 @@ extern const struct VMStateDescription vms_avr_cpu; =20 void avr_cpu_do_interrupt(CPUState *cpu); bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req); -hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr avr_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int avr_print_insn(bfd_vma addr, disassemble_info *info); diff --git a/target/avr/helper.c b/target/avr/helper.c index 365c8c60e1..f3be8483b2 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -107,7 +107,7 @@ void avr_cpu_do_interrupt(CPUState *cs) qemu_plugin_vcpu_interrupt_cb(cs, ret); } =20 -hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr avr_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { return addr; /* I assume 1:1 address correspondence */ } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 92027d129a..6443122cf1 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -244,7 +244,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 static const struct SysemuCPUOps hppa_sysemu_ops =3D { .has_work =3D hppa_cpu_has_work, - .get_phys_page_debug =3D hppa_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D hppa_cpu_get_phys_addr_debug, }; #endif =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7d47afe8ef..8a859d27b0 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -389,7 +389,7 @@ int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t = *buf, int reg); void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); #ifndef CONFIG_USER_ONLY void hppa_ptlbe(CPUHPPAState *env); -hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); +hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr); void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled= ); bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr add= r, MMUAccessType access_type, int mmu_idx, diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index ffbad8acfd..f507649226 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -345,7 +345,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr = addr, int mmu_idx, return ret; } =20 -hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr hppa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { HPPACPU *cpu =3D HPPA_CPU(cs); hwaddr phys; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c6fd1dc00e..be331cab25 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10691,7 +10691,7 @@ static const struct SysemuCPUOps i386_sysemu_ops = =3D { .has_work =3D x86_cpu_has_work, .get_memory_mapping =3D x86_cpu_get_memory_mapping, .get_paging_enabled =3D x86_cpu_get_paging_enabled, - .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, + .get_phys_addr_attrs_debug =3D x86_cpu_get_phys_addr_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0b539155c4..8615361cc9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2580,7 +2580,7 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env); #ifndef CONFIG_USER_ONLY int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); =20 -hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, +hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); int cpu_get_pic_interrupt(CPUX86State *s); =20 diff --git a/target/i386/helper.c b/target/i386/helper.c index 108b02396d..8cc73f619a 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -252,7 +252,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_= cr4) } =20 #if !defined(CONFIG_USER_ONLY) -hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, +hwaddr x86_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { X86CPU *cpu =3D X86_CPU(cs); diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index e56ae2b343..406ca0355c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -238,7 +238,7 @@ struct whpx_register_set { * e. Let the affected CPU run in the exclusive mode. * f. Restore the original handler and the exception exit bitmap. * Note that handling all corner cases related to IDT/GDT is harder - * than it may seem. See x86_cpu_get_phys_page_attrs_debug() for a + * than it may seem. See x86_cpu_get_phys_addr_attrs_debug() for a * rough idea. * * 3. In order to properly support guest-level debugging in parallel w= ith diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 3286accc14..2d7ebb2d72 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -97,7 +97,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *= context, int access_type, int mmu_idx, int debug); void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, unsigned int level); -hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); uint64_t loongarch_palen_mask(CPULoongArchState *env); =20 #endif /* LOONGARCH_CPU_MMU_H */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index e22568c84a..43ba414ac5 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -832,7 +832,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE= *f, int flags) static const struct SysemuCPUOps loongarch_sysemu_ops =3D { .has_work =3D loongarch_cpu_has_work, .write_elf64_note =3D loongarch_cpu_write_elf64_note, - .get_phys_page_debug =3D loongarch_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D loongarch_cpu_get_phys_addr_debug, }; =20 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 6044168766..181b931130 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -354,7 +354,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMU= Context *context, return loongarch_map_address(env, context, access_type, mmu_idx, is_de= bug); } =20 -hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { CPULoongArchState *env =3D cpu_env(cs); MMUContext context; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index d849a4a90f..425efdf7cc 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -606,7 +606,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 static const struct SysemuCPUOps m68k_sysemu_ops =3D { .has_work =3D m68k_cpu_has_work, - .get_phys_page_debug =3D m68k_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D m68k_cpu_get_phys_addr_debug, }; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7911ab9de3..b181d5f981 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -186,7 +186,7 @@ struct M68kCPUClass { #ifndef CONFIG_USER_ONLY void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); -hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr m68k_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); #endif /* !CONFIG_USER_ONLY */ void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bab184389..2dd9ec1bdc 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -907,7 +907,7 @@ txfail: return -1; } =20 -hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr m68k_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { CPUM68KState *env =3D cpu_env(cs); hwaddr phys_addr; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index ec513ae82d..20fffccb60 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -428,7 +428,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 static const struct SysemuCPUOps mb_sysemu_ops =3D { .has_work =3D mb_cpu_has_work, - .get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug, + .get_phys_addr_attrs_debug =3D mb_cpu_get_phys_addr_attrs_debug, }; #endif =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d26b933b6d..d42565808f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -370,7 +370,7 @@ struct MicroBlazeCPUClass { #ifndef CONFIG_USER_ONLY void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); -hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, +hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); #endif /* !CONFIG_USER_ONLY */ G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index da8abe063e..f81c4f625b 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -280,7 +280,7 @@ void mb_cpu_do_interrupt(CPUState *cs) } } =20 -hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, +hwaddr mb_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 5f88c077db..6ef18105b9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -535,7 +535,7 @@ static ObjectClass *mips_cpu_class_by_name(const char *= cpu_model) =20 static const struct SysemuCPUOps mips_sysemu_ops =3D { .has_work =3D mips_cpu_has_work, - .get_phys_page_debug =3D mips_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D mips_cpu_get_phys_addr_debug, .legacy_vmsd =3D &vmstate_mips_cpu, }; #endif diff --git a/target/mips/internal.h b/target/mips/internal.h index 28eb28936b..24bfa1903c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -115,7 +115,7 @@ enum { int get_physical_address(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong real_address, MMUAccessType access_type, int mmu_idx); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr mips_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); =20 typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { diff --git a/target/mips/system/physaddr.c b/target/mips/system/physaddr.c index b8e1a5ac98..fbbbcf6e00 100644 --- a/target/mips/system/physaddr.c +++ b/target/mips/system/physaddr.c @@ -228,7 +228,7 @@ int get_physical_address(CPUMIPSState *env, hwaddr *phy= sical, return ret; } =20 -hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr mips_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { CPUMIPSState *env =3D cpu_env(cs); hwaddr phys_addr; diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 3d1c22bf75..ea29b2e01f 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -247,7 +247,7 @@ static void openrisc_any_initfn(Object *obj) =20 static const struct SysemuCPUOps openrisc_sysemu_ops =3D { .has_work =3D openrisc_cpu_has_work, - .get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D openrisc_cpu_get_phys_addr_debug, }; #endif =20 diff --git a/target/or1k/cpu.h b/target/or1k/cpu.h index c8e2827930..8f20b9a122 100644 --- a/target/or1k/cpu.h +++ b/target/or1k/cpu.h @@ -297,7 +297,7 @@ void openrisc_translate_code(CPUState *cs, TranslationB= lock *tb, int print_insn_or1k(bfd_vma addr, disassemble_info *info); =20 #ifndef CONFIG_USER_ONLY -hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); =20 bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/or1k/mmu.c b/target/or1k/mmu.c index 315debaf3e..3ff288a1f9 100644 --- a/target/or1k/mmu.c +++ b/target/or1k/mmu.c @@ -138,7 +138,7 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, in= t size, cpu_loop_exit_restore(cs, retaddr); } =20 -hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); int prot, excp, sr =3D cpu->env.sr; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d637a50798..24a53ee2e1 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1639,7 +1639,7 @@ void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int f= lags); int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #ifndef CONFIG_USER_ONLY -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr ppc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); #endif int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 191f5726f6..d25f69f13b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7477,7 +7477,7 @@ static void ppc_disas_set_info(const CPUState *cs, di= sassemble_info *info) =20 static const struct SysemuCPUOps ppc_sysemu_ops =3D { .has_work =3D ppc_cpu_has_work, - .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D ppc_cpu_get_phys_addr_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, .internal_is_big_endian =3D ppc_cpu_is_big_endian, diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 8b980a5aa9..43d581cadf 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -131,7 +131,7 @@ static bool ppc_hash32_direct_store(PowerPCCPU *cpu, ta= rget_ulong sr, } =20 /* - * From ppc_cpu_get_phys_page_debug, env->access_type is not set. + * From ppc_cpu_get_phys_addr_debug, env->access_type is not set. * Assume ACCESS_INT for that case. */ switch (guest_visible ? env->access_type : ACCESS_INT) { diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index a1345df716..2499e619f8 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -848,7 +848,7 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessT= ype access_type, } } =20 -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr ppc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); hwaddr raddr; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ac935ac06..e5d8592ef2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2717,7 +2717,7 @@ static int64_t riscv_get_arch_id(CPUState *cs) =20 static const struct SysemuCPUOps riscv_sysemu_ops =3D { .has_work =3D riscv_cpu_has_work, - .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D riscv_cpu_get_phys_addr_debug, .write_elf64_note =3D riscv_cpu_write_elf64_note, .write_elf32_note =3D riscv_cpu_write_elf32_note, .legacy_vmsd =3D &vmstate_riscv_cpu, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35d1f6362c..111afe19d1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -629,7 +629,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retad= dr); -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 475e9cfd57..584a3928a4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1657,7 +1657,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, env->two_stage_indirect_lookup =3D two_stage_indirect; } =20 -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index b5284199e6..20b188c24c 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -209,7 +209,7 @@ static void rx_cpu_init(Object *obj) =20 static const struct SysemuCPUOps rx_sysemu_ops =3D { .has_work =3D rx_cpu_has_work, - .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D rx_cpu_get_phys_addr_debug, }; =20 static const TCGCPUOps rx_tcg_ops =3D { diff --git a/target/rx/cpu.h b/target/rx/cpu.h index b3b1ecff5a..328521791b 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -137,7 +137,7 @@ struct RXCPUClass { const char *rx_crname(uint8_t cr); void rx_cpu_do_interrupt(CPUState *cpu); bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); -hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr rx_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/rx/helper.c b/target/rx/helper.c index daaeeec1b5..0f99279bba 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -147,7 +147,7 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_= request) return false; } =20 -hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr rx_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { return addr; } diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index c133b0c262..1bd3721d10 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -176,7 +176,7 @@ void s390_cpu_finalize(Object *obj) =20 static const struct SysemuCPUOps s390_sysemu_ops =3D { .has_work =3D s390_cpu_has_work, - .get_phys_page_debug =3D s390_cpu_get_phys_addr_debug, + .get_phys_addr_debug =3D s390_cpu_get_phys_addr_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .legacy_vmsd =3D &vmstate_s390_cpu, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index e2bde45761..40d5fde76d 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -278,7 +278,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { =20 static const struct SysemuCPUOps sh4_sysemu_ops =3D { .has_work =3D superh_cpu_has_work, - .get_phys_page_debug =3D superh_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D superh_cpu_get_phys_addr_debug, }; #endif =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index b0759010c4..3743452190 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -252,7 +252,7 @@ void sh4_translate_code(CPUState *cs, TranslationBlock = *tb, int *max_insns, vaddr pc, void *host_pc); =20 #if !defined(CONFIG_USER_ONLY) -hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr superh_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 5d6295618f..b3ec7ce64d 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -435,7 +435,7 @@ static int get_physical_address(CPUSH4State *env, hwadd= r* physical, return get_mmu_address(env, physical, prot, address, access_type); } =20 -hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr superh_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { hwaddr physical; int prot; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1493336e7a..d5a08928e5 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -997,7 +997,7 @@ static const Property sparc_cpu_properties[] =3D { =20 static const struct SysemuCPUOps sparc_sysemu_ops =3D { .has_work =3D sparc_cpu_has_work, - .get_phys_page_debug =3D sparc_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D sparc_cpu_get_phys_addr_debug, .legacy_vmsd =3D &vmstate_sparc_cpu, }; #endif diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 0139732e4c..307b98b76c 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -580,7 +580,7 @@ struct SPARCCPUClass { #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_sparc_cpu; =20 -hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr sparc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); #endif =20 void sparc_cpu_do_interrupt(CPUState *cpu); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 25f8a85fae..34b212a7aa 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -902,7 +902,7 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, ta= rget_ulong addr, } #endif =20 -hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr sparc_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { CPUSPARCState *env =3D cpu_env(cs); hwaddr phys_addr; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 04319e107b..472c24ae32 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -176,7 +176,7 @@ static bool tricore_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) =20 static const struct SysemuCPUOps tricore_sysemu_ops =3D { .has_work =3D tricore_cpu_has_work, - .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D tricore_cpu_get_phys_addr_debug, }; =20 static const TCGCPUOps tricore_tcg_ops =3D { diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index ab46192e26..56241b491f 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -80,7 +80,7 @@ struct TriCoreCPUClass { ResettablePhases parent_phases; }; =20 -hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr tricore_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); =20 FIELD(PCXI, PCPN_13, 24, 8) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7ee8c7fd69..ce1693622b 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -46,7 +46,7 @@ static int get_physical_address(CPUTriCoreState *env, hwa= ddr *physical, return ret; } =20 -hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr tricore_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { TriCoreCPU *cpu =3D TRICORE_CPU(cs); hwaddr phys_addr; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index eebf40559b..8a22f1a08e 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -303,7 +303,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { =20 static const struct SysemuCPUOps xtensa_sysemu_ops =3D { .has_work =3D xtensa_cpu_has_work, - .get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug, + .get_phys_addr_debug =3D xtensa_cpu_get_phys_addr_debug, }; #endif =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 2219292484..546a5e76a6 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -591,7 +591,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, vaddr addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t reta= ddr); -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); bool xtensa_debug_check_breakpoint(CPUState *cs); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 71330fc84b..a126f6b671 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -316,7 +316,7 @@ static void xtensa_tlb_set_entry(CPUXtensaState *env, b= ool dtlb, } } =20 -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr xtensa_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 09/17] target: Rename cpu_get_phys_page_{,attrs_}debug Date: Fri, 17 Apr 2026 18:30:57 +0100 Message-ID: <20260417173105.1648172-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447363290158500 Content-Type: text/plain; charset="utf-8" Rename cpu_phys_page_debug() and cpu_phys_page_attrs_debug() to cpu_phys_addr_debug() and cpu_phys_addr_attrs_debug(). Commit created with: sed -i -e 's/cpu_get_phys_page_debug/cpu_get_phys_addr_debug/g;s/cpu_get_p= hys_page_attrs_debug/cpu_get_phys_addr_attrs_debug/g' $(git grep -l cpu_get= _phys_page) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu-system.c | 6 +++--- hw/i386/vapic.c | 4 ++-- hw/xtensa/sim.c | 2 +- hw/xtensa/xtfpga.c | 2 +- include/hw/core/cpu.h | 8 ++++---- monitor/hmp-cmds.c | 2 +- plugins/api.c | 2 +- system/physmem.c | 2 +- target/sparc/mmu_helper.c | 6 +++--- target/xtensa/xtensa-semi.c | 2 +- 10 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 93dc861083..05c126ecb6 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -55,7 +55,7 @@ bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingL= ist *list, return false; } =20 -hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, +hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs) { hwaddr paddr; @@ -73,11 +73,11 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, return paddr; } =20 -hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +hwaddr cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr) { MemTxAttrs attrs =3D {}; =20 - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); + return cpu_get_phys_addr_attrs_debug(cpu, addr, &attrs); } =20 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) diff --git a/hw/i386/vapic.c b/hw/i386/vapic.c index 41e5ca26df..20183242a7 100644 --- a/hw/i386/vapic.c +++ b/hw/i386/vapic.c @@ -173,7 +173,7 @@ static int find_real_tpr_addr(VAPICROMState *s, CPUX86S= tate *env) * virtual address space for the APIC mapping. */ for (addr =3D 0xfffff000; addr >=3D 0x80000000; addr -=3D TARGET_PAGE_= SIZE) { - paddr =3D cpu_get_phys_page_debug(cs, addr); + paddr =3D cpu_get_phys_addr_debug(cs, addr); if (paddr !=3D APIC_DEFAULT_ADDRESS) { continue; } @@ -305,7 +305,7 @@ static int update_rom_mapping(VAPICROMState *s, CPUX86S= tate *env, target_ulong i =20 /* find out virtual address of the ROM */ rom_state_vaddr =3D s->rom_state_paddr + (ip & 0xf0000000); - paddr =3D cpu_get_phys_page_debug(cs, rom_state_vaddr); + paddr =3D cpu_get_phys_addr_debug(cs, rom_state_vaddr); if (paddr =3D=3D -1) { return -1; } diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 994460d041..32eb16442f 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -41,7 +41,7 @@ static uint64_t translate_phys_addr(void *opaque, uint64_= t addr) { XtensaCPU *cpu =3D opaque; =20 - return cpu_get_phys_page_debug(CPU(cpu), addr); + return cpu_get_phys_addr_debug(CPU(cpu), addr); } =20 static void sim_reset(void *opaque) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index ed24720f94..0c66dff557 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -192,7 +192,7 @@ static uint64_t translate_phys_addr(void *opaque, uint6= 4_t addr) { XtensaCPU *cpu =3D opaque; =20 - return cpu_get_phys_page_debug(CPU(cpu), addr); + return cpu_get_phys_addr_debug(CPU(cpu), addr); } =20 static void xtfpga_reset(void *opaque) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 04e1f970ca..6dedad535c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -745,7 +745,7 @@ enum CPUDumpFlags { void cpu_dump_state(CPUState *cpu, FILE *f, int flags); =20 /** - * cpu_get_phys_page_attrs_debug: + * cpu_get_phys_addr_attrs_debug: * @cpu: The CPU to obtain the physical page address for. * @addr: The virtual address. * @attrs: Updated on return with the memory transaction attributes to use @@ -757,11 +757,11 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags= ); * * Returns: Corresponding physical page address or -1 if no page found. */ -hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, +hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); =20 /** - * cpu_get_phys_page_debug: + * cpu_get_phys_addr_debug: * @cpu: The CPU to obtain the physical page address for. * @addr: The virtual address. * @@ -770,7 +770,7 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index bc26b39d70..e6d8322bcc 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -720,7 +720,7 @@ void hmp_gva2gpa(Monitor *mon, const QDict *qdict) return; } =20 - gpa =3D cpu_get_phys_page_debug(cs, addr & TARGET_PAGE_MASK); + gpa =3D cpu_get_phys_addr_debug(cs, addr & TARGET_PAGE_MASK); if (gpa =3D=3D -1) { monitor_printf(mon, "Unmapped\n"); } else { diff --git a/plugins/api.c b/plugins/api.c index 0c348a789b..4b6fad4999 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -619,7 +619,7 @@ bool qemu_plugin_translate_vaddr(uint64_t vaddr, uint64= _t *hwaddr) #ifdef CONFIG_SOFTMMU g_assert(current_cpu); =20 - uint64_t res =3D cpu_get_phys_page_debug(current_cpu, vaddr); + uint64_t res =3D cpu_get_phys_addr_debug(current_cpu, vaddr); =20 if (res =3D=3D (uint64_t)-1) { return false; diff --git a/system/physmem.c b/system/physmem.c index 4e26f1a1d4..f2d9a4ff8f 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -4047,7 +4047,7 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, MemTxResult res; =20 page =3D addr & TARGET_PAGE_MASK; - phys_addr =3D cpu_get_phys_page_attrs_debug(cpu, page, &attrs); + phys_addr =3D cpu_get_phys_addr_attrs_debug(cpu, page, &attrs); asidx =3D cpu_asidx_from_attrs(cpu, attrs); /* if no physical page mapped, return an error */ if (phys_addr =3D=3D -1) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 34b212a7aa..e1abd520c4 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -366,20 +366,20 @@ void dump_mmu(CPUSPARCState *env) for (n =3D 0, va =3D 0; n < 256; n++, va +=3D 16 * 1024 * 1024) { pde =3D mmu_probe(env, va, 2); if (pde) { - pa =3D cpu_get_phys_page_debug(cs, va); + pa =3D cpu_get_phys_addr_debug(cs, va); qemu_printf("VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n", va, pa, pde); for (m =3D 0, va1 =3D va; m < 64; m++, va1 +=3D 256 * 1024) { pde =3D mmu_probe(env, va1, 1); if (pde) { - pa =3D cpu_get_phys_page_debug(cs, va1); + pa =3D cpu_get_phys_addr_debug(cs, va1); qemu_printf(" VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); for (o =3D 0, va2 =3D va1; o < 64; o++, va2 +=3D 4 * 1= 024) { pde =3D mmu_probe(env, va2, 0); if (pde) { - pa =3D cpu_get_phys_page_debug(cs, va2); + pa =3D cpu_get_phys_addr_debug(cs, va2); qemu_printf(" VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx " PTE: " TARGET_FMT_lx "\n", diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index 28dfb29cbd..9a6a9c8b4e 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -215,7 +215,7 @@ void HELPER(simcall)(CPUXtensaState *env) uint32_t len_done =3D 0; =20 while (len > 0) { - hwaddr paddr =3D cpu_get_phys_page_debug(cs, vaddr); + hwaddr paddr =3D cpu_get_phys_addr_debug(cs, vaddr); uint32_t page_left =3D TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1)); uint32_t io_sz =3D page_left < len ? page_left : len; --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 10/17] hw/core: Update docs for get_phys_addr_{attrs_,}debug Date: Fri, 17 Apr 2026 18:30:58 +0100 Message-ID: <20260417173105.1648172-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447379180154100 Content-Type: text/plain; charset="utf-8" Update the documentation for the get_phys_addr_{attrs_,}debug methods and wrapper functions to state that they can handle non-page aligned addresses and will return the corresponding exact physaddr for them. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 16 +++++++++++----- include/hw/core/sysemu-cpu-ops.h | 4 ++++ 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6dedad535c..0941757c55 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -746,15 +746,18 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags= ); =20 /** * cpu_get_phys_addr_attrs_debug: - * @cpu: The CPU to obtain the physical page address for. + * @cpu: The CPU to use for the virtual-to-physical translation * @addr: The virtual address. * @attrs: Updated on return with the memory transaction attributes to use * for this access. * - * Obtains the physical page corresponding to a virtual one, together + * Obtains the physical address corresponding to a virtual one, together * with the corresponding memory transaction attributes to use for the acc= ess. * Use it only for debugging because no protection checks are done. * + * The address need not be page-aligned; the returned address will + * be the physical address corresponding to that virtual address. + * * Returns: Corresponding physical page address or -1 if no page found. */ hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, @@ -762,13 +765,16 @@ hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, v= addr addr, =20 /** * cpu_get_phys_addr_debug: - * @cpu: The CPU to obtain the physical page address for. + * @cpu: The CPU to use for the virtual-to-physical translation * @addr: The virtual address. * - * Obtains the physical page corresponding to a virtual one. + * Obtains the physical address corresponding to a virtual one. * Use it only for debugging because no protection checks are done. * - * Returns: Corresponding physical page address or -1 if no page found. + * The address need not be page-aligned; the returned address will + * be the physical address corresponding to that virtual address. + * + * Returns: Corresponding physical address, or -1 if no page found. */ hwaddr cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index a4fc330bea..a87c55d922 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -31,6 +31,8 @@ typedef struct SysemuCPUOps { bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_addr_debug: Callback for obtaining a physical address. + * This must be able to handle a non-page-aligned address, and will + * return the physical address corresponding to that address. */ hwaddr (*get_phys_addr_debug)(CPUState *cpu, vaddr addr); /** @@ -39,6 +41,8 @@ typedef struct SysemuCPUOps { * access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_addr_debug. + * This must be able to handle a non-page-aligned address, and will + * return the physical address corresponding to that address. */ hwaddr (*get_phys_addr_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 11/17] target/arm: Rename arm_cpu_get_phys_page() Date: Fri, 17 Apr 2026 18:30:59 +0100 Message-ID: <20260417173105.1648172-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447379153154100 Content-Type: text/plain; charset="utf-8" The internal helper function arm_cpu_get_phys_page() is named that way because of its use in the get_phys_page_attrs_debug method. Now we've renamed the method, rename the helper to match, since it can handle non-page-aligned addresses. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f5f624c7c3..8be6f243e6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3922,7 +3922,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, memop, result, fi); } =20 -static hwaddr arm_cpu_get_phys_page(CPUARMState *env, vaddr addr, +static hwaddr arm_cpu_get_phys_addr(CPUARMState *env, vaddr addr, MemTxAttrs *attrs, ARMMMUIdx mmu_idx) { S1Translate ptw =3D { @@ -3950,7 +3950,7 @@ hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs= , vaddr addr, CPUARMState *env =3D &cpu->env; ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); =20 - hwaddr res =3D arm_cpu_get_phys_page(env, addr, attrs, mmu_idx); + hwaddr res =3D arm_cpu_get_phys_addr(env, addr, attrs, mmu_idx); =20 if (res !=3D -1) { return res; @@ -3964,10 +3964,10 @@ hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *= cs, vaddr addr, switch (mmu_idx) { case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - return arm_cpu_get_phys_page(env, addr, attrs, ARMMMUIdx_E10_0); + return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E10_0); case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - return arm_cpu_get_phys_page(env, addr, attrs, ARMMMUIdx_E20_0); + return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E20_0); default: return -1; } --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447241; cv=none; d=zohomail.com; s=zohoarc; b=PFnXhK/xynIdSVPW9CHdvpKWaE/gmkXzReqPI+sTQT3cUOLnBMw5xRkajOGlNpdyGlYRHg3IXeXPBbIWg61viXQKbojlEKQs3Tf655cOeJ2cGn2dp3ZNpx5rSKwSyanmCTFNrfd4hWwZoEYQGOPEJKwnR0MV3ZTIIV0Ee2DfEfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447241; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Otb+V+N26YB8iFs+WkqEaZZLt8iUFfx2rXXM3vvsWPA=; b=BTOdadXww6jdKRi5rbZrnIJDrrBHVz3aqFu3cC4PlBWxckj/8qZ0s4C5RBNqcI2PSU1fPBn5J0yAY3bdtvOXw/ktjhXcpWcsraPvdZhOTgAgan64iNe571OaeVcI7Q/ZlaQwU6mU8hNhAhj1Iq1MMLn3Oza5KrBSmtWiWLvI5xg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177644724108769.0468106448277; Fri, 17 Apr 2026 10:34:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn38-0007Q6-CN; Fri, 17 Apr 2026 13:32:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2b-0006tR-5D for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:48 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2V-0002CK-80 for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:39 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-482f454be5bso20232305e9.0 for ; Fri, 17 Apr 2026 10:31:33 -0700 (PDT) Received: from lanath.. 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 12/17] monitor: hmp_gva2gpa: Don't page-align cpu_get_phys_addr_debug() arg and return Date: Fri, 17 Apr 2026 18:31:00 +0100 Message-ID: <20260417173105.1648172-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447242566158500 Content-Type: text/plain; charset="utf-8" In hmp_gva2gpa() we currently have a workaround for not all implementations of get_phys_addr_debug handling non-page-aligned addresses: we round the input address from the user down to the target page boundary before the call and then add the page offset back to the returned value. Now that we guarantee that all implementations will return the correct exact physaddr for a virtual address, we can drop this handling. Signed-off-by: Peter Maydell Acked-by: Dr. David Alan Gilbert Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- monitor/hmp-cmds.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index e6d8322bcc..f8380bda58 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -720,12 +720,11 @@ void hmp_gva2gpa(Monitor *mon, const QDict *qdict) return; } =20 - gpa =3D cpu_get_phys_addr_debug(cs, addr & TARGET_PAGE_MASK); + gpa =3D cpu_get_phys_addr_debug(cs, addr); if (gpa =3D=3D -1) { monitor_printf(mon, "Unmapped\n"); } else { - monitor_printf(mon, "gpa: 0x%" HWADDR_PRIx "\n", - gpa + (addr & ~TARGET_PAGE_MASK)); + monitor_printf(mon, "gpa: 0x%" HWADDR_PRIx "\n", gpa); } } =20 --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447316; cv=none; d=zohomail.com; s=zohoarc; b=Rehjfd/jSWGJoha/nowePbBAUqkYht3EOK5YDUK8VhXHDKqnZWCuHkywXB4VyRwrHsTmsIMrK7U3ZaStihw0sfXVQMedrp2uwN+HH+I0Z+ZhhGV73ZnHbKycLijgraNOO019WK2fDvGfmwmjlZk8JcDtaTHsTqJOGbAlbx9KTxo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447316; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DaHo77KFkT8Px7cBdcv5JOj+A13ipNoa8Ob819EY2bI=; b=cyADB4fINbHyDfWIupbvlLxgPWAqL7dFi5qV1dro25Rc6iXavm35axNEbLIumYrZ8IC+fIF9izeiUmXP8Mc3O38YrLRB6c9uZEw3YQ20Gc8VWilgfB6svLMlGQGFAE4qMjk+TyTV3Xp+muWilZcT0RDmRuE0hC3PZpit3ZPxNfM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447316131278.58496004927224; Fri, 17 Apr 2026 10:35:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn37-0007PE-4R; Fri, 17 Apr 2026 13:32:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2b-0006tX-E6 for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:48 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2X-0002DQ-4D for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:41 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-43cf7683a28so668442f8f.2 for ; Fri, 17 Apr 2026 10:31:35 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e4ffa8sm5819650f8f.35.2026.04.17.10.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 10:31:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1776447094; x=1777051894; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DaHo77KFkT8Px7cBdcv5JOj+A13ipNoa8Ob819EY2bI=; b=tQGlt1GZEojDuX9Dg/lQDy8T4nru8/CFiRct/cnw/92Z4UegPtrB2okmRUI70A6QhL 6Lxr/3LFPOLQi8UgDCG03xA0fRvfN4zta/7D80q8pk1UNNXr1glWBXcfhfDHElwEKuQp vwQXAgK2Pwvf+FtgLTVe7rEHHRpxDsL91R+AQ04Vg+FRdjnNW5o/KwSzHWV365Fu8yLP CZeh2/CU8ekuuKnGNqo02PmbonGAGsUmFPurZNQdNSxry99aaNlwC8zyeBCAww7fZ3lF ttOgT7xrv2CuYfB9q3HSBHAS0dbE+2Yc4LhbAt1nCteiZRxzXyvDgLfxLt48X52Ofh75 nW1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776447094; x=1777051894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=DaHo77KFkT8Px7cBdcv5JOj+A13ipNoa8Ob819EY2bI=; b=Tyz5RPOX5FVbTQI3VGy8Jlf1WysfXJeCMOAxf78uGvluOkZBB1r4tPQXM4uLVsmW8V eCo6c2U98frz3yMF8rdcyPnqlVhoud2TduEqX9ycZ2I9uV060ZS0iL67e5rwun8dMBK6 +E0e167wMY56KhrviBazfe/gaQaL1uKbK6aqc+1ouwYd9uhmAoF0NHVadFD0SzAC9bY7 6SCeFDxrzzeCX/McPWJzhz9Y9MUbzo/cS+q9v3rq6YEOpU9pQ4JRxD2N76vUpBSIUvth F2o/xkgUtdjmLJFRJejCD+pJ6oLb/yluILcnNPJ8EKQS4GcbR+oHvi39XZ7WlPbkI6+L 6GdA== X-Forwarded-Encrypted: i=1; AFNElJ8d3fDeD8BAbgBcXEEbPnC9NA37IxZX7I1wjNlP/41f4ssScsMrsxYowOp3dnhhXtKDrJWkGpQGnoIP@nongnu.org X-Gm-Message-State: AOJu0Ywh8Kx4NcX5RLB9E9k/0yfqXhnYwRaukvp3aGwwPbNDyUpMBg51 FlkJ0p32Xk7vFWIbvrXZ28IV2qn5CpsXaWkkqZIrJjjFM8Odjs7KRrP7c/usjfJAkF8= X-Gm-Gg: AeBDieu3azdZveT1spGkx2NQdA7/ol1HfmIgI+bTVRX+a2SWnH4qyQ0D7foG+liQibp 9kS1iXyulBNG1eCkKgL1eeFuV7B2FEnz4Ei9NOITwXnRAWb2saDPgiAWAbxE386w2SylcJpaUTL 1A8RcMecaGwBR9+ld5TANWBOi5J+tTIUTvrgkCjoO6GTPYwRx+B13GfUoUX6QNKohrzNlHWh6oi bh5YAqIfZnawcZJF//cGxEgxQSFo5dFW7vYgtlL+Ae+xmTHkcKtHR3aDpct6zZb6ugXaz3GIJwC uUgy7lx8acXrvY1GU4HBYCbJ6RWdH5DbRnPV9s70dNKtjUJpJeUu22xOs2djJEo2iGzjp8qqPqa C3fWshca/tfvDQjTsD4+P2+gbL0aIyrE72jPWeh1OgDdi+JqpnutG3A6cmNeJbpQf5zUVaq3+s6 nC/SSnet3ot61vl0H/2Gx97zrDgd228f7i74PMSbC3QiSa5OiAPvZjN4KUokxgJXKI+Xre2N6qY vPowOxs8BYE/4d1bJ6yTLneR3oLsSzUWfEO+OQkOg== X-Received: by 2002:a05:6000:40dc:b0:43c:ffee:ee94 with SMTP id ffacd0b85a97d-43fe3dca95cmr5737764f8f.11.1776447093977; Fri, 17 Apr 2026 10:31:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Paolo Bonzini , Richard Henderson , "Dr. David Alan Gilbert" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour , Peter Xu , "Edgar E. Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 13/17] plugins/api.c: Trust cpu_get_phys_addr_debug() return address Date: Fri, 17 Apr 2026 18:31:01 +0100 Message-ID: <20260417173105.1648172-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447318020154100 Content-Type: text/plain; charset="utf-8" In qemu_plugin_translate_vaddr() we have a workaround for not all implementations of get_phys_addr_debug returning an exact physaddr for the input virtual address: we OR back in the page offset to the return value. Now that we guarantee that get_phys_addr_debug returns the exact physaddr for the input virtual address, we can drop this workaround. Signed-off-by: Peter Maydell --- plugins/api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plugins/api.c b/plugins/api.c index 4b6fad4999..c97cc68882 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -625,7 +625,7 @@ bool qemu_plugin_translate_vaddr(uint64_t vaddr, uint64= _t *hwaddr) return false; } =20 - *hwaddr =3D res | (vaddr & ~TARGET_PAGE_MASK); + *hwaddr =3D res; =20 return true; #else --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447254; cv=none; d=zohomail.com; s=zohoarc; b=LtmLhGuLD/elfHF3nFds57y3e3pO4OxXJW8s2Gulpjlp1vxzQHgaVojsi7X1e5ljA6fECG3txuvL4pwI9O0FcDfVMy4+LDlbQce9MO7UJcJ5NYWy53aOUvBCh8s1q0Qb0wOTsLdqWlyM7D7U/zT/fk5nCVxz7lPoX9/jlqbUOps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447254; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=q1XLnzDD++kcgvvN+mJ7kGySfBQkB+0ZpLjBuZfsQOc=; b=JDg1OGSQ1DfXEMMRhaoOVCxkcZOCkXAJl0j4MUGV875JYPZ9v0eQz76qVbK+yux2RnQQuWiuNChNZKUgSQ3DSVcI/WKSlZHowLFl0H6M3oa7DRH2djQtriaKzyfMR24lH1NqugOwmOjCffw7LWHVRsGtL0lcFZuU3y2jKnIonvw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447254789579.2018863002734; Fri, 17 Apr 2026 10:34:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn30-0007He-Ci; Fri, 17 Apr 2026 13:32:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2i-0006v4-Im for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:54 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2d-0002L5-6a for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:46 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-43d7605ec91so794039f8f.3 for ; Fri, 17 Apr 2026 10:31:42 -0700 (PDT) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e4ffa8sm5819650f8f.35.2026.04.17.10.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 10:31:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1776447102; x=1777051902; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q1XLnzDD++kcgvvN+mJ7kGySfBQkB+0ZpLjBuZfsQOc=; b=nd3kD9WYhfSwEHrxEgF8A2n9dTYsOl8zZRb3zMzBON8DT1cgJvbydfcyPWNEeXI/OY vnT3OHyhcULRGvNuDMQDsZ8fUNevFsS7MOzqGF/EX4jKz1MORgp/mIt0uvWf9Np2N7hi AkQ7vLMi5FXSPCTuh+iTFBhi86r7QZOJz9Gz1zlELASMdyaxGKzW6VmHOlnZdaby18AI su4rELSc+g+HaEyLgIVPaZE0ixZQOxt2jeWazpYqMIZXO10c42hMFCSprZHdbammcub3 /Z+HelNM8FMYwYQnsp5vIWgb4HwQTEurX4YOlKVll3r/Oz3tp+U4Om30GviMLfT/E1Yc woPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776447102; x=1777051902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=q1XLnzDD++kcgvvN+mJ7kGySfBQkB+0ZpLjBuZfsQOc=; b=fng7SW5S8RtYzkcBSoTM9gWx2awGZJi3kHYgJ21y5fXe1pk1dyj6lAfDZm/zVI73LS 6FmCka3kI5ud23S55bTbl68iQgMZ0Dr3LKwdBGfxI7jmuqJ6b4L4zEp/kBtpVP2wIXry slIpnUtFDbIBpN80DD1tM6mJupGbLhmx4mMQpM3R1qu87sBjvKRLKZjMdcSJTtq0C855 Lte6JeHg2qsL3Ov3GK9+5lQsiYChYR9vjxXbxGpDzuTRblJcH0CZRLv7+2lHA1iUcaLB jDobB3/rT76+Yy7IiYp+cOz9byiGzdYyQFjgqroKsUw3aCacE+lGvfIRY4BDrYaqBRtN fGnw== X-Forwarded-Encrypted: i=1; AFNElJ+lWllCAHqZ+GuKRyPD+TwfyVANz9jhEYcD6lNLC1t6g5PuQcaq/m/Ax26H2qBn6v/jCj8ifs7t6pOG@nongnu.org X-Gm-Message-State: AOJu0YzNaeTCE2S9mnjwscB09CHXqU4zDKeuu+6QIsiFSN6DI4gJw6hP pT363LMx3iDjUzWxGOiNfESfjQgkUvTOrPeq5SgElMkpbqbJpsehOEVkQcimPt/Cqnw= X-Gm-Gg: AeBDiesqSbB37MPHzNV4wIwVKiu5aaD7sfTK0NuwWE1uGE2LbCOSqAFiBd8YzEh9klZ yjnTS6i+u8Z1nAJMtY5/Pw43ySnQXHgNasCQonkZ6hNaSLEys0431Thkdv/RNm3TCEkj5DcBrP2 SbEYA+WpmPagI+yIRVg+XmyLShQYomFU46Sz/304+srWdBgh5WrYU5tCpu7Vx+lDa2cE8lHKIzi XpJivFG9Op9Zab0IRQMdLb+paLXBR4iACEBzj7N8Z1lngfTnypVGGzzjnLRYCQfuFJ40DYwPEI6 /mz3e4ylW1wNkkaEnXrY6eLRD4N2WgbvE699LlGSUkQ70wBs/JvymoVugfTflRMno0ZAPijWtSN sUbB0tOZNkBievpqP8APnju97P3tjGBi76PjjXPB1VP8M+nNIq6qI+15K/Yc0nHlLFfZMOSnxxP lGCVVgOgchbHuupjn9hBxen8kyb59HzwGJLyMRh6wxEv8Dyl7GOJP4drTv7W2LfW+gnb81VlSFg zi42W2Sx1z4fsMNERlEAokf5ngR77b2EXCp1b8kjQ== X-Received: by 2002:a05:6000:25c7:b0:43d:71b:204b with SMTP id ffacd0b85a97d-43fe3e1433emr6138994f8f.39.1776447101514; Fri, 17 Apr 2026 10:31:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Paolo Bonzini , Richard Henderson , "Dr. David Alan Gilbert" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour , Peter Xu , "Edgar E. Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 14/17] hw/core: Implement new cpu_translate_for_debug() Date: Fri, 17 Apr 2026 18:31:02 +0100 Message-ID: <20260417173105.1648172-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447256747158500 Content-Type: text/plain; charset="utf-8" In cpu_memory_rw_debug() we need to do a virtual-to-physical address translation for debug access. Currently we assume that the translation is valid for an entire guest page, but this may not be true if the target implements some protection regions that have sub-page granularity. (Currently the only such target is the Arm CPUs when using an MPU, as in R-profile and M-profile.) For TCG's emulated accesses, we handle sub-page granularity by the CPU filling in the lg_page_size field of the CPUTLBEntryFull struct to tell us how large the region covered by the result is. But we didn't extend this to the debug-access code path, with the result that debug accesses might incorrectly fail because they are looking at the mapping for the address rounded down to a page boundary. Provide a cpu_translate_for_debug() function which reports to the caller not just the physical address and attributes of the translation but also the lg_page_size for which it is valid. The fallback implementation calls cpu_get_phys_addr_attrs_debug() and assumes target-page-sized validity. NB: the "return true on valid access, false on failure" follows the same convention as TCGCPUOps::tlb_fill_align() (though it is the opposite of what we use in some other places, e.g. in target/arm's get_phys_addr_* functions). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu-system.c | 32 ++++++++++++++++++++++++++++++++ include/hw/core/cpu.h | 32 ++++++++++++++++++++++++++++++++ include/hw/core/sysemu-cpu-ops.h | 27 +++++++++++++++++++++++++-- 3 files changed, 89 insertions(+), 2 deletions(-) diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 05c126ecb6..cab65d549a 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -22,6 +22,7 @@ #include "qapi/error.h" #include "system/address-spaces.h" #include "exec/cputlb.h" +#include "exec/target_page.h" #include "system/memory.h" #include "qemu/target-info.h" #include "hw/core/qdev.h" @@ -55,6 +56,37 @@ bool cpu_get_memory_mapping(CPUState *cpu, MemoryMapping= List *list, return false; } =20 +bool cpu_translate_for_debug(CPUState *cpu, vaddr addr, + TranslateForDebugResult *result) +{ + if (cpu->cc->sysemu_ops->translate_for_debug) { + return cpu->cc->sysemu_ops->translate_for_debug(cpu, addr, result); + } else { + /* Fallbacks for CPUs which don't implement translate_for_debug */ + if (cpu->cc->sysemu_ops->get_phys_addr_attrs_debug) { + result->physaddr =3D + cpu->cc->sysemu_ops->get_phys_addr_attrs_debug(cpu, addr, + &result->at= trs); + } else { + result->physaddr + =3D cpu->cc->sysemu_ops->get_phys_addr_debug(cpu, addr); + result->attrs =3D MEMTXATTRS_UNSPECIFIED; + } + if (result->physaddr =3D=3D -1) { + return false; + } + /* Indicate that this is a debug access. */ + result->attrs.debug =3D 1; + /* + * Assume memory access permissions are valid for the whole page. + * Targets where this isn't true should implement the + * translate_for_debug method. + */ + result->lg_page_size =3D TARGET_PAGE_SIZE; + return true; + } +} + hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs) { diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 0941757c55..084d691e6c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -778,6 +778,38 @@ hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, va= ddr addr, */ hwaddr cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); =20 +/** + * TranslateForDebugResult: gives result of cpu_translate_for_debug() + * + * @physaddr: the physical address corresponding to the virtual address + * @attrs: the transaction attributes for this access + * @lg_page_size: log2 of the size of the aligned block of memory + * that this physaddr and attrs are valid for. + */ +typedef struct TranslateForDebugResult { + hwaddr physaddr; + MemTxAttrs attrs; + uint8_t lg_page_size; +} TranslateForDebugResult; + +/** + * cpu_translate_for_debug: + * @cpu: The CPU use for the virtual-to-physical translation + * @addr: The virtual address + * @result: Struct filled in with results of translation + * + * Perform a virtual-to-physical address translation for debug accesses. + * Use it only for debugging because no protection checks are done. + * + * The address need not be page-aligned; the returned address in @result + * will be the physical address corresponding to that virtual address. + * + * Returns: false on translation failure; true on successful translation + * and fills in the fields of @result. + */ +bool cpu_translate_for_debug(CPUState *cpu, vaddr addr, + TranslateForDebugResult *result); + /** cpu_asidx_from_attrs: * @cpu: CPU * @attrs: memory transaction attributes diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index a87c55d922..8625ebb564 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -33,19 +33,42 @@ typedef struct SysemuCPUOps { * @get_phys_addr_debug: Callback for obtaining a physical address. * This must be able to handle a non-page-aligned address, and will * return the physical address corresponding to that address. + * + * CPUs should prefer to implement translate_for_debug instead of + * this (and must do so if their translations are not always valid + * for a complete target page or they use memory attributes). */ hwaddr (*get_phys_addr_debug)(CPUState *cpu, vaddr addr); /** * @get_phys_addr_attrs_debug: Callback for obtaining a physical addre= ss * and the associated memory transaction attributes to use for t= he * access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_addr_debug. + * * This must be able to handle a non-page-aligned address, and will * return the physical address corresponding to that address. + * + * CPUs should prefer to implement translate_for_debug instead of + * this (and must do so if their translations are not always valid + * for a complete target page). */ hwaddr (*get_phys_addr_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); + /** + * @translate_for_debug: Callback for translating a virtual address in= to + * a physical address for debug purposes. + * The implementation should fill in @result with the physical address, + * transaction attributes, and log2 of the size of the aligned block of + * memory that the translation is valid for. + * This must be able to handle a non-page-aligned address, and will + * return the physical address corresponding to that address. + * The attributes must include the debug flag being set. + * Returns false on translation failure; on success returns true and + * fills in @result. + * + * This is the preferred method to implement for new CPUs. + */ + bool (*translate_for_debug)(CPUState *cpu, vaddr addr, + TranslateForDebugResult *result); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447350; cv=none; d=zohomail.com; s=zohoarc; b=SPQA7VYUcCjbpKXBH6DAPQ+QfI07IO07QIf8orKX0lpNYbUO/jpGRiuTLYQtacneC/Om80Gc9PDNAMKQ08qED6Dt3flDLwi3Imk6Fyy3a3GEpO/evIPb9Jg25qX7z627bkayaCxE68v7TJSTtqbU1OoVgu6eBoJ2btgF/xAHc9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e4ffa8sm5819650f8f.35.2026.04.17.10.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 10:31:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1776447103; x=1777051903; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mjdw55nvUmDEoZC6Zfcjvd3ZPIFn9XfgQXXNer13HYA=; b=sz3z9UdOQD5jqbwweL59/qtGEIowTsxd5PXnzmESRR6dZGdszmFLUByU5JWPh1aEkJ 8Kc2ok2qflCZkJC/eYGhYSZanS+aa48ayJSVbjYE5lM7xeUJxTnTLRIGaT5DgrnG4FKj b5tzB9G6+lSA8Y0VLxI2PRxHduTCjUJ0IiOHAV25ettwt/pkIa4uYD+JLkipSWlqYzv1 wWRY8BuHSZlT7huvziV9buSX3b8rfP9enFLVAIuZzlVRonOAy6jRfx+RNHm8HZsSEJ5C o1/GdwVQZ9So9eLsyzDROhwHtkeaHnn4dKAqyV7MUQA75cShJ/MMGOHDsWJLfOT7bRiq S2Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776447103; x=1777051903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Mjdw55nvUmDEoZC6Zfcjvd3ZPIFn9XfgQXXNer13HYA=; b=jZ1ZQ5kLOJlY/3AnFZcPba+nirvqgCR3iRgddUKsVkhFY5jRjbek3DwA+QnQqTCFU8 NnbCOWeF9RIxLX9kOrz0IIiga/5cxOCspvhRJ9AUFOSb903Ci/nOzhOWW/gkOKGHSA05 Snv48vjhNZx8dV38p/YQ4VsHDkW53Lje2pkfqZj57YmzN9fv0zhtnAgxlcUvd5JdHPji tU9X9ExcUg5C9nZ7AqfoSrTi8BEq1/zWKRdDMXrmyDkSLMasS5dygnULfJW37B9wawTs J7P8Q7G+55fBF1AVXsPG06fQ++S2hDJLjgxDuQVGW3kWSXPplkL+7EHgEXs95jDLus3e 02mQ== X-Forwarded-Encrypted: i=1; AFNElJ8njdpPZh/LIhEGlesz9+OxNZkGIt2//Cl2dmgxjxl9mWuqPmBzX6EUW4t8JQIGD7jKX64a9Hh+tCkw@nongnu.org X-Gm-Message-State: AOJu0YyJUfp+UrBt87jjfoKblG1+Mys7uF+oIbh68+cfHd2n2Szxs9gz /fNnwH1yC2g/Mo2yK25o4QuaVKcJkk3+iFvhVEQTMiwEjVJObaY8T+/XGNvCVKqnTZM= X-Gm-Gg: AeBDiesqiHyE7FuCrVt6bcGwFJUjwbZVXF2EiW/NG+4l+7Vb91XvJ/KFMGkIHwbxPOn UPsHato8+h9ruTO7P2usXs/YMBn5HiEfO3q1K2gqUtVPRNMMvSjKGSCPbiy9ak4h4+oiC4fn1py RwMqZP4OL1DLnkg5Zxq37Q+155xxtOPcAFOEgoZSSyzok/wIEIygrf69XNJ6h134v1M9LbRhUCT WgMVM4iyrRkFcgbAOrzdw/7sSDCqH3fHVdc0zQOxlYDnzs0nleAlWjXvytA5O1gtL768Azl1q4F piFVIJKDyESHPvQRgWX3l080bEno8FDLzorauVM+sTKnn9jrx3csUgPnopRlQN/GPHVnS1Llhlu CldxG7pSS0f0BW+SjJyHrzjbH9taxJo9BRQHsBh7idtKDthd8W2wtQyISVCzizSpudD3L/VhQeX 9CkHKcNb53BRdome68tl0/HUpqYJGngw4EeeesMniLWwloxhk0aeJGeQ4PS/uRR+MQ8SSxMBarI 6l5K1eyz8DapxX1Q1e5ETX4BJIJ2EKmyXLjlUkRFg== X-Received: by 2002:a5d:584c:0:b0:43d:7403:4b57 with SMTP id ffacd0b85a97d-43fe3db3ca7mr5903786f8f.10.1776447103468; Fri, 17 Apr 2026 10:31:43 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Yanan Wang , Zhao Liu , Paolo Bonzini , Richard Henderson , "Dr. David Alan Gilbert" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour , Peter Xu , "Edgar E. Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 15/17] hw/core: Implement cpu_get_phys_addr_attrs_debug() with cpu_translate_for_debug() Date: Fri, 17 Apr 2026 18:31:03 +0100 Message-ID: <20260417173105.1648172-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447352582154100 Content-Type: text/plain; charset="utf-8" Implement cpu_get_phys_addr_attrs_debug() with cpu_translate_for_debug(), so that CPUs can implement only the translate_for_debug method and have all of the wrapper functions cpu_translate_for_debug(), cpu_get_phys_addr_attrs_debug() and cpu_get_phys_addr_debug() work. Signed-off-by: Peter Maydell --- hw/core/cpu-system.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index cab65d549a..be5cb48126 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -90,19 +90,14 @@ bool cpu_translate_for_debug(CPUState *cpu, vaddr addr, hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs) { - hwaddr paddr; + TranslateForDebugResult result; =20 - if (cpu->cc->sysemu_ops->get_phys_addr_attrs_debug) { - paddr =3D cpu->cc->sysemu_ops->get_phys_addr_attrs_debug(cpu, addr, - attrs); - } else { - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - paddr =3D cpu->cc->sysemu_ops->get_phys_addr_debug(cpu, addr); + if (!cpu_translate_for_debug(cpu, addr, &result)) { + return -1; } - /* Indicate that this is a debug access. */ - attrs->debug =3D 1; - return paddr; + + *attrs =3D result.attrs; + return result.physaddr; } =20 hwaddr cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr) --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447373; cv=none; d=zohomail.com; s=zohoarc; b=csRMA4SKJX2XinwTlMxeXFb+5HdKx0v8U4jDmxYCKcmEEbPbwh49WGL1J17brE6p6YjJz0dyE9zgBwnp8cmW+/kKFRv1UZ2H7NmlW2CO7fLtRdO8VgDeEzXWLYC+GTrzFu80xrmqH8Xk0u8Cjop2LagJ29cqkHAl+5J0Css/09g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776447373; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wxY3ZiluRC3qmS1pGuPIEiJq7+uwFw+8gR7Q01pS8h0=; b=WZA0laksTsVJDAgqHzovBeQM8IjnGOGI0XmpV1WsEP70ImsK6lSqGU6FZgx/clhqtcFOwVsBKSh3Op2/01kDF3w4ftgqF8uEj2GfMQW1213RHS03WhcHrzdJJHtdCoJ5mjEHZ25VXR4foohLXwx+MDbsDQdyBQ75RwuqDtKCSdY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776447373643924.442226105391; Fri, 17 Apr 2026 10:36:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDn35-0007MA-1w; Fri, 17 Apr 2026 13:32:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDn2l-0006vV-P4 for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:56 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDn2i-0002P2-A4 for qemu-devel@nongnu.org; Fri, 17 Apr 2026 13:31:51 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-43d77f60944so688538f8f.3 for ; Fri, 17 Apr 2026 10:31:46 -0700 (PDT) Received: from lanath.. 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 16/17] target/arm: Implement translate_for_debug Date: Fri, 17 Apr 2026 18:31:04 +0100 Message-ID: <20260417173105.1648172-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447375287158500 Content-Type: text/plain; charset="utf-8" Implement the translate_for_debug method instead of the get_phys_addr_attrs_debug one. This allows us to pass the caller the lg_page_size from our internal GetPhysAddrResult struct. Awkwardly, translate_for_debug's "true on success" convention is the opposite of the one we use internally in ptw.c, so we have to be careful about the sense of the return values. This corresponds to the way that arm_cpu_tlb_fill_align() also has to return true when get_phys_addr() returns false. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 2 +- target/arm/cpu.h | 3 --- target/arm/internals.h | 4 ++++ target/arm/ptw.c | 37 ++++++++++++++++++++++--------------- 4 files changed, 27 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f28c74a94b..c014375cb7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2295,7 +2295,7 @@ static vaddr aarch64_untagged_addr(CPUState *cs, vadd= r x) =20 static const struct SysemuCPUOps arm_sysemu_ops =3D { .has_work =3D arm_cpu_has_work, - .get_phys_addr_attrs_debug =3D arm_cpu_get_phys_addr_attrs_debug, + .translate_for_debug =3D arm_cpu_translate_for_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 917e4668da..ea3c65ba1a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1231,9 +1231,6 @@ extern const VMStateDescription vmstate_arm_cpu; void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); =20 -hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); - typedef struct ARMGranuleProtectionConfig { /* GPCCR_EL3 */ uint64_t gpccr; diff --git a/target/arm/internals.h b/target/arm/internals.h index 85980f0e69..5527c004db 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1532,6 +1532,10 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, =20 void arm_log_exception(CPUState *cs); =20 +/* Implementation of SysemuCPUOps::translate_for_debug */ +bool arm_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result); + #endif /* !CONFIG_USER_ONLY */ =20 /* diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8be6f243e6..ae4089a14c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3922,8 +3922,9 @@ bool get_phys_addr(CPUARMState *env, vaddr address, memop, result, fi); } =20 -static hwaddr arm_cpu_get_phys_addr(CPUARMState *env, vaddr addr, - MemTxAttrs *attrs, ARMMMUIdx mmu_idx) +static bool arm_cpu_get_phys_addr(CPUARMState *env, vaddr addr, + TranslateForDebugResult *result, + ARMMMUIdx mmu_idx) { S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, @@ -3935,25 +3936,30 @@ static hwaddr arm_cpu_get_phys_addr(CPUARMState *en= v, vaddr addr, GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; bool ret =3D get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, 0, &res= , &fi); - *attrs =3D res.f.attrs; =20 - if (ret) { - return -1; + if (!ret) { + /* translation succeeded */ + result->physaddr =3D res.f.phys_addr; + result->attrs =3D res.f.attrs; + result->lg_page_size =3D res.f.lg_page_size; } - return res.f.phys_addr; + return ret; } =20 -hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *cs, vaddr addr, - MemTxAttrs *attrs) +bool arm_cpu_translate_for_debug(CPUState *cs, vaddr addr, + TranslateForDebugResult *result) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); =20 - hwaddr res =3D arm_cpu_get_phys_addr(env, addr, attrs, mmu_idx); - - if (res !=3D -1) { - return res; + /* + * Note that this function returns true on translation success, + * but arm_cpu_get_phys_addr() and all the other get_phys_addr + * style functions in this file return true on failure. + */ + if (!arm_cpu_get_phys_addr(env, addr, result, mmu_idx)) { + return true; } =20 /* @@ -3964,11 +3970,12 @@ hwaddr arm_cpu_get_phys_addr_attrs_debug(CPUState *= cs, vaddr addr, switch (mmu_idx) { case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: - return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E10_0); + return !arm_cpu_get_phys_addr(env, addr, result, ARMMMUIdx_E10_0); case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: - return arm_cpu_get_phys_addr(env, addr, attrs, ARMMMUIdx_E20_0); + return !arm_cpu_get_phys_addr(env, addr, result, ARMMMUIdx_E20_0); default: - return -1; + /* translation failed */ + return false; } } --=20 2.43.0 From nobody Tue Apr 21 14:38:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776447285; cv=none; d=zohomail.com; s=zohoarc; b=CWO7o0OanoOOZs703PR+FO6aCgjl+N/wKlxLHPau8Azjr/I3pV6kYbOiYNWiZ6AHQhN3AeyTFjf2O93/T4/9+GZkuF9W1wx7/Wz/vmVbEzVEczZ3A8wkjKZHyyA1wKgO/W61TRiEuWMu6vAo/UJ7GTt9cUmU3x/yTTuLQ3VdQT0= ARC-Message-Signature: i=1; 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Iglesias" , Jiaxun Yang , Nicholas Piggin , Chinmay Rath , Glenn Miles , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 17/17] system/physmem: Use translate_for_debug() in cpu_memory_rw_debug() Date: Fri, 17 Apr 2026 18:31:05 +0100 Message-ID: <20260417173105.1648172-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417173105.1648172-1-peter.maydell@linaro.org> References: <20260417173105.1648172-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776447287640154100 Content-Type: text/plain; charset="utf-8" Currently cpu_memory_rw_debug() assumes page-granularity for translations, and it works in a loop where each iteration translates for the vaddr rounded down to a page boundary and then copies up to the end of the page boundary. Rewrite it to use the new cpu_translate_for_debug(): we no longer want to round down the input address, and the boundary we copy up to is now determined by the lg_page_size it returns rather than being assumed to be page-sized. This, together with the implementation of translate_for_debug for Arm targets, fixes the bug where semihosting would incorrectly fail to access parameter blocks that were in memory where the start of the 4K region they were in was inaccessible due to MPU region settings, even if the parameter block itself was readable. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3292 Signed-off-by: Peter Maydell --- system/physmem.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/system/physmem.c b/system/physmem.c index f2d9a4ff8f..45c3a926cf 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -4036,28 +4036,38 @@ address_space_write_cached_slow(MemoryRegionCache *= cache, hwaddr addr, int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, void *ptr, size_t len, bool is_write) { - hwaddr phys_addr; - vaddr l, page; uint8_t *buf =3D ptr; =20 cpu_synchronize_state(cpu); while (len > 0) { int asidx; - MemTxAttrs attrs; + TranslateForDebugResult tres; MemTxResult res; + hwaddr blk_base, blk_size, l; =20 - page =3D addr & TARGET_PAGE_MASK; - phys_addr =3D cpu_get_phys_addr_attrs_debug(cpu, page, &attrs); - asidx =3D cpu_asidx_from_attrs(cpu, attrs); - /* if no physical page mapped, return an error */ - if (phys_addr =3D=3D -1) + if (!cpu_translate_for_debug(cpu, addr, &tres)) { + /* Return error if no physical page mapped */ return -1; - l =3D (page + TARGET_PAGE_SIZE) - addr; - if (l > len) - l =3D len; - phys_addr +=3D (addr & ~TARGET_PAGE_MASK); - res =3D address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, attrs= , buf, - l, is_write); + } + asidx =3D cpu_asidx_from_attrs(cpu, tres.attrs); + /* + * Clamp the amount we read to not go beyond a page even if + * the CPU returned a larger lg_page_size, in case this access + * is to a memory-mapped IO region. + */ + tres.lg_page_size =3D MIN(tres.lg_page_size, TARGET_PAGE_BITS); + /* + * Find the length in bytes from tres.physaddr to the end of the + * block whose size is 1 << tres.lg_page_size; we will access + * that much in one go. + */ + blk_size =3D 1ULL << tres.lg_page_size; + blk_base =3D ROUND_DOWN(tres.physaddr, blk_size); + l =3D blk_base + blk_size - tres.physaddr; + l =3D MIN(l, len); + + res =3D address_space_rw(cpu->cpu_ases[asidx].as, tres.physaddr, + tres.attrs, buf, l, is_write); if (res !=3D MEMTX_OK) { return -1; } --=20 2.43.0