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b=uBBE5XxeTg7ErMelq/W5O6FyqP/GNkl/xHcYP0RyHkKg08bGyv3y7JpmXS1XUkNXqfP9YRxbOC4wFySV+J2IHq8SNpcjgSTtGtX6LriKxENRQpwgUVQJVsMNLVebwUMXO/MQO9LcFarhozGeprulz8EimodHJT+rApK1e9pyvbJYYydMUEA9Ko9c9UkoIaIfCFVBNWECSP+tCuQRqOxJftckym8kPg8wCDGLPeWs4XqwuzA4YdwUgGSrNNISoixSd47U73RW/W7kS6WK0yyoshUp7pJuYWe4HEDNmF0UaEBdGnItvTlzXM2HH/xCehQluXu/DoX5RblbK6o7/FzCAw== From: Djordje Todorovic To: "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , "alistair23@gmail.com" , "thuth@redhat.com" , Djordje Todorovic , Alistair Francis Subject: [PATCH v7 1/6] target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks Thread-Topic: [PATCH v7 1/6] target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks Thread-Index: AQHczlFlmldkxMXfFUSHMi8S6Z7mEA== Date: Fri, 17 Apr 2026 10:03:09 +0000 Message-ID: <20260417100302.162260-2-djordje.todorovic@htecgroup.com> References: <20260417100302.162260-1-djordje.todorovic@htecgroup.com> In-Reply-To: <20260417100302.162260-1-djordje.todorovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; 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envelope-from=Djordje.Todorovic@htecgroup.com; helo=DB3PR0202CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1776420222391154100 Add the RISC-V privileged ISA defined bit positions for the Supervisor Big-Endian (SBE, bit 36) and Machine Big-Endian (MBE, bit 37) fields in the mstatus register. These are used alongside the existing MSTATUS_UBE (bit 6) to control data endianness at each privilege level. The MSTATUS_UBE definition was already present, but SBE and MBE were missing. Signed-off-by: Djordje Todorovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7..c2a3ee4bf3 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -628,6 +628,8 @@ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ #define MSTATUS_SPELP 0x00800000 /* zicfilp */ #define MSTATUS_SDT 0x01000000 +#define MSTATUS_SBE 0x1000000000ULL +#define MSTATUS_MBE 0x2000000000ULL #define MSTATUS_MPELP 0x020000000000 /* zicfilp */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL --=20 2.34.1 From nobody Sat May 30 20:13:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=htecgroup.com); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c200::1; envelope-from=Djordje.Todorovic@htecgroup.com; helo=DB3PR0202CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1776420234853154100 Content-Type: text/plain; charset="utf-8" Add a "big-endian" boolean property to the RISC-V CPU configuration, defaulting to false (little-endian). When enabled, this models a big-endian-only RISC-V implementation as described in section 3.1.6.5 of the RISC-V Privileged Specification ("Memory Endianness"), where the MSTATUS MBE/SBE/UBE bits are hardwired to 1. This is a static, per-CPU hardware configuration option, not a runtime switch. It is intended for modeling RISC-V CPU variants whose data endianness is fixed to big-endian at the hardware level. Instructions remain little-endian regardless, per the RISC-V ISA specification. When cfg.big_endian is set, riscv_cpu_reset_hold() writes 1 into the MSTATUS UBE/SBE/MBE fields; otherwise it writes 0. The assignment is done with set_field() so the reset value is deterministic on both cold and warm reset, rather than depending on the pre-reset state. The MBE/SBE/UBE bits are not included in the writable mask of any mstatus/mstatush/sstatus CSR write path, so the value chosen at reset effectively hardwires them. The actual effect of those bits on data accesses, page-table walks and boot code is implemented by the subsequent patches in this series. Also update the disassembler comment to clarify that BFD_ENDIAN_LITTLE is correct because RISC-V instructions are always little-endian per the ISA specification. No upstream CPU currently defaults to big-endian; the property can be enabled from the command line, e.g.: -cpu ,big-endian=3Don Signed-off-by: Djordje Todorovic Reviewed-by: Chao Liu --- docs/system/target-riscv.rst | 24 ++++++++++++++++++++++++ target/riscv/cpu.c | 11 ++++++----- target/riscv/cpu_cfg_fields.h.inc | 1 + 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 3ad5d1ddaf..7798184ebe 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -95,3 +95,27 @@ the images they need. * ``-bios `` =20 Tells QEMU to load the specified file as the firmware. + +RISC-V CPU endianness +--------------------- + +The RISC-V ISA specifies that instruction fetches are always little-endian, +while data accesses can be either little-endian or big-endian under control +of the MSTATUS ``MBE``/``SBE``/``UBE`` bits (see section 3.1.6.5, "Memory +Endianness", in the RISC-V Privileged Specification). + +QEMU implements the full data-endianness behaviour described by those bits. +In addition, the RISC-V CPU object exposes a ``big-endian`` boolean proper= ty +which models a big-endian-only hardware implementation, where the +``MBE``/``SBE``/``UBE`` bits are hardwired to 1. When the property is set, +the CPU is reset with all three bits initialised to 1, so the guest starts +executing in big-endian data mode from the reset vector. The property is a +static, per-CPU hardware configuration option and is not meant to be toggl= ed +at runtime. + +The property can be enabled from the command line, for example:: + + -cpu ,big-endian=3Don + +No upstream CPU model currently defaults to big-endian; the property is +provided so that big-endian-only RISC-V CPU variants can be modelled. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e56470a374..c39500cb3f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -716,6 +716,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType= type) env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 1); } } + env->mstatus =3D set_field(env->mstatus, MSTATUS_MBE, cpu->cfg.big_end= ian); + env->mstatus =3D set_field(env->mstatus, MSTATUS_SBE, cpu->cfg.big_end= ian); + env->mstatus =3D set_field(env->mstatus, MSTATUS_UBE, cpu->cfg.big_end= ian); env->mcause =3D 0; env->miclaim =3D MIP_SGEIP; env->pc =3D env->resetvec; @@ -803,11 +806,8 @@ static void riscv_cpu_disas_set_info(const CPUState *s= , disassemble_info *info) info->target_info =3D &cpu->cfg; =20 /* - * A couple of bits in MSTATUS set the endianness: - * - MSTATUS_UBE (User-mode), - * - MSTATUS_SBE (Supervisor-mode), - * - MSTATUS_MBE (Machine-mode) - * but we don't implement that yet. + * RISC-V instructions are always little-endian, regardless of the + * data endianness configured via MSTATUS UBE/SBE/MBE bits. */ info->endian =3D BFD_ENDIAN_LITTLE; =20 @@ -2641,6 +2641,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { =20 static const Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + DEFINE_PROP_BOOL("big-endian", RISCVCPU, cfg.big_endian, false), =20 {.name =3D "pmu-mask", .info =3D &prop_pmu_mask}, {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 70ec650abf..51436daabf 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -154,6 +154,7 @@ BOOL_FIELD(ext_xmipscbop) BOOL_FIELD(ext_xmipscmov) BOOL_FIELD(ext_xmipslsp) =20 +BOOL_FIELD(big_endian) BOOL_FIELD(mmu) BOOL_FIELD(pmp) BOOL_FIELD(debug) --=20 2.34.1 From nobody Sat May 30 20:13:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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b=nahxjx57r94U5ByrJxvxe4chcrrhdJ6ERW9VywMs+m096Fe318pcjhnCmWjiszEvFQi+oail+OSRtVo7Mt/rwtwNr8/VxT+GtUvd2c+FSly8EolWAxXR0M4jWxAWmmLRbgNPetnO3L+ojpQ0GciE58Ta6Lr0LqgJlF/ROh+P87gaYmfCs3V8f1zpUdJck2H8wx35teKOJUeLzEBsW30P8uep2HnxDPrAR7htwf3b6pFmnZ+Wvg9IjZZu9V5DA+g7LJTqIyLd8FYtk5PPLvIdVwATnsEIPoCdDgaDq2DlQtjEhhua+6iPt3bfABpgkw02LakLRCte5DmqugLwdaRSnA== From: Djordje Todorovic To: "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , "alistair23@gmail.com" , "thuth@redhat.com" , Djordje Todorovic Subject: [PATCH v7 3/6] target/riscv: Implement runtime data endianness via MSTATUS bits Thread-Topic: [PATCH v7 3/6] target/riscv: Implement runtime data endianness via MSTATUS bits Thread-Index: AQHczlFlihUusYngh02OWnt1bDc+5A== Date: Fri, 17 Apr 2026 10:03:11 +0000 Message-ID: <20260417100302.162260-4-djordje.todorovic@htecgroup.com> References: <20260417100302.162260-1-djordje.todorovic@htecgroup.com> In-Reply-To: <20260417100302.162260-1-djordje.todorovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c200::1; envelope-from=Djordje.Todorovic@htecgroup.com; helo=DB3PR0202CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1776420273323154100 Content-Type: text/plain; charset="utf-8" Make data accesses honour the MSTATUS MBE/SBE/UBE endianness bits instead of being hardcoded to little-endian. A new helper, riscv_cpu_data_is_big_endian(), picks the bit corresponding to the current privilege level (MBE for M, SBE for S, UBE for U). The existing mo_endian_env() wrapper in internals.h now returns MO_BE or MO_LE based on that helper, so the hypervisor load/store helpers in op_helper.c pick up the runtime endianness automatically. On the translator side, DisasContext gains a mo_endianness field holding MO_BE or MO_LE, which the generated load/store ops OR into their MemOp. The trivial mo_endian() wrapper is dropped and call sites reference ctx->mo_endianness directly. TB_FLAGS has no free bits, so the endianness is carried into the translator through bit 32 of cs_base (alongside misa_ext in bits 0-25). This keys TBs correctly on the current data endianness. The cs_base comment in include/exec/translation-block.h is updated to document the RISC-V usage. Instruction fetches remain MO_LE unconditionally; RISC-V instructions are always little-endian per the ISA specification. Signed-off-by: Djordje Todorovic --- include/exec/translation-block.h | 3 +- target/riscv/cpu.h | 28 +++++++++++++++++++ target/riscv/insn_trans/trans_rva.c.inc | 4 +-- target/riscv/insn_trans/trans_rvd.c.inc | 4 +-- target/riscv/insn_trans/trans_rvf.c.inc | 4 +-- target/riscv/insn_trans/trans_rvi.c.inc | 8 +++--- target/riscv/insn_trans/trans_rvzacas.c.inc | 4 +-- target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 +-- target/riscv/insn_trans/trans_rvzce.c.inc | 4 +-- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +-- target/riscv/insn_trans/trans_rvzicfiss.c.inc | 4 +-- target/riscv/insn_trans/trans_xmips.c.inc | 8 +++--- target/riscv/insn_trans/trans_xthead.c.inc | 16 +++++------ target/riscv/insn_trans/trans_zilsd.c.inc | 4 +-- target/riscv/internals.h | 9 +----- target/riscv/tcg/tcg-cpu.c | 7 ++++- target/riscv/translate.c | 22 +++++---------- 17 files changed, 78 insertions(+), 59 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 4f83d5bec9..66068c61a3 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -64,7 +64,8 @@ struct TranslationBlock { * x86: the original user, the Code Segment virtual base, * arm: an extension of tb->flags, * s390x: instruction data for EXECUTE, - * sparc: the next pc of the instruction queue (for delay slots). + * sparc: the next pc of the instruction queue (for delay slots), + * riscv: misa_ext in bits 0-25, data endianness in bit 32. */ uint64_t cs_base; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35d1f6362c..ef870d05b3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -703,6 +703,12 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) =20 +/* + * cs_base carries misa_ext (bits 0-25) plus additional flags. + * Bit 32 is used for data endianness since TB_FLAGS has no free bits. + */ +#define TB_CSBASE_BIG_ENDIAN (1ULL << 32) + #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else @@ -718,6 +724,28 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPUR= ISCVState *env) return &env_archcpu(env)->cfg; } =20 +/* + * Return true if data accesses are big-endian for the current privilege + * level, based on the MSTATUS MBE/SBE/UBE bits. + */ +static inline bool riscv_cpu_data_is_big_endian(CPURISCVState *env) +{ +#if defined(CONFIG_USER_ONLY) + return false; +#else + switch (env->priv) { + case PRV_M: + return env->mstatus & MSTATUS_MBE; + case PRV_S: + return env->mstatus & MSTATUS_SBE; + case PRV_U: + return env->mstatus & MSTATUS_UBE; + default: + g_assert_not_reached(); + } +#endif +} + #if !defined(CONFIG_USER_ONLY) static inline int cpu_address_mode(CPURISCVState *env) { diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index a7a3278d24..6597ae8bb7 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -35,7 +35,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGv src1; =20 mop |=3D MO_ALIGN; - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; =20 decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); @@ -65,7 +65,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) TCGLabel *l2 =3D gen_new_label(); =20 mop |=3D MO_ALIGN; - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; =20 decode_save_opc(ctx, 0); src1 =3D get_address(ctx, a->rs1, 0); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index ffea0c2a1f..3b9a745520 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -60,7 +60,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) } else { memop |=3D MO_ATOM_IFALIGN; } - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); @@ -85,7 +85,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) } else { memop |=3D MO_ATOM_IFALIGN; } - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; =20 decode_save_opc(ctx, 0); addr =3D get_address(ctx, a->rs1, a->imm); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 89fb0f604a..e935523c93 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -71,7 +71,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 2c82ae41a7..2de74fac3a 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -392,7 +392,7 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a,= MemOp memop) } } else { tcg_gen_qemu_ld_i128(t16, addrl, ctx->mem_idx, memop); - if (mo_endian(ctx) =3D=3D MO_LE) { + if (ctx->mo_endianness =3D=3D MO_LE) { tcg_gen_extr_i128_i64(tl, th, t16); } else { tcg_gen_extr_i128_i64(th, tl, t16); @@ -409,7 +409,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemO= p memop) { bool out; =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } @@ -508,7 +508,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) tcg_gen_ext_tl_i64(tl, src2l); tcg_gen_ext_tl_i64(th, src2h); =20 - if (mo_endian(ctx) =3D=3D MO_LE) { + if (ctx->mo_endianness =3D=3D MO_LE) { tcg_gen_concat_i64_i128(t16, tl, th); } else { tcg_gen_concat_i64_i128(t16, th, tl); @@ -520,7 +520,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) =20 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b) { memop |=3D MO_ATOM_WITHIN16; } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/ins= n_trans/trans_rvzacas.c.inc index 8d94b83ce9..79bca1e957 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -76,7 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *= a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv_i64 src2 =3D get_gpr_pair(ctx, a->rs2); =20 - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop); =20 @@ -121,7 +121,7 @@ static bool trans_amocas_q(DisasContext *ctx, arg_amoca= s_q *a) TCGv_i64 desth =3D get_gpr(ctx, a->rd =3D=3D 0 ? 0 : a->rd + 1, EXT_NO= NE); MemOp memop =3D MO_ALIGN | MO_UO; =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_concat_i64_i128(src2, src2l, src2h); tcg_gen_concat_i64_i128(dest, destl, desth); decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/in= sn_trans/trans_rvzalasr.c.inc index 0f307affec..79b0b2c63b 100644 --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc @@ -29,7 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aq= rl *a, MemOp memop) return false; } =20 - memop |=3D MO_ALIGN | mo_endian(ctx); + memop |=3D MO_ALIGN | ctx->mo_endianness; memop |=3D (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); @@ -79,7 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_a= qrl *a, MemOp memop) return false; } =20 - memop |=3D MO_ALIGN | mo_endian(ctx); + memop |=3D MO_ALIGN | ctx->mo_endianness; memop |=3D (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; =20 /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */ diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index 0d3ba40e52..71b4ca5473 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -185,7 +185,7 @@ static bool gen_pop(DisasContext *ctx, arg_cmpp *a, boo= l ret, bool ret_val) =20 tcg_gen_addi_tl(addr, sp, stack_adj - reg_size); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; for (i =3D X_Sn + 11; i >=3D 0; i--) { if (reg_bitmap & (1 << i)) { TCGv dest =3D dest_gpr(ctx, i); @@ -239,7 +239,7 @@ static bool trans_cm_push(DisasContext *ctx, arg_cm_pus= h *a) =20 tcg_gen_subi_tl(addr, sp, reg_size); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; for (i =3D X_Sn + 11; i >=3D 0; i--) { if (reg_bitmap & (1 << i)) { TCGv val =3D get_gpr(ctx, i, EXT_NONE); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 791ee51f65..f36b46c211 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -49,7 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -74,7 +74,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) REQUIRE_FPU; REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; decode_save_opc(ctx, 0); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/i= nsn_trans/trans_rvzicfiss.c.inc index 0b6ad57965..43f586dce9 100644 --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc @@ -105,7 +105,7 @@ static bool trans_ssamoswap_w(DisasContext *ctx, arg_am= oswap_w *a) decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; @@ -135,7 +135,7 @@ static bool trans_ssamoswap_d(DisasContext *ctx, arg_am= oswap_w *a) decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); src1 =3D get_address(ctx, a->rs1, 0); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), memop); gen_set_gpr(ctx, a->rd, dest); return true; diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_= trans/trans_xmips.c.inc index c1a30156d3..1b9993a9b0 100644 --- a/target/riscv/insn_trans/trans_xmips.c.inc +++ b/target/riscv/insn_trans/trans_xmips.c.inc @@ -47,7 +47,7 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a) /* Load Doubleword Pair. */ static bool trans_ldp(DisasContext *ctx, arg_ldp *a) { - MemOp memop =3D MO_SQ | mo_endian(ctx); + MemOp memop =3D MO_SQ | ctx->mo_endianness; =20 REQUIRE_XMIPSLSP(ctx); REQUIRE_64_OR_128BIT(ctx); @@ -71,7 +71,7 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a) /* Load Word Pair. */ static bool trans_lwp(DisasContext *ctx, arg_lwp *a) { - MemOp memop =3D MO_SL | mo_endian(ctx); + MemOp memop =3D MO_SL | ctx->mo_endianness; =20 REQUIRE_XMIPSLSP(ctx); =20 @@ -94,7 +94,7 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a) /* Store Doubleword Pair. */ static bool trans_sdp(DisasContext *ctx, arg_sdp *a) { - MemOp memop =3D MO_UQ | mo_endian(ctx); + MemOp memop =3D MO_UQ | ctx->mo_endianness; =20 REQUIRE_XMIPSLSP(ctx); REQUIRE_64_OR_128BIT(ctx); @@ -116,7 +116,7 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a) /* Store Word Pair. */ static bool trans_swp(DisasContext *ctx, arg_swp *a) { - MemOp memop =3D MO_SL | mo_endian(ctx); + MemOp memop =3D MO_SL | ctx->mo_endianness; =20 REQUIRE_XMIPSLSP(ctx); =20 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index f8b95c6498..f4e3051000 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -349,7 +349,7 @@ static bool gen_fload_idx(DisasContext *ctx, arg_th_mem= idx *a, MemOp memop, TCGv_i64 rd =3D cpu_fpr[a->rd]; TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); if ((memop & MO_SIZE) =3D=3D MO_32) { gen_nanbox_s(rd, rd); @@ -370,7 +370,7 @@ static bool gen_fstore_idx(DisasContext *ctx, arg_th_me= midx *a, MemOp memop, TCGv_i64 rd =3D cpu_fpr[a->rd]; TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); =20 return true; @@ -570,7 +570,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_memi= nc *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rd, rd); @@ -591,7 +591,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_mem= inc *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv rs1 =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rs1, rs1); @@ -747,7 +747,7 @@ static bool gen_load_idx(DisasContext *ctx, arg_th_memi= dx *a, MemOp memop, TCGv rd =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd, rd); =20 @@ -765,7 +765,7 @@ static bool gen_store_idx(DisasContext *ctx, arg_th_mem= idx *a, MemOp memop, TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zex= t_offs); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); =20 return true; @@ -926,7 +926,7 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_p= air *a, MemOp memop, addr1 =3D get_address(ctx, a->rs, imm); addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop); tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd1, t1); @@ -965,7 +965,7 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_= pair *a, MemOp memop, addr1 =3D get_address(ctx, a->rs, imm); addr2 =3D get_address(ctx, a->rs, memop_size(memop) + imm); =20 - memop |=3D mo_endian(ctx); + memop |=3D ctx->mo_endianness; tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); return true; diff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_= trans/trans_zilsd.c.inc index f50c52f22c..8068cc1aec 100644 --- a/target/riscv/insn_trans/trans_zilsd.c.inc +++ b/target/riscv/insn_trans/trans_zilsd.c.inc @@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a) TCGv addr =3D get_address(ctx, a->rs1, a->imm); TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx)); + tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_SQ | ctx->mo_endiannes= s); =20 if (a->rd =3D=3D 0) { return true; @@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a) } else { tcg_gen_concat_tl_i64(tmp, data_low, data_high); } - tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | mo_endian(ctx)); + tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_SQ | ctx->mo_endiannes= s); =20 return true; } diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 460346dd6d..e2f0334da8 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -64,14 +64,7 @@ static inline bool mmuidx_2stage(int mmu_idx) =20 static inline MemOp mo_endian_env(CPURISCVState *env) { - /* - * A couple of bits in MSTATUS set the endianness: - * - MSTATUS_UBE (User-mode), - * - MSTATUS_SBE (Supervisor-mode), - * - MSTATUS_MBE (Machine-mode) - * but we don't implement that yet. - */ - return MO_LE; + return riscv_cpu_data_is_big_endian(env) ? MO_BE : MO_LE; } =20 /* share data between vector helpers and decode code */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 3407191c22..d73b749bae 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -189,10 +189,15 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState = *cs) flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 + uint64_t cs_base =3D env->misa_ext; + if (riscv_cpu_data_is_big_endian(env)) { + cs_base |=3D TB_CSBASE_BIG_ENDIAN; + } + return (TCGTBCPUState){ .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, .flags =3D flags, - .cs_base =3D env->misa_ext, + .cs_base =3D cs_base, }; } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5df5b73849..9f538ba96d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -119,6 +119,8 @@ typedef struct DisasContext { bool fcfi_lp_expected; /* zicfiss extension, if shadow stack was enabled during TB gen */ bool bcfi_enabled; + /* Data endianness from MSTATUS UBE/SBE/MBE */ + MemOp mo_endianness; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -126,18 +128,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t= ext) return ctx->misa_ext & ext; } =20 -static inline MemOp mo_endian(DisasContext *ctx) -{ - /* - * A couple of bits in MSTATUS set the endianness: - * - MSTATUS_UBE (User-mode), - * - MSTATUS_SBE (Supervisor-mode), - * - MSTATUS_MBE (Machine-mode) - * but we don't implement that yet. - */ - return MO_LE; -} - #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -154,7 +144,7 @@ static inline MemOp mo_endian(DisasContext *ctx) #define get_address_xl(ctx) ((ctx)->address_xl) #endif =20 -#define mxl_memop(ctx) ((get_xl(ctx) + 1) | mo_endian(ctx)) +#define mxl_memop(ctx) ((get_xl(ctx) + 1) | (ctx)->mo_endianness) =20 /* The word size for this machine mode. */ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) @@ -1147,7 +1137,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, TCGv src1, src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); MemOp size =3D mop & MO_SIZE; =20 - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; if (ctx->cfg_ptr->ext_zama16b && size >=3D MO_32) { mop |=3D MO_ATOM_WITHIN16; } else { @@ -1168,7 +1158,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic= *a, MemOp mop) TCGv src1 =3D get_address(ctx, a->rs1, 0); TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 - mop |=3D mo_endian(ctx); + mop |=3D ctx->mo_endianness; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); =20 @@ -1346,6 +1336,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; + ctx->mo_endianness =3D (ctx->base.tb->cs_base & TB_CSBASE_BIG_ENDIAN) + ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c200::1; envelope-from=Djordje.Todorovic@htecgroup.com; helo=DB3PR0202CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1776420242872154100 Content-Type: text/plain; charset="utf-8" Add riscv_is_big_endian() helper that checks the hart's big-endian CPU property and use it throughout the boot code: - ELF loading: pass ELFDATA2MSB or ELFDATA2LSB based on endianness - Firmware dynamic info: use cpu_to_be* or cpu_to_le* based on endianness - Reset vector: instructions (entries 0-5) remain always little-endian, data words (entries 6-9) use target data endianness. For RV64 BE, the hi/lo word pairs within each dword are swapped since LD reads as BE. This is part of the runtime big-endian support series which avoids separate BE binaries by handling endianness as a CPU property. Signed-off-by: Djordje Todorovic --- hw/riscv/boot.c | 81 +++++++++++++++++++++++++++++++++++------ include/hw/riscv/boot.h | 1 + 2 files changed, 70 insertions(+), 12 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e5490beda0..03fb338d2a 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -40,6 +40,28 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) return mcc->def->misa_mxl_max =3D=3D MXL_RV32; } =20 +bool riscv_is_big_endian(RISCVHartArrayState *harts) +{ + return harts->harts[0].cfg.big_endian; +} + +/* + * Convert a pair of 32-bit words forming a 64-bit dword to target data + * endianness. For big-endian, the hi/lo word order is swapped since LD + * interprets bytes as BE. + */ +static void riscv_boot_data_dword(uint32_t *data, bool big_endian) +{ + if (big_endian) { + uint32_t tmp =3D data[0]; + data[0] =3D cpu_to_be32(data[1]); + data[1] =3D cpu_to_be32(tmp); + } else { + data[0] =3D cpu_to_le32(data[0]); + data[1] =3D cpu_to_le32(data[1]); + } +} + /* * Return the per-socket PLIC hart topology configuration string * (caller must free with g_free()) @@ -247,8 +269,9 @@ void riscv_load_kernel(MachineState *machine, */ kernel_size =3D load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NU= LL, &info->image_low_addr, &info->image_hig= h_addr, - NULL, ELFDATA2LSB, EM_RISCV, - 1, 0, NULL, true, sym_cb); + NULL, + ELFDATA2LSB, + EM_RISCV, 1, 0, NULL, true, sym_cb); if (kernel_size > 0) { info->kernel_size =3D kernel_size; goto out; @@ -391,21 +414,32 @@ void riscv_rom_copy_firmware_info(MachineState *machi= ne, struct fw_dynamic_info64 dinfo64; void *dinfo_ptr =3D NULL; size_t dinfo_len; + bool big_endian =3D riscv_is_big_endian(harts); =20 if (riscv_is_32bit(harts)) { - dinfo32.magic =3D cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo32.version =3D cpu_to_le32(FW_DYNAMIC_INFO_VERSION); - dinfo32.next_mode =3D cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo32.next_addr =3D cpu_to_le32(kernel_entry); + dinfo32.magic =3D big_endian ? cpu_to_be32(FW_DYNAMIC_INFO_MAGIC_V= ALUE) + : cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VAL= UE); + dinfo32.version =3D big_endian ? cpu_to_be32(FW_DYNAMIC_INFO_VERSI= ON) + : cpu_to_le32(FW_DYNAMIC_INFO_VERSION= ); + dinfo32.next_mode =3D big_endian + ? cpu_to_be32(FW_DYNAMIC_INFO_NEXT_MODE_S) + : cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo32.next_addr =3D big_endian ? cpu_to_be32(kernel_entry) + : cpu_to_le32(kernel_entry); dinfo32.options =3D 0; dinfo32.boot_hart =3D 0; dinfo_ptr =3D &dinfo32; dinfo_len =3D sizeof(dinfo32); } else { - dinfo64.magic =3D cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); - dinfo64.version =3D cpu_to_le64(FW_DYNAMIC_INFO_VERSION); - dinfo64.next_mode =3D cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); - dinfo64.next_addr =3D cpu_to_le64(kernel_entry); + dinfo64.magic =3D big_endian ? cpu_to_be64(FW_DYNAMIC_INFO_MAGIC_V= ALUE) + : cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VAL= UE); + dinfo64.version =3D big_endian ? cpu_to_be64(FW_DYNAMIC_INFO_VERSI= ON) + : cpu_to_le64(FW_DYNAMIC_INFO_VERSION= ); + dinfo64.next_mode =3D big_endian + ? cpu_to_be64(FW_DYNAMIC_INFO_NEXT_MODE_S) + : cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); + dinfo64.next_addr =3D big_endian ? cpu_to_be64(kernel_entry) + : cpu_to_le64(kernel_entry); dinfo64.options =3D 0; dinfo64.boot_hart =3D 0; dinfo_ptr =3D &dinfo64; @@ -474,10 +508,33 @@ void riscv_setup_rom_reset_vec(MachineState *machine,= RISCVHartArrayState *harts reset_vec[2] =3D 0x00000013; /* addi x0, x0, 0 */ } =20 - /* copy in the reset vector in little_endian byte order */ - for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { + /* RISC-V instructions are always little-endian */ + for (i =3D 0; i < 6; i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } + + /* + * Data words (addresses at entries 6-9) must match the firmware's data + * endianness. + */ + if (riscv_is_32bit(harts)) { + for (i =3D 6; i < ARRAY_SIZE(reset_vec); i++) { + if (riscv_is_big_endian(harts)) { + reset_vec[i] =3D cpu_to_be32(reset_vec[i]); + } else { + reset_vec[i] =3D cpu_to_le32(reset_vec[i]); + } + } + } else { + /* + * For RV64, each pair of 32-bit words forms a dword. For big-endi= an, + * the hi/lo word order within each dword must be swapped since LD + * interprets bytes as BE. + */ + for (i =3D 6; i < ARRAY_SIZE(reset_vec); i +=3D 2) { + riscv_boot_data_dword(reset_vec + i, riscv_is_big_endian(harts= )); + } + } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_base, &address_space_memory); riscv_rom_copy_firmware_info(machine, harts, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f00b3ca122..93b9a37f03 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -39,6 +39,7 @@ typedef struct RISCVBootInfo { } RISCVBootInfo; =20 bool riscv_is_32bit(RISCVHartArrayState *harts); +bool riscv_is_big_endian(RISCVHartArrayState *harts); =20 char *riscv_plic_hart_config_string(int hart_count); =20 --=20 2.34.1 From nobody Sat May 30 20:13:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c200::1; envelope-from=Djordje.Todorovic@htecgroup.com; helo=DB3PR0202CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1776420261690158500 The page table walker reads PTEs using address_space_ldl/ldq which use compile-time native endianness (always LE for RISC-V). However, when a big-endian kernel writes PTEs via normal store instructions, they are stored in big-endian byte order. The walker then misinterprets the PTE values, causing page faults and a hang when the kernel enables the MMU. The RISC-V privileged specification states that implicit data memory accesses to supervisor-level memory management data structures follow the hart's endianness setting (MSTATUS SBE/MBE bits). Fix both PTE reads and atomic A/D bit updates to use the explicit _le or _be memory access variants based on the hart's runtime endianness. Signed-off-by: Djordje Todorovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu_helper.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c28832e0e3..b3d33da13e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1365,9 +1365,13 @@ static int get_physical_address(CPURISCVState *env, = hwaddr *physical, } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - pte =3D address_space_ldl_le(cs->as, pte_addr, attrs, &res); + pte =3D riscv_cpu_data_is_big_endian(env) + ? address_space_ldl_be(cs->as, pte_addr, attrs, &res) + : address_space_ldl_le(cs->as, pte_addr, attrs, &res); } else { - pte =3D address_space_ldq_le(cs->as, pte_addr, attrs, &res); + pte =3D riscv_cpu_data_is_big_endian(env) + ? address_space_ldq_be(cs->as, pte_addr, attrs, &res) + : address_space_ldq_le(cs->as, pte_addr, attrs, &res); } =20 if (res !=3D MEMTX_OK) { @@ -1566,12 +1570,24 @@ static int get_physical_address(CPURISCVState *env,= hwaddr *physical, if (memory_region_is_ram(mr)) { target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1= ); target_ulong old_pte; + bool be =3D riscv_cpu_data_is_big_endian(env); if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { - old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, cpu_to_le3= 2(pte), cpu_to_le32(updated_pte)); - old_pte =3D le32_to_cpu(old_pte); + uint32_t cmp =3D be ? cpu_to_be32(pte) + : cpu_to_le32(pte); + uint32_t val =3D be ? cpu_to_be32(updated_pte) + : cpu_to_le32(updated_pte); + old_pte =3D qatomic_cmpxchg((uint32_t *)pte_pa, + cmp, val); + old_pte =3D be ? be32_to_cpu(old_pte) + : le32_to_cpu(old_pte); } else { - old_pte =3D qatomic_cmpxchg(pte_pa, cpu_to_le64(pte), cpu_= to_le64(updated_pte)); - old_pte =3D le64_to_cpu(old_pte); + target_ulong cmp =3D be ? cpu_to_be64(pte) + : cpu_to_le64(pte); + target_ulong val =3D be ? cpu_to_be64(updated_pte) + : cpu_to_le64(updated_pte); + old_pte =3D qatomic_cmpxchg(pte_pa, cmp, val); + old_pte =3D be ? be64_to_cpu(old_pte) + : le64_to_cpu(old_pte); } if (old_pte !=3D pte) { goto restart; --=20 2.34.1 From nobody Sat May 30 20:13:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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b=K4GFV/ZWkqneaY4Aof4IYyH7fMpEYSkAF0cXSkcNwwUtB3K6O04F1m1gG59Y2iUSvwDWZaoZjEO/OnCeYE1BXAtKqLY+sQcCnu93fAbZhge5DhiR9if3YrfrgnXWf+5ChXuhYtlcFKOjbw9jLBrlQYFXBHU6xbvf4Kr8stKJdEIfKxddrHfyneNgMiVfxwP8E+8YJGX38/aQCSddRX4pgzxiFCt825WyUyb43FFeIbluotJuFqWBTxdcM20Q+5ODjt4mYCnCncYGYa8n9mzreskYki4NBk3i094COCZX89YAVZLYuDIJVrNVwaoekH09ItEi/X31kBviIEfCIwTzjQ== From: Djordje Todorovic To: "qemu-devel@nongnu.org" CC: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" , "alistair23@gmail.com" , "thuth@redhat.com" , Djordje Todorovic Subject: [PATCH v7 6/6] target/riscv: Add test for RISC-V BE Thread-Topic: [PATCH v7 6/6] target/riscv: Add test for RISC-V BE Thread-Index: AQHczlFnQUhj58YbwkiHr8IkU7Ix+w== Date: Fri, 17 Apr 2026 10:03:14 +0000 Message-ID: <20260417100302.162260-7-djordje.todorovic@htecgroup.com> References: <20260417100302.162260-1-djordje.todorovic@htecgroup.com> In-Reply-To: <20260417100302.162260-1-djordje.todorovic@htecgroup.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=htecgroup.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c200::1; envelope-from=Djordje.Todorovic@htecgroup.com; helo=DB3PR0202CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @htecgroup.com) X-ZM-MESSAGEID: 1776420261692158500 Content-Type: text/plain; charset="utf-8" Add functional test for RISC-V big-endian. Signed-off-by: Djordje Todorovic Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_bigendian.py | 57 ++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 tests/functional/riscv64/test_bigendian.py diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index b996c89d7d..d06d6ea112 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -11,6 +11,7 @@ tests_riscv64_system_quick =3D [ ] =20 tests_riscv64_system_thorough =3D [ + 'bigendian', 'boston', 'sifive_u', 'tuxrun', diff --git a/tests/functional/riscv64/test_bigendian.py b/tests/functional/= riscv64/test_bigendian.py new file mode 100644 index 0000000000..9e0b3b7db5 --- /dev/null +++ b/tests/functional/riscv64/test_bigendian.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# +# Functional tests for RISC-V big-endian support +# +# Copyright (c) 2026 MIPS +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset +from qemu_test import wait_for_console_pattern + + +class RiscvBigEndian(QemuSystemTest): + """ + Tests for RISC-V runtime big-endian data support. + + Uses a bare-metal RV64 ELF that detects data endianness at runtime + by storing a 32-bit word and reading back byte 0. Prints "ENDIAN: BE" + or "ENDIAN: LE" to the NS16550A UART on the virt machine. + """ + + timeout =3D 10 + + ASSET_BE_TEST =3D Asset( + 'https://github.com/MIPS/linux-test-downloads/raw/main/' + 'riscvbe-baremetal/be-test-bare-metal.elf', + '9ad51b675e101de65908fadbac064ed1d0564c17463715d09dd734db86ea0f58') + + def _run_bare_metal(self, big_endian=3DFalse): + self.set_machine('virt') + kernel =3D self.ASSET_BE_TEST.fetch() + self.vm.add_args('-bios', 'none') + self.vm.add_args('-kernel', kernel) + if big_endian: + self.vm.add_args('-cpu', 'rv64,big-endian=3Don') + self.vm.set_console() + self.vm.launch() + expected =3D 'ENDIAN: BE' if big_endian else 'ENDIAN: LE' + wait_for_console_pattern(self, expected) + + def test_bare_metal_littleendian(self): + """ + Boot bare-metal ELF on virt with default little-endian CPU. + Expects "ENDIAN: LE" on UART. + """ + self._run_bare_metal(big_endian=3DFalse) + + def test_bare_metal_bigendian(self): + """ + Boot bare-metal ELF on virt with big-endian=3Don CPU property. + Expects "ENDIAN: BE" on UART. + """ + self._run_bare_metal(big_endian=3DTrue) + + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.34.1