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That in turn means that tests of cpu_isar_feature(aa64_something, cpu) will return true. Until now we have had a design policy that you shouldn't check an aa64_ feature unless you know that the CPU has AArch64; but this is quite fragile as it's easy to forget and only causes a problem in the corner case where AArch64 was turned off. In particular, when we extend the ability to disable AArch64 from only KVM to also TCG there are many more aa64 feature check points which we would otherwise have to audit for whether they needed to be guarded with a check on ARM_FEATURE_AARCH64. Instead, make the CPU realize function zero out all the 64-bit ID registers if a TCG CPU doesn't have AArch64; this will make aa64_ feature tests generally return false. We only do this for TCG because only TCG really needs it, and for KVM it might be confusing to have QEMU's idea of the ID registers be different from KVM's. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v1->v2: limit scope of register clearing to TCG, as I suggested after posting and testing the v1 version: https://patchew.org/QEMU/20251002101648.2455374-1-peter.maydell@linaro.org= /20251002101648.2455374-2-peter.maydell@linaro.org/ --- target/arm/cpu.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 3 ++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ccc47c8a9a..11d3437843 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1610,6 +1610,27 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) } } =20 +static void arm_clear_aarch64_idregs(ARMCPU *cpu) +{ + /* Zero out all the AArch64 ID registers in ARMISARegisters */ + SET_IDREG(&cpu->isar, ID_AA64ISAR0, 0); + SET_IDREG(&cpu->isar, ID_AA64ISAR1, 0); + SET_IDREG(&cpu->isar, ID_AA64ISAR2, 0); + SET_IDREG(&cpu->isar, ID_AA64PFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64PFR1, 0); + SET_IDREG(&cpu->isar, ID_AA64PFR2, 0); + SET_IDREG(&cpu->isar, ID_AA64MMFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64MMFR1, 0); + SET_IDREG(&cpu->isar, ID_AA64MMFR2, 0); + SET_IDREG(&cpu->isar, ID_AA64MMFR3, 0); + SET_IDREG(&cpu->isar, ID_AA64DFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64DFR1, 0); + SET_IDREG(&cpu->isar, ID_AA64AFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64AFR1, 0); + SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); + SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); +} + static void arm_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1737,6 +1758,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) } #endif =20 + /* + * A TCG aarch64=3Doff CPU has no AArch64 at all, so we clear out the + * ID registers to avoid cpu_isar_feature(aa64_something, cpu) tests + * incorrectly returning true. We don't do this for other accelerators + * (which in practice means "for KVM", since no others have AArch32 + * guest support) because from KVM's point of view the AArch64 ID + * registers still exist and must have their correct values. So we + * avoid clearing them out so that we don't have QEMU and KVM with + * different ideas of the ID registers. + */ + if (tcg_enabled() && !arm_feature(env, ARM_FEATURE_AARCH64)) { + arm_clear_aarch64_idregs(cpu); + } + #ifdef CONFIG_USER_ONLY /* * User mode relies on IC IVAU instructions to catch modification of diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 657ff4ab20..ab6bacf4aa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1080,7 +1080,8 @@ struct ArchCPU { * Note that if you add an ID register to the ARMISARegisters struct * you need to also update the 32-bit and 64-bit versions of the * kvm_arm_get_host_cpu_features() function to correctly populate the - * field by reading the value from the KVM vCPU. + * field by reading the value from the KVM vCPU. If it is an AArch64 + * ID register then you also must update arm_clear_aarch64_idregs(). */ struct ARMISARegisters { uint32_t mvfr0; --=20 2.43.0 From nobody Sat May 30 20:11:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776358498; cv=none; d=zohomail.com; s=zohoarc; b=nUaoOUpXEig0csrkRLxCydQTtseBV8eb825knJdFonrvePLmA0d0uy/rUJVtXaWyb+wuKjDUCLcobjWC1fJ9+kHVWzXpzTpgpiQb11L9iNu5ZtN0ev+Wm/uP1jHG8CJCqyfONwqfmyy72VqtPs3IblfJXfs5Nk6kHwqwuWPaOtc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776358498; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CxoE2sQDfNJcl7sNbi2G1nRN3fSKrRDunzLrpBK4/AE=; b=IsNUaZaAtr3Xy1DEGgtw4Wqf3b5FXc8I81gaJXcgYDFgcOD+sLeXhzyXT1kherwkZcPI7s3qjpBtC59V97nl/3VCqAzby0Dp7kZDfDNzijum15KYnlWUyyAGyqULxrhJa3vK6J9FsCYc2Q74fJIfiWAtHTluCYGSRFMus74m7xk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776358498823622.3514385316413; Thu, 16 Apr 2026 09:54:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wDPyi-0006Ay-Kh; Thu, 16 Apr 2026 12:54:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wDPyh-0006A7-30 for qemu-devel@nongnu.org; Thu, 16 Apr 2026 12:54:07 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wDPyf-0007ou-7Z for qemu-devel@nongnu.org; Thu, 16 Apr 2026 12:54:06 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-488ba840146so81567965e9.1 for ; Thu, 16 Apr 2026 09:54:04 -0700 (PDT) Received: from lanath.. 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Note that we don't permit it on the qemu-aarch64 user-mode binary: this makes no sense as that executable can only handle AArch64 syscalls (and it would also assert at startup since it doesn't compile in the A32-specific GDB xml files like arm-neon.xml). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Cl=C3=A9ment Chigot Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v1->v2: slight tweak to the docs wording --- docs/system/arm/cpu-features.rst | 10 +++++---- target/arm/cpu-features.h | 5 +++++ target/arm/cpu.c | 36 ++++++++++++++++++++++++++++---- tests/qtest/arm-cpu-features.c | 8 ++----- 4 files changed, 45 insertions(+), 14 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index ce19ae6a04..10b0eff27e 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -23,10 +23,12 @@ not implement ARMv8-A, will not have the ``aarch64`` CP= U property. QEMU's support may be limited for some CPU features, only partially supporting the feature or only supporting the feature under certain configurations. For example, the ``aarch64`` CPU feature, which, when -disabled, enables the optional AArch32 CPU feature, is only supported -when using the KVM accelerator and when running on a host CPU type that -supports the feature. While ``aarch64`` currently only works with KVM, -it could work with TCG. CPU features that are specific to KVM are +disabled, enables the optional AArch32 CPU feature, can only be set to +``off`` on the TCG and KVM accelerators, and it cannot be set to +``off`` under KVM unless running on a host CPU type that supports +running guests in AArch32. + +CPU features that are inherently specific to KVM are prefixed with "kvm-" and are described in "KVM VCPU Features". =20 CPU Feature Probing diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index b683c9551a..6e5212ff6c 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1071,6 +1071,11 @@ static inline bool isar_feature_aa64_aa32_el2(const = ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >=3D 2; } =20 +static inline bool isar_feature_aa64_aa32_el3(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL3) >=3D 2; +} + static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 11d3437843..347616fa5a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1248,10 +1248,38 @@ static void aarch64_cpu_set_aarch64(Object *obj, bo= ol value, Error **errp) * uniform execution state like do_interrupt. */ if (value =3D=3D false) { - if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { - error_setg(errp, "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported"); + if (kvm_enabled()) { + if (!kvm_arm_aarch32_supported()) { + error_setg(errp, "'aarch64' feature cannot be disabled for= KVM " + "because this host does not support 32-bit EL1"= ); + return; + } + } else if (tcg_enabled()) { +#ifdef CONFIG_USER_ONLY + error_setg(errp, "'aarch64' feature cannot be disabled for " + "usermode emulator qemu-aarch64; use qemu-arm inste= ad"); + return; +#else + bool aa32_at_highest_el; + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { + aa32_at_highest_el =3D cpu_isar_feature(aa64_aa32_el3, cpu= ); + } else if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { + aa32_at_highest_el =3D cpu_isar_feature(aa64_aa32_el2, cpu= ); + } else { + aa32_at_highest_el =3D cpu_isar_feature(aa64_aa32_el1, cpu= ); + } + + if (!aa32_at_highest_el) { + error_setg(errp, "'aarch64' feature cannot be disabled for= " + "this TCG CPU because it does not support 32-bi= t " + "execution at its highest implemented exception= " + "level"); + return; + } +#endif + } else { + error_setg(errp, "'aarch64' feature cannot be disabled for " + "this accelerator"); return; } unset_feature(&cpu->env, ARM_FEATURE_AARCH64); diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index bbdd89a81d..cb4d01fd46 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -493,12 +493,8 @@ static void test_query_cpu_model_expansion(const void = *data) sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); =20 - /* Test that features that depend on KVM generate errors without. = */ - assert_error(qts, "max", - "'aarch64' feature cannot be disabled " - "unless KVM is enabled and 32-bit EL1 " - "is supported", - "{ 'aarch64': false }"); + /* TCG allows us to turn off AArch64 on the 'max' CPU type */ + assert_set_feature(qts, "max", "aarch64", false); } =20 qtest_quit(qts); --=20 2.43.0 From nobody Sat May 30 20:11:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776358527; cv=none; d=zohomail.com; s=zohoarc; b=VOVSktZVEg/tm1iA4eiGpGG7+1muxKGZ7HTL4+62sy4ppAit9mCiFatkJqRTBEFarODm/UsB8ISmZ6bEwtSlAi54Oa1vf1UllVxyWlqka9o5l8djR4+Eq92+/FJgBfOi9Y1BomxHYpuOh3KI5aTVP9Du75d6jzHblLtzDsueSN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776358527; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fa79d476sm473035e9.1.2026.04.16.09.54.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2026 09:54:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1776358445; x=1776963245; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aEvZ7lrKLdAgMPjxUR6yVusIcpnHSNVLRW4q8x7Iv2s=; b=SDz5089kQrFyqbadZZoWfAEnOn9cqid7Upa4VQbj6/ocGJfJUVp1hEUmoCG2ifj9G4 T7vLvGulxnHJcEdLsJu23PFboL5XHi632SEf/YOQjxMX+Psat0NDVFFG/7IFrOXpEwZw U9yq0eIv0uQclB7T3u7zx2O0Ft5fuwFitfxNqYwDUaRQ76DuSnkv4WojQoUNDZ2zQPJK U9nV+QOF0/wD72ro7VRE0jyX5RYjKrzloMajUoEQRiLVkq6H8Qqn2hVSDld+MJjSIVmC emmG3zGTYpq6ilwXT6UafgoePKCjbxIbCsFi9IAzaVdEFZVtP8FkvuTTHmOto+v3wlnE M6ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776358445; x=1776963245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=aEvZ7lrKLdAgMPjxUR6yVusIcpnHSNVLRW4q8x7Iv2s=; b=SJUT3js1w0zPOPjp84JhJxg8Vdv0ymdQ5j/ClJB1oReio9/Gn/WmJtVKThY9MFFJ6A 8xQx6opip9Pz0iomZHbOCCWj0JLTvyn5M9A4P1AlwcaAvvOjZVAYXGplVL24kDyBwAeq RBu7Xi5VPieGojDUvtOC54EGs2mI2VKQbp56kkaOGEEZ/pAlAxFyiF28yRic8xy/vPU7 hFvqjNbKGL0jR/OV+ZLia/1w/hrRUdzGjOlqdpn5PamWUiRydOWL+0UjlLso7oJ7+9tV +kJHOyNyYwx27fMRowjG+nLIpwIjfbITn1hiXEirq0W/vonSz+50BFKjSdCOYARzykhh uHFQ== X-Forwarded-Encrypted: i=1; AFNElJ+TN0InivtCBsUDK5ySO3IbmeE35xEEjHuS1L9K+h/gz8auu9MDaLmVp9ZT2GFlVxl7w0NxoCY5QuHW@nongnu.org X-Gm-Message-State: AOJu0YxNXIX8FvVlILWTpsaB38iXf92L4GB4u8w8iMfqBeqwLUdX1wBY Mm8kRg+v3ZeYFz7H+bb3fqmjQthp6dTAJ885WOk53FeVY3ZFEzm4J8gBcHsFk0HNprc= X-Gm-Gg: AeBDietVI9Pkja7QTPy+APrJkGsFfgHcpUFCg0uxhGtNytGEIBCW9plFq5HYZSkGSge mbARiskZJp7e2NAMsor1wYmrvFazO9eOsD+w8cnFcZEGKNwli4tPrTYgDIpWtI4dmB/CBhChwpp RLhneJ1spZhS11+hIgDPk/GzJwVoWKzgxVmz0W+emT6JoDNK5sjgVXx4NJ0auc8hMnMH/iCN/Md TagecyQ2f1wjtRbKDPgeqPADMRI7HGAoTrIVvww/IQJqvciMTOZ2LZIdCgpZoYmWS+VaT006ugg t7cmoiZ2OeRfm1BgDXj+F+NQnyOjtXWLUjO5tzi4LAbgt9D+ocRDeLZytwID1RhZPGGiD1TrT2W EgkVlM1AEhIznoGPDVqMyftVKUeDRJnWgCUbkvt75uYh0mBk4KUtN5iPEhYyCPnAiv7+rjfUTsl M72TukQfG0QL3pI74ndb/T+rDd2g1oMVaJ1pl2IAIDUrxJ+LqLSKEZ7ABmtj09GPFDzL1IA4Z4u p67D1VXQQM5a9x53mg09NoDva0i+4AvKgUCZmfcug== X-Received: by 2002:a05:600c:3b24:b0:480:2521:4d92 with SMTP id 5b1f17b1804b1-488d687adb3mr388987975e9.24.1776358445122; Thu, 16 Apr 2026 09:54:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Cl=C3=A9ment=20Chigot?= Subject: [PATCH v2 3/3] tests/functional/aarch64: Add basic test of TCG aarch64=off Date: Thu, 16 Apr 2026 17:53:53 +0100 Message-ID: <20260416165353.589569-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260416165353.589569-1-peter.maydell@linaro.org> References: <20260416165353.589569-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776358529338154100 Content-Type: text/plain; charset="utf-8" Add a basic test of the TCG 'aarch64=3Doff' functionality; this is the same as our existing arm/test_virt test, but it runs the AArch32 guest kernel on qemu-system-aarch64 with -cpu max,aarch64=3Doff. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- tests/functional/aarch64/meson.build | 1 + .../aarch64/test_virt_aarch64_off.py | 37 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100755 tests/functional/aarch64/test_virt_aarch64_off.py diff --git a/tests/functional/aarch64/meson.build b/tests/functional/aarch6= 4/meson.build index 7ea8c22b04..de6f3ad5e6 100644 --- a/tests/functional/aarch64/meson.build +++ b/tests/functional/aarch64/meson.build @@ -45,6 +45,7 @@ tests_aarch64_system_thorough =3D [ 'tcg_plugins', 'tuxrun', 'virt', + 'virt_aarch64_off', 'virt_gpu', 'virt_vbsa', 'xen', diff --git a/tests/functional/aarch64/test_virt_aarch64_off.py b/tests/func= tional/aarch64/test_virt_aarch64_off.py new file mode 100755 index 0000000000..13d8b73b0d --- /dev/null +++ b/tests/functional/aarch64/test_virt_aarch64_off.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +# +# Functional test that boots an AArch32 Linux kernel and checks the console +# on a TCG aarch64 CPU with aarch64=3Doff. This is the same image etc +# as we use in tests/functional/arm/test_virt.py. +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest, Asset + +class ArmVirtMachine(LinuxKernelTest): + + ASSET_KERNEL =3D Asset( + ('https://archives.fedoraproject.org/pub/archive/fedora/linux/' + 'releases/29/Everything/armhfp/os/images/pxeboot/vmlinuz'), + '18dd5f1a9a28bd539f9d047f7c0677211bae528e8712b40ca5a229a4ad8e2591') + + def test_arm_virt(self): + self.set_machine('virt') + # KVM aarch64=3Doff requires a host CPU that supports it, so + # restrict the test to TCG only + self.require_accelerator('tcg') + self.vm.add_args('-cpu', 'max,aarch64=3Doff') + + kernel_path =3D self.ASSET_KERNEL.fetch() + + self.vm.set_console() + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + + 'console=3DttyAMA0') + self.vm.add_args('-kernel', kernel_path, + '-append', kernel_command_line) + self.vm.launch() + console_pattern =3D 'Kernel command line: %s' % kernel_command_line + self.wait_for_console_pattern(console_pattern) + +if __name__ =3D=3D '__main__': + LinuxKernelTest.main() --=20 2.43.0