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charset="utf-8" From: Nicolin Chen The updated IOMMUFD uAPI introduces the ability for userspace to request a specific hardware info data type via IOMMU_GET_HW_INFO. Update iommufd_backend_get_device_info() to set IOMMU_HW_INFO_FLAG_INPUT_TYPE when a non-zero type is supplied, and adjust all callers to pass a type value explicitly initialised to zero (IOMMU_HW_INFO_TYPE_DEFAULT) when no specific type is requested. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 7 +++++++ hw/arm/smmuv3-accel.c | 2 +- hw/vfio/iommufd.c | 4 ++-- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index 52cb060454..20d4186f29 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -397,16 +397,23 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend = *be, return true; } =20 +/* + * @type can carry a desired HW info type defined in the uapi headers. If = caller + * doesn't have one, indicating it wants the default type, then @type shou= ld be + * zeroed (i.e. IOMMU_HW_INFO_TYPE_DEFAULT). + */ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, uint64_t *caps, uint8_t *max_pasid_lo= g2, Error **errp) { struct iommu_hw_info info =3D { + .flags =3D (*type) ? IOMMU_HW_INFO_FLAG_INPUT_TYPE : 0, .size =3D sizeof(info), .dev_id =3D devid, .data_len =3D len, .data_uptr =3D (uintptr_t)data, + .in_data_type =3D *type, }; =20 if (ioctl(be->fd, IOMMU_GET_HW_INFO, &info)) { diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 48f8017262..d68d4141a0 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -172,7 +172,7 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDev= iceIOMMUFD *idev, Error **errp) { struct iommu_hw_info_arm_smmuv3 info; - uint32_t data_type; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_DEFAULT; uint64_t caps; =20 if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 3e33dfbb35..4043111667 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -352,7 +352,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, ERRP_GUARD(); IOMMUFDBackend *iommufd =3D vbasedev->iommufd; VFIOContainer *bcontainer =3D VFIO_IOMMU(container); - uint32_t type, flags =3D 0; + uint32_t type =3D IOMMU_HW_INFO_TYPE_DEFAULT, flags =3D 0; uint64_t hw_caps; VendorCaps caps; VFIOIOASHwpt *hwpt; @@ -941,7 +941,7 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *= hiod, void *opaque, HostIOMMUDeviceIOMMUFD *idev; HostIOMMUDeviceCaps *caps =3D &hiod->caps; VendorCaps *vendor_caps =3D &caps->vendor_caps; - enum iommu_hw_info_type type; + uint32_t type =3D IOMMU_HW_INFO_TYPE_DEFAULT; uint8_t max_pasid_log2; uint64_t hw_caps; =20 --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250671; cv=pass; d=zohomail.com; s=zohoarc; b=JXhKZbmrE/UGnDse/+9aQE9smZ8I1xGlDBsr2VvZFqrhX2ltkhKzzBnWj977lPNhw0fo0oF0n0z/Lz9kFUbbKFefwfFrZhTz3Yb5nAaikz/T7CVvj+eLj3y3pAufM6j9OhQdM84KMiKSYBdXNL0N5QnCSr4Pb5XXU1eH3LhtH8Q= ARC-Message-Signature: i=2; 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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7971 Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=skolothumtho@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1776250673827154100 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The updated IOMMUFD VIOMMU_ALLOC uAPI allows userspace to provide a data buffer when creating a vIOMMU (e.g. for Tegra241 CMDQV). Extend iommufd_backend_alloc_viommu() to pass a user pointer and size to the kernel. Update the caller accordingly. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 1 + backends/iommufd.c | 4 ++++ hw/arm/smmuv3-accel.c | 4 ++-- backends/trace-events | 2 +- 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 7062944fe6..e027800c91 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -89,6 +89,7 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint3= 2_t dev_id, Error **errp); bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_hwpt, Error **errp); =20 bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index 20d4186f29..9b07ac19c2 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -470,6 +470,7 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *b= e, uint32_t id, =20 bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_viommu_id, Error **errp) { int ret; @@ -478,11 +479,14 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be,= uint32_t dev_id, .type =3D viommu_type, .dev_id =3D dev_id, .hwpt_id =3D hwpt_id, + .data_len =3D data_len, + .data_uptr =3D (uintptr_t)data_ptr, }; =20 ret =3D ioctl(be->fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); =20 trace_iommufd_backend_alloc_viommu(be->fd, dev_id, viommu_type, hwpt_i= d, + (uintptr_t)data_ptr, data_len, alloc_viommu.out_viommu_id, ret); if (ret) { error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index d68d4141a0..c356ff9708 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -578,8 +578,8 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *idev, IOMMUFDViommu *viommu; =20 if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, - s2_hwpt_id, &viommu_id, errp)) { + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, + NULL, 0, &viommu_id, errp)) { return false; } =20 diff --git a/backends/trace-events b/backends/trace-events index b9365113e7..3ba0c3503c 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -21,7 +21,7 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" -iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_ptr=3D0x%"= PRIx64" data_len=3D0x%x viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" =20 --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd backed HW queue for a vIOMMU. While at it, define a struct IOMMUFDHWqueue for use by vendor implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 11 +++++++++++ backends/iommufd.c | 31 +++++++++++++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 43 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index e027800c91..8009ce3d31 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -65,6 +65,12 @@ typedef struct IOMMUFDVeventq { bool event_start; /* True after first valid event; cleared on overflow= */ } IOMMUFDVeventq; =20 +/* HW queue object for a vIOMMU-specific HW-accelerated queue */ +typedef struct IOMMUFDHWqueue { + IOMMUFDViommu *viommu; + uint32_t hw_queue_id; +} IOMMUFDHWqueue; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -101,6 +107,11 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, uint32_t *out_veventq_id, uint32_t *out_veventq_fd, Error **errp); =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t queue_type, uint32_t index, + uint64_t addr, uint64_t length, + uint32_t *out_hw_queue_id, Error **err= p); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index 9b07ac19c2..3be7b07eec 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -556,6 +556,37 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, return true; } =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t queue_type, uint32_t index, + uint64_t addr, uint64_t length, + uint32_t *out_hw_queue_id, Error **err= p) +{ + int ret; + struct iommu_hw_queue_alloc alloc_hw_queue =3D { + .size =3D sizeof(alloc_hw_queue), + .flags =3D 0, + .viommu_id =3D viommu_id, + .type =3D queue_type, + .index =3D index, + .nesting_parent_iova =3D addr, + .length =3D length, + }; + + ret =3D ioctl(be->fd, IOMMU_HW_QUEUE_ALLOC, &alloc_hw_queue); + + trace_iommufd_backend_alloc_hw_queue(be->fd, viommu_id, queue_type, + index, addr, length, + alloc_hw_queue.out_hw_queue_id, r= et); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_HW_QUEUE_ALLOC failed"); + return false; + } + + g_assert(out_hw_queue_id); + *out_hw_queue_id =3D alloc_hw_queue.out_hw_queue_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 3ba0c3503c..c5c1d95aad 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -24,6 +24,7 @@ iommufd_backend_invalidate_cache(int iommufd, uint32_t id= , uint32_t data_type, u iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_ptr=3D0x%"= PRIx64" data_len=3D0x%x viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" +iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Add a backend helper to mmap hardware MMIO regions exposed via iommufd for a vIOMMU instance. This allows user space to access HW-accelerated MMIO pages provided by the vIOMMU. The caller is responsible for unmapping the returned region. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 4 ++++ backends/iommufd.c | 22 ++++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 27 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 8009ce3d31..38cfceca84 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -112,6 +112,10 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, uint64_t addr, uint64_t length, uint32_t *out_hw_queue_id, Error **err= p); =20 +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index 3be7b07eec..e26675990e 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -587,6 +587,28 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, return true; } =20 +/* + * Helper to mmap HW MMIO regions exposed via iommufd for a vIOMMU instanc= e. + * The caller is responsible for unmapping the mapped region. + */ +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp) +{ + g_assert(viommu_id); + g_assert(out_ptr); + + *out_ptr =3D mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, be->= fd, + offset); + trace_iommufd_backend_viommu_mmap(be->fd, viommu_id, size, offset); + if (*out_ptr =3D=3D MAP_FAILED) { + error_setg_errno(errp, errno, "IOMMUFD vIOMMU mmap failed"); + return false; + } + + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index c5c1d95aad..b63420b73e 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -25,6 +25,7 @@ iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id= , uint32_t type, uint32 iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" +iommufd_backend_viommu_mmap(int iommufd, uint32_t viommu_id, uint64_t size= , uint64_t offset) " iommufd=3D%d viommu_id=3D%u size=3D0x%"PRIx64" offset= =3D0x%"PRIx64 =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , Subject: [PATCH v4 05/31] system/iommufd: Remove unused viommu pointer from IOMMUFDVeventq Date: Wed, 15 Apr 2026 11:55:26 +0100 Message-ID: <20260415105552.622421-6-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260415105552.622421-1-skolothumtho@nvidia.com> References: <20260415105552.622421-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6A:EE_|DM4PR12MB6085:EE_ X-MS-Office365-Filtering-Correlation-Id: 6bea79b7-06c0-4d7b-a867-08de9addbbd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" The viommu field is assigned but never used. Callers freeing the veventq already have access to the IOMMUFDViommu object through other references, so this field is redundant. Removing it also simplifies upcoming changes where veventq is allocated based on the viommu id before the IOMMUFDViommu object is created (e.g. vendor CMDQV-based veventq allocation). No functional change. Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 1 - hw/arm/smmuv3-accel.c | 1 - 2 files changed, 2 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 38cfceca84..b6599521b8 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -58,7 +58,6 @@ typedef struct IOMMUFDVdev { =20 /* Virtual event queue interface for a vIOMMU */ typedef struct IOMMUFDVeventq { - IOMMUFDViommu *viommu; uint32_t veventq_id; uint32_t veventq_fd; uint32_t last_event_seq; /* Sequence number of last processed event */ diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c356ff9708..f65e654adf 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -549,7 +549,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error *= *errp) veventq =3D g_new0(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; - veventq->viommu =3D accel->viommu; accel->veventq =3D veventq; =20 /* Set up event handler for veventq fd */ --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Command Queue Virtualization (CMDQV) is a hardware extension available on certain platforms that allows the SMMUv3 command queue to be virtualized and passed through to a VM, improving performance. For example, NVIDIA Tegra241 implements CMDQV to support virtualization of multiple command queues (VCMDQs). The term CMDQV is used here generically to refer to any platform that provides hardware support to virtualize the SMMUv3 command queue. CMDQV support is a specialization of the IOMMUFD-backed accelerated SMMUv3 path. Introduce an ops interface to factor out CMDQV-specific probe, initialization, and vIOMMU allocation logic from the base implementation. The ops pointer and associated state are stored in the accelerated SMMUv3 state. This provides an extensible design to support future vendor-specific CMDQV implementations. No functional change. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 7b4a0be000..86301afcb4 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -10,11 +10,28 @@ #define HW_ARM_SMMUV3_ACCEL_H =20 #include "hw/arm/smmu-common.h" +#include "hw/arm/smmuv3.h" #include "system/iommufd.h" #ifdef CONFIG_LINUX #include #endif =20 +/* + * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to + * support multiple VCMDQs with virtualization capabilities. + * CMDQV specific behavior is factored behind this ops interface. + */ +typedef struct SMMUv3AccelCmdqvOps { + bool (*probe)(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **er= rp); + bool (*init)(SMMUv3State *s, Error **errp); + bool (*alloc_viommu)(SMMUv3State *s, + HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, + Error **errp); + void (*free_viommu)(SMMUv3State *s); + void (*reset)(SMMUv3State *s); +} SMMUv3AccelCmdqvOps; + /* * Represents an accelerated SMMU instance backed by an iommufd vIOMMU obj= ect. * Holds bypass and abort proxy HWPT IDs used for device attachment. @@ -27,6 +44,7 @@ typedef struct SMMUv3AccelState { QLIST_HEAD(, SMMUv3AccelDevice) device_list; bool auto_mode; bool auto_finalised; + const SMMUv3AccelCmdqvOps *cmdqv_ops; } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250708; cv=pass; d=zohomail.com; s=zohoarc; b=iybWInLw47XThYwtN0BNqvPkDfJjIEY5jYmV0J6EgSH8jFrDBGkCdT8TSTmeg8Qse6NdRZAUNM2T7DCeTJcrC41Jf7zS2y5/RNeOvA+MTPmArJoFR0XGiRdHubhAMW6OSB7p4anutwys+EN9Mwxd0VSM+Qyd4HPEk2fKfOCzMjA= ARC-Message-Signature: i=2; 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charset="utf-8" Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated CMDQV ops interface. This patch wires up the Tegra241 CMDQV backend and provides a stub implementation for CMDQV probe, initialization, vIOMMU allocation and reset handling. Functional CMDQV support is added in follow-up patches. Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 15 ++++++++++ hw/arm/tegra241-cmdqv-stubs.c | 16 ++++++++++ hw/arm/tegra241-cmdqv.c | 56 +++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 2 ++ 5 files changed, 94 insertions(+) create mode 100644 hw/arm/tegra241-cmdqv.h create mode 100644 hw/arm/tegra241-cmdqv-stubs.c create mode 100644 hw/arm/tegra241-cmdqv.c diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h new file mode 100644 index 0000000000..07e10e86ee --- /dev/null +++ b/hw/arm/tegra241-cmdqv.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * NVIDIA Tegra241 CMDQ-Virtualiisation extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_TEGRA241_CMDQV_H +#define HW_ARM_TEGRA241_CMDQV_H + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); + +#endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv-stubs.c b/hw/arm/tegra241-cmdqv-stubs.c new file mode 100644 index 0000000000..eabf90daf8 --- /dev/null +++ b/hw/arm/tegra241-cmdqv-stubs.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * + * Stubs for Tegra241 CMDQ-Virtualiisation extension for SMMUv3 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "smmuv3-accel.h" +#include "hw/arm/tegra241-cmdqv.h" + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void) +{ + return NULL; +} diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c new file mode 100644 index 0000000000..ad5a0d4611 --- /dev/null +++ b/hw/arm/tegra241-cmdqv.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + +static void tegra241_cmdqv_free_viommu(SMMUv3State *s) +{ +} + +static bool +tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static void tegra241_cmdqv_reset(SMMUv3State *s) +{ +} + +static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, + Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D { + .probe =3D tegra241_cmdqv_probe, + .init =3D tegra241_cmdqv_init, + .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, + .free_viommu =3D tegra241_cmdqv_free_viommu, + .reset =3D tegra241_cmdqv_reset, +}; + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void) +{ + return &tegra241_cmdqv_ops; +} diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4e50fb1111..073f2ebaaf 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -618,6 +618,10 @@ config FSL_IMX8MP_EVK depends on TCG select FSL_IMX8MP =20 +config TEGRA241_CMDQV + bool + depends on ARM_SMMUV3_ACCEL + config ARM_SMMUV3_ACCEL bool depends on ARM_SMMUV3 @@ -625,6 +629,7 @@ config ARM_SMMUV3_ACCEL config ARM_SMMUV3 bool select ARM_SMMUV3_ACCEL if IOMMUFD + imply TEGRA241_CMDQV =20 config FSL_IMX6UL bool diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 3be1252c4f..64bcdc5a7c 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -87,6 +87,8 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true:= files('imx8mp-evk.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-= accel.c')) stub_ss.add(files('smmuv3-accel-stubs.c')) +arm_common_ss.add(when: 'CONFIG_TEGRA241_CMDQV', if_true: files('tegra241-= cmdqv.c')) +stub_ss.add(files('tegra241-cmdqv-stubs.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add support for selecting and initializing a CMDQV backend based on the cmdqv OnOffAuto property. If set to OFF, CMDQV is not used and the default IOMMUFD-backed allocation path is taken. If set to AUTO, QEMU attempts to probe a CMDQV backend during device setup. If probing succeeds, the selected ops are stored in the accelerated SMMUv3 state and used. If probing fails, QEMU silently falls back to the default path. If set to ON, QEMU requires CMDQV support. Probing is performed during setup and failure results in an error. When a CMDQV backend is active, its callbacks are used for vIOMMU allocation, free, and reset handling. Otherwise, the base implementation is used. The current implementation wires up the Tegra241 CMDQV backend through the generic ops interface. Functional CMDQV behaviour is added in subsequent patches. No functional change. Signed-off-by: Shameer Kolothum --- include/hw/arm/smmuv3.h | 2 + hw/arm/smmuv3-accel.c | 93 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 88 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index fe0493c1aa..aa6a79237a 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -74,6 +74,8 @@ struct SMMUv3State { OnOffAuto ats; OasMode oas; SsidSizeMode ssidsize; + /* SMMU CMDQV extension */ + OnOffAuto cmdqv; =20 Notifier machine_done; }; diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f65e654adf..9068e65e2b 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -18,6 +18,7 @@ =20 #include "smmuv3-internal.h" #include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" =20 /* * The root region aliases the global system memory, and shared_as_sysmem @@ -566,6 +567,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *idev, Error **errp) { SMMUv3AccelState *accel =3D s->s_accel; + const SMMUv3AccelCmdqvOps *cmdqv_ops =3D accel->cmdqv_ops; struct iommu_hwpt_arm_smmuv3 bypass_data =3D { .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, }; @@ -576,10 +578,17 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, uint32_t viommu_id, hwpt_id; IOMMUFDViommu *viommu; =20 - if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, - NULL, 0, &viommu_id, errp)) { - return false; + if (cmdqv_ops) { + if (!cmdqv_ops->alloc_viommu(s, idev, &viommu_id, errp)) { + return false; + } + } else { + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, NULL, 0, &viommu_id, + errp)) { + return false; + } } =20 viommu =3D g_new0(IOMMUFDViommu, 1); @@ -625,12 +634,69 @@ free_bypass_hwpt: free_abort_hwpt: iommufd_backend_free_id(idev->iommufd, accel->abort_hwpt_id); free_viommu: - iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); + if (cmdqv_ops && cmdqv_ops->free_viommu) { + cmdqv_ops->free_viommu(s); + } else { + iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); + } g_free(viommu); accel->viommu =3D NULL; return false; } =20 +static const SMMUv3AccelCmdqvOps * +smmuv3_accel_probe_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + const SMMUv3AccelCmdqvOps *ops =3D tegra241_cmdqv_get_ops(); + + if (!ops || !ops->probe) { + error_setg(errp, "No CMDQV ops found"); + return NULL; + } + + if (!ops->probe(s, idev, errp)) { + return NULL; + } + return ops; +} + +static bool +smmuv3_accel_select_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + const SMMUv3AccelCmdqvOps *ops =3D NULL; + + if (s->s_accel->cmdqv_ops) { + return true; + } + + switch (s->cmdqv) { + case ON_OFF_AUTO_OFF: + s->s_accel->cmdqv_ops =3D NULL; + return true; + case ON_OFF_AUTO_AUTO: + ops =3D smmuv3_accel_probe_cmdqv(s, idev, NULL); + break; + case ON_OFF_AUTO_ON: + ops =3D smmuv3_accel_probe_cmdqv(s, idev, errp); + if (!ops) { + error_append_hint(errp, "CMDQV requested but not supported"); + return false; + } + s->s_accel->cmdqv_ops =3D ops; + break; + default: + g_assert_not_reached(); + } + + if (ops && ops->init && !ops->init(s, errp)) { + return false; + } + s->s_accel->cmdqv_ops =3D ops; + return true; +} + static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, HostIOMMUDevice *hiod, Error **e= rrp) { @@ -665,6 +731,10 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, goto done; } =20 + if (!smmuv3_accel_select_cmdqv(s, idev, errp)) { + return false; + } + if (!smmuv3_accel_alloc_viommu(s, idev, errp)) { error_append_hint(errp, "Unable to alloc vIOMMU: idev devid 0x%x: = ", idev->devid); @@ -936,8 +1006,17 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Er= ror **errp) =20 void smmuv3_accel_reset(SMMUv3State *s) { - /* Attach a HWPT based on GBPA reset value */ - smmuv3_accel_attach_gbpa_hwpt(s, NULL); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel) { + return; + } + /* Attach a HWPT based on GBPA reset value */ + smmuv3_accel_attach_gbpa_hwpt(s, NULL); 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charset="utf-8" Introduce a GPtrArray in VirtMachineState to track all SMMUv3 devices created on the virt machine, and use it when building the IORT table instead of relying on object_child_foreach_recursive() walks of the object tree. This avoids recursive object traversal and provides a foundation for subsequent patches that need direct access to SMMUv3 instances for CMDQV-related handling. No functional change. No bios-tables qtest failures observed. Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/hw/arm/virt.h | 1 + hw/arm/virt-acpi-build.c | 70 ++++++++++++++++++---------------------- hw/arm/virt.c | 3 ++ 3 files changed, 35 insertions(+), 39 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 5fcbd1c76f..a840a97de8 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -187,6 +187,7 @@ struct VirtMachineState { MemoryRegion *sysmem; MemoryRegion *secure_sysmem; bool pci_preserve_config; + GPtrArray *smmuv3_devices; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 591cfc993c..521443de87 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -385,49 +385,41 @@ static int smmuv3_dev_idmap_compare(gconstpointer a, = gconstpointer b) return map_a->input_base - map_b->input_base; } =20 -static int iort_smmuv3_devices(Object *obj, void *opaque) -{ - VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); - AcpiIortSMMUv3Dev sdev =3D {0}; - GArray *sdev_blob =3D opaque; - AcpiIortIdMapping idmap; - PlatformBusDevice *pbus; - int min_bus, max_bus; - SysBusDevice *sbdev; - PCIBus *bus; - - if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) { - return 0; - } - - bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); - sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); - pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); - sbdev =3D SYS_BUS_DEVICE(obj); - sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); - sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; - sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); - sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; - sdev.irq +=3D ARM_SPI_BASE; - - pci_bus_range(bus, &min_bus, &max_bus); - sdev.rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); - idmap.input_base =3D min_bus << 8, - idmap.id_count =3D (max_bus - min_bus + 1) << 8, - g_array_append_val(sdev.rc_smmu_idmaps, idmap); - g_array_append_val(sdev_blob, sdev); - return 0; -} - /* * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and * return the total number of idmaps. */ -static int populate_smmuv3_dev(GArray *sdev_blob) +static int populate_smmuv3_dev(VirtMachineState *vms, GArray *sdev_blob) { - object_child_foreach_recursive(object_get_root(), - iort_smmuv3_devices, sdev_blob); + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + Object *obj =3D OBJECT(g_ptr_array_index(vms->smmuv3_devices, i)); + AcpiIortSMMUv3Dev sdev =3D {0}; + AcpiIortIdMapping idmap; + PlatformBusDevice *pbus; + int min_bus, max_bus; + SysBusDevice *sbdev; + PCIBus *bus; + + bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", + &error_abort)); + sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); + sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + sdev.irq +=3D ARM_SPI_BASE; + + pci_bus_range(bus, &min_bus, &max_bus); + sdev.rc_smmu_idmaps =3D g_array_new(false, true, + sizeof(AcpiIortIdMapping)); + idmap.input_base =3D min_bus << 8; + idmap.id_count =3D (max_bus - min_bus + 1) << 8; + g_array_append_val(sdev.rc_smmu_idmaps, idmap); + g_array_append_val(sdev_blob, sdev); + } /* Sort the smmuv3 devices(if any) by smmu idmap input_base */ g_array_sort(sdev_blob, smmuv3_dev_idmap_compare); /* @@ -561,7 +553,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) if (vms->legacy_smmuv3_present) { rc_smmu_idmaps_len =3D populate_smmuv3_legacy_dev(smmuv3_devs); } else { - rc_smmu_idmaps_len =3D populate_smmuv3_dev(smmuv3_devs); + rc_smmu_idmaps_len =3D populate_smmuv3_dev(vms, smmuv3_devs); } =20 num_smmus =3D smmuv3_devs->len; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ec0d8475ca..68464ceb14 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3261,6 +3261,7 @@ static void virt_machine_device_plug_cb(HotplugHandle= r *hotplug_dev, } =20 create_smmuv3_dev_dtb(vms, dev, bus, errp); + g_ptr_array_add(vms->smmuv3_devices, dev); } } =20 @@ -3697,6 +3698,8 @@ static void virt_instance_init(Object *obj) vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); vms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); cxl_machine_init(obj, &vms->cxl_devices_state); + + vms->smmuv3_devices =3D g_ptr_array_new_with_free_func(NULL); } =20 static const TypeInfo virt_machine_info =3D { --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Use IOMMU_GET_HW_INFO to query host support for Tegra241 CMDQV. Validate the returned data type, version, and minimum number of vCMDQs and SIDs per Tegra241 CMDQ Virtual Interface(VI). Fail the probe if the host does not meet these requirements. The QEMU model supports one Virtual Interface(VI) per VM with 2 vCMDQs and 16 SIDs per VI, so the probe ensures the host implementation is compatible with these limits. Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 4 ++++ hw/arm/tegra241-cmdqv.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 07e10e86ee..c1866084f8 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,6 +10,10 @@ #ifndef HW_ARM_TEGRA241_CMDQV_H #define HW_ARM_TEGRA241_CMDQV_H =20 +#define CMDQV_VER 1 +#define CMDQV_NUM_CMDQ_LOG2 1 +#define CMDQV_NUM_SID_PER_VI_LOG2 4 + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index ad5a0d4611..3a19a1af56 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -38,8 +38,36 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error **= errp) static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV; + struct iommu_hw_info_tegra241_cmdqv cmdqv_info; + uint64_t caps; + + if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, + &cmdqv_info, sizeof(cmdqv_info), = &caps, + NULL, errp)) { + return false; + } + if (data_type !=3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV) { + error_setg(errp, "Host CMDQV: unexpected data type %u (expected %u= )", + data_type, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV); + return false; + } + if (cmdqv_info.version !=3D CMDQV_VER) { + error_setg(errp, "Host CMDQV: unsupported version %u (expected %u)= ", + cmdqv_info.version, CMDQV_VER); + return false; + } + if (cmdqv_info.log2vcmdqs < CMDQV_NUM_CMDQ_LOG2) { + error_setg(errp, "Host CMDQV: insufficient vCMDQs log2=3D%u (need = >=3D %u)", + cmdqv_info.log2vcmdqs, CMDQV_NUM_CMDQ_LOG2); + return false; + } + if (cmdqv_info.log2vsids < CMDQV_NUM_SID_PER_VI_LOG2) { + error_setg(errp, "Host CMDQV: insufficient SIDs log2=3D%u (need >= =3D %u)", + cmdqv_info.log2vsids, CMDQV_NUM_SID_PER_VI_LOG2); + return false; + } + return true; } =20 static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D { --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250727; cv=pass; d=zohomail.com; s=zohoarc; b=fhVbYZ2GM7nQUpZuQT4Ef14jEsZs3gL2MJSaTsL+56M6j3Jp1PVjl8nrVGcHguCcKP0FnYjk9R9Q68ggkf/vPHHKzSLfVODz2JKu2lEFfWyDBpXTathMEdpLeAqyrSGgPb316oZL8r2rSQUqN8kwVuztQrIXS3W4NnQXASTfkto= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776250727; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" From: Nicolin Chen Tegra241 CMDQV extends SMMUv3 with support for virtual command queues (VCMDQs) exposed via a CMDQV MMIO region. The CMDQV MMIO space is split into 64KB pages: 0x00000 (CMDQ-V Config page) 0x10000 (CMDQ-V CMDQ Page0) 0x20000 (CMDQ-V CMDQ Page1) 0x30000 (Virtual Interface Page0) 0x40000 (Virtual Interface Page1) This patch wires up the Tegra241 CMDQV init callback and allocates vendor-specific CMDQV state. The state pointer is stored in SMMUv3AccelState for use by subsequent CMDQV operations. The CMDQV MMIO region and a dedicated IRQ line are registered with the SMMUv3 device. The MMIO read/write handlers are currently stubs and will be implemented in later patches. The CMDQV interrupt is edge-triggered and indicates VCMDQ or VINTF error conditions. This patch only registers the IRQ line. Interrupt generation and propagation to the guest will be added in a subsequent patch. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 1 + hw/arm/tegra241-cmdqv.h | 18 ++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 30 ++++++++++++++++++++++++++++-- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 86301afcb4..28bceca061 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -45,6 +45,7 @@ typedef struct SMMUv3AccelState { bool auto_mode; bool auto_finalised; const SMMUv3AccelCmdqvOps *cmdqv_ops; + void *cmdqv; /* vendor specific CMDQV state */ } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index c1866084f8..2a34a4b6b4 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -14,6 +14,24 @@ #define CMDQV_NUM_CMDQ_LOG2 1 #define CMDQV_NUM_SID_PER_VI_LOG2 4 =20 +/* + * Tegra241 CMDQV MMIO layout (64KB pages) + * + * 0x00000 (CMDQ-V Config page) + * 0x10000 (CMDQ-V CMDQ Page0) + * 0x20000 (CMDQ-V CMDQ Page1) + * 0x30000 (Virtual Interface Page0) + * 0x40000 (Virtual Interface Page1) + */ +#define TEGRA241_CMDQV_IO_LEN 0x50000 + +typedef struct Tegra241CMDQV { + struct iommu_viommu_tegra241_cmdqv cmdqv_data; + SMMUv3AccelState *s_accel; + MemoryRegion mmio_cmdqv; + qemu_irq irq; +} Tegra241CMDQV; + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 3a19a1af56..ccd3c6d275 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -13,6 +13,16 @@ #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned = size) +{ + return 0; +} + +static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t val= ue, + unsigned size) +{ +} + static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { } @@ -29,10 +39,26 @@ static void tegra241_cmdqv_reset(SMMUv3State *s) { } =20 +static const MemoryRegionOps mmio_cmdqv_ops =3D { + .read =3D tegra241_cmdqv_read, + .write =3D tegra241_cmdqv_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); 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charset="utf-8" SMMUv3 devices with acceleration may enable CMDQV extensions after device realize. In that case, additional MMIO regions and IRQ lines may be registered but not yet mapped to the platform bus. Ensure SMMUv3 device resources are linked to the platform bus during machine_done(). This is safe to do unconditionally since the platform bus helpers skip resources that are already mapped. Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 68464ceb14..6c5e51af37 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1832,6 +1832,25 @@ static void virt_build_smbios(VirtMachineState *vms) } } =20 +/* + * SMMUv3 devices with acceleration may enable CMDQV extensions + * after device realize. In that case, additional MMIO regions and + * IRQ lines may be registered but not yet mapped to the platform bus. + * + * Ensure all resources are linked to the platform bus before final + * machine setup. + */ + +static void virt_smmuv3_dev_link_cmdqv(VirtMachineState *vms) +{ + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + DeviceState *dev =3D g_ptr_array_index(vms->smmuv3_devices, i); + + platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev= ), + SYS_BUS_DEVICE(dev)); + } +} + static void virt_machine_done(Notifier *notifier, void *data) { @@ -1848,6 +1867,9 @@ void virt_machine_done(Notifier *notifier, void *data) if (vms->cxl_devices_state.is_enabled) { cxl_fmws_link_targets(&error_fatal); } + + virt_smmuv3_dev_link_cmdqv(vms); + /* * If the user provided a dtb, we assume the dynamic sysbus nodes * already are integrated there. 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charset="utf-8" From: Nicolin Chen Replace the stub implementation with real vIOMMU allocation for Tegra241 CMDQV. Allocate a matching vEVENTQ together with the vIOMMU, since it is specific to the Tegra241 CMDQV vIOMMU and used to receive CMDQV events. Free both objects on teardown. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 1 + hw/arm/tegra241-cmdqv.c | 46 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 2a34a4b6b4..fa0aa3ab04 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -30,6 +30,7 @@ typedef struct Tegra241CMDQV { SMMUv3AccelState *s_accel; MemoryRegion mmio_cmdqv; qemu_irq irq; + IOMMUFDVeventq *veventq; } Tegra241CMDQV; =20 const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index ccd3c6d275..2f1084b55f 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -25,13 +25,57 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + IOMMUFDViommu *viommu =3D accel->viommu; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + + if (!viommu) { + return; + } + if (veventq) { + close(veventq->veventq_fd); + iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id); + g_free(veventq); + cmdqv->veventq =3D NULL; + } + iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id); } =20 static bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, uint32_t *out_viommu_id, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; + uint32_t viommu_id, veventq_id, veventq_fd; + IOMMUFDVeventq *veventq; + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, + idev->hwpt_id, &cmdqv->cmdqv_data, + sizeof(cmdqv->cmdqv_data), &viommu_i= d, + errp)) { + return false; + } + + if (!iommufd_backend_alloc_veventq(idev->iommufd, viommu_id, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + 1 << 16, &veventq_id, &veventq_fd, + errp)) { + error_append_hint(errp, "Tegra241 CMDQV: failed to alloc veventq"); + goto free_viommu; + } + + veventq =3D g_new(IOMMUFDVeventq, 1); + veventq->veventq_id =3D veventq_id; + veventq->veventq_fd =3D veventq_fd; + cmdqv->veventq =3D veventq; + + *out_viommu_id =3D viommu_id; + return true; + +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu_id); return false; } =20 --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250747; cv=pass; d=zohomail.com; s=zohoarc; b=F1ZuSHqeDUN2/QXppyZL9G+8HgcoR6FdazTYc8869mLndfA5UsItu/dgdcCifZPhE+u7qTiph/jcpNmz6L8ddsOw/P7aI7qzzi2KNH/p6m+tIgVfSTOAdeRpCOWOa9bM43vaLE1cDRamtmVLAJjm2XyYiLR/v7wKtDlncjBaVp0= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; 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charset="utf-8" From: Nicolin Chen Tegra241 CMDQV exposes control and status registers in the CMDQ-V Config page (offset [0x0, 0x10000)) used to configure virtual command queue allocation and interrupt behavior. Add read/write emulation for the CMDQ-V Config region ([CMDQV_BASE, CMDQV_CMDQ_BASE]), backed by a simple register cache. This includes CONFIG, PARAM, STATUS, VI error and interrupt maps, CMDQ allocation map and the VINTF0 related registers defined in the CMDQ-V Config space. Only VINTF0 is supported; VINTF1-63 are not. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 127 +++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 163 ++++++++++++++++++++++++++++++++++++++-- hw/arm/trace-events | 4 + 3 files changed, 288 insertions(+), 6 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index fa0aa3ab04..965670066d 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,10 +10,14 @@ #ifndef HW_ARM_TEGRA241_CMDQV_H #define HW_ARM_TEGRA241_CMDQV_H =20 +#include "hw/core/registerfields.h" + #define CMDQV_VER 1 #define CMDQV_NUM_CMDQ_LOG2 1 #define CMDQV_NUM_SID_PER_VI_LOG2 4 =20 +#define TEGRA241_CMDQV_MAX_CMDQ (1U << CMDQV_NUM_CMDQ_LOG2) + /* * Tegra241 CMDQV MMIO layout (64KB pages) * @@ -31,8 +35,131 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDVeventq *veventq; + + /* Register Cache */ + uint32_t config; + uint32_t param; + uint32_t status; + uint32_t vi_err_map[2]; + uint32_t vi_int_mask[2]; + uint32_t cmdq_err_map[4]; + uint32_t cmdq_alloc_map[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vintf_config; + uint32_t vintf_status; + uint32_t vintf_sid_match[16]; + uint32_t vintf_sid_replace[16]; + uint32_t vintf_cmdq_err_map[4]; } Tegra241CMDQV; =20 +/* CMDQ-V Config page registers (offset 0x00000) */ +REG32(CONFIG, 0x0) +FIELD(CONFIG, CMDQV_EN, 0, 1) +FIELD(CONFIG, CMDQV_PER_CMD_OFFSET, 1, 3) +FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) +FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) +FIELD(CONFIG, CONS_DRAM_EN, 20, 1) + +REG32(PARAM, 0x4) +FIELD(PARAM, CMDQV_VER, 0, 4) +FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) +FIELD(PARAM, CMDQV_NUM_VI_LOG2, 8, 4) +FIELD(PARAM, CMDQV_NUM_SID_PER_VI_LOG2, 12, 4) + +REG32(STATUS, 0x8) +FIELD(STATUS, CMDQV_ENABLED, 0, 1) + +/* SMMU_CMDQV_VI_ERR_MAP_0/1 definitions */ +#define A_VI_ERR_MAP_0 0x14 +#define A_VI_ERR_MAP_1 0x18 +#define V_VI_ERR_MAP_NO_ERROR (0) +#define V_VI_ERR_MAP_ERROR (1) + +/* SMMU_CMDQV_VI_INT_MASK_0/1 definitions */ +#define A_VI_INT_MASK 0x1c +#define A_VI_INT_MASK_1 0x20 +#define V_VI_INT_MASK_NOT_MASKED (0) +#define V_VI_INT_MASK_MASKED (1) + +/* SMMU_CMDQV_CMDQ_ERR_MAP_0-3 definitions */ +#define A_CMDQ_ERR_MAP_0 0x24 +#define A_CMDQ_ERR_MAP_1 0x28 +#define A_CMDQ_ERR_MAP_2 0x2c +#define A_CMDQ_ERR_MAP_3 0x30 + +/* + * CMDQ_ALLOC_MAP: one entry per physical VCMDQ. Hardware supports up to 1= 28 + * entries (CMDQV_NUM_CMDQ_LOG2=3D7), but QEMU only exposes + * TEGRA241_CMDQV_MAX_CMDQ (=3D2) VCMDQs per VM so only entries 0 and 1 are + * defined here. + */ +/* 2 identical register entries */ +#define SMMU_CMDQV_CMDQ_ALLOC_MAP_(i) \ + REG32(CMDQ_ALLOC_MAP_##i, 0x200 + i * 4) \ + FIELD(CMDQ_ALLOC_MAP_##i, ALLOC, 0, 1) \ + FIELD(CMDQ_ALLOC_MAP_##i, LVCMDQ, 1, 7) \ + FIELD(CMDQ_ALLOC_MAP_##i, VIRT_INTF_INDX, 15, 6) + +SMMU_CMDQV_CMDQ_ALLOC_MAP_(0) +SMMU_CMDQV_CMDQ_ALLOC_MAP_(1) + + +/* Only VINTF0 is exposed to the guest; vintf =3D 0 */ +#define SMMU_CMDQV_VINTFi_CONFIG_(vi) \ + REG32(VINTF##vi##_CONFIG, 0x1000 + vi * 0x100) \ + FIELD(VINTF##vi##_CONFIG, ENABLE, 0, 1) \ + FIELD(VINTF##vi##_CONFIG, VMID, 1, 16) \ + FIELD(VINTF##vi##_CONFIG, HYP_OWN, 17, 1) + +SMMU_CMDQV_VINTFi_CONFIG_(0) + +#define SMMU_CMDQV_VINTFi_STATUS_(vi) \ + REG32(VINTF##vi##_STATUS, 0x1004 + vi * 0x100) \ + FIELD(VINTF##vi##_STATUS, ENABLE_OK, 0, 1) \ + FIELD(VINTF##vi##_STATUS, STATUS, 1, 3) \ + FIELD(VINTF##vi##_STATUS, VI_NUM_LVCMDQ, 16, 8) + +SMMU_CMDQV_VINTFi_STATUS_(0) + +#define V_VINTF_STATUS_NO_ERROR (0 << 1) +#define V_VINTF_STATUS_VCMDQ_ERROR (1 << 1) + +/* + * SID_MATCH/SID_REPLACE: 16 entries per VINTF (CMDQV_NUM_SID_PER_VI_LOG2= =3D4). + * vintf =3D 0, 16 identical register entries + */ +#define SMMU_CMDQV_VINTFi_SID_MATCH_(vi, j) \ + REG32(VINTF##vi##_SID_MATCH_##j, 0x1040 + j * 4 + vi * 0x100) \ + FIELD(VINTF##vi##_SID_MATCH_##j, ENABLE, 0, 1) \ + FIELD(VINTF##vi##_SID_MATCH_##j, VIRT_SID, 1, 20) + +SMMU_CMDQV_VINTFi_SID_MATCH_(0, 0) +/* Omitting [0][1~14] as not being directly called */ +SMMU_CMDQV_VINTFi_SID_MATCH_(0, 15) + +/* vintf =3D 0, 16 identical register entries */ +#define SMMU_CMDQV_VINTFi_SID_REPLACE_(vi, j) \ + REG32(VINTF##vi##_SID_REPLACE_##j, 0x1080 + j * 4 + vi * 0x100) \ + FIELD(VINTF##vi##_SID_REPLACE_##j, PHYS_SID, 0, 20) + +SMMU_CMDQV_VINTFi_SID_REPLACE_(0, 0) +/* Omitting [0][1~14] as not being directly called */ +SMMU_CMDQV_VINTFi_SID_REPLACE_(0, 15) + +/* + * LVCMDQ_ERR_MAP: hardware defines 4 registers per VINTF (offset + * 0x10c0..0x10cc), each covering 32 logical VCMDQs. All 4 are accessible + * by the guest. With TEGRA241_CMDQV_MAX_CMDQ=3D2 only MAP_0 bits [1:0] + * carry meaningful error state; MAP_1..MAP_3 always read as 0. + * vintf =3D 0, 4 identical register entries + */ +#define SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(vi, j) \ + REG32(VINTF##vi##_LVCMDQ_ERR_MAP_##j, 0x10c0 + j * 4 + vi * 0x100) \ + FIELD(VINTF##vi##_LVCMDQ_ERR_MAP_##j, LVCMDQ_ERR_MAP, 0, 32) + +SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(0, 0) +/* MAP_1 and MAP_2 omitted; not referenced directly */ +SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(0, 3) + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 2f1084b55f..3b08ed0ff3 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,19 +8,170 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" =20 #include "hw/arm/smmuv3.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" +#include "trace.h" =20 -static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned = size) +static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv, + hwaddr offset) { - return 0; + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + return cmdqv->vintf_config; + case A_VINTF0_STATUS: + return cmdqv->vintf_status; + case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15: + i =3D (offset - A_VINTF0_SID_MATCH_0) / 4; + return cmdqv->vintf_sid_match[i]; + case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15: + i =3D (offset - A_VINTF0_SID_REPLACE_0) / 4; + return cmdqv->vintf_sid_replace[i]; + case A_VINTF0_LVCMDQ_ERR_MAP_0 ... A_VINTF0_LVCMDQ_ERR_MAP_3: + i =3D (offset - A_VINTF0_LVCMDQ_ERR_MAP_0) / 4; + return cmdqv->vintf_cmdq_err_map[i]; + default: + /* + * GLB_FILT_CFG_0 (offset 0xC) and GLB_FILT_DATA_0 (offset 0x10) a= re + * filter config and filter data registers. They are not required = for + * normal VINTF operation and are not emulated. + */ + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + return 0; + } +} + +static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv, + hwaddr offset, uint64_t valu= e) +{ + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + /* + * Mask out HYP_OWN on guest writes. This bit selects Hypervisor (= 1) vs + * Guest (0) ownership of the CMDQ. Force it to 0 so the VINTF alw= ays + * remains guest-owned. + */ + value &=3D ~R_VINTF0_CONFIG_HYP_OWN_MASK; + + cmdqv->vintf_config =3D value; + if (value & R_VINTF0_CONFIG_ENABLE_MASK) { + cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + } else { + cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; + } + break; + case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15: + i =3D (offset - A_VINTF0_SID_MATCH_0) / 4; + cmdqv->vintf_sid_match[i] =3D value; + break; + case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15: + i =3D (offset - A_VINTF0_SID_REPLACE_0) / 4; + cmdqv->vintf_sid_replace[i] =3D value; + break; + default: + /* + * GLB_FILT_CFG_0 (offset 0xC) and GLB_FILT_DATA_0 (offset 0x10) a= re + * filter config and filter data registers. They are not required = for + * normal VINTF operation and are not emulated. + */ + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + return; + } +} + +static uint64_t tegra241_cmdqv_read_mmio(void *opaque, hwaddr offset, + unsigned size) +{ + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + uint64_t val =3D 0; + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x%x)\n", __func= __, + offset, TEGRA241_CMDQV_IO_LEN); + goto out; + } + + switch (offset) { + case A_CONFIG: + val =3D cmdqv->config; + break; + case A_PARAM: + val =3D cmdqv->param; + break; + case A_STATUS: + val =3D cmdqv->status; + break; + case A_VI_ERR_MAP_0 ... A_VI_ERR_MAP_1: + val =3D cmdqv->vi_err_map[(offset - A_VI_ERR_MAP_0) / 4]; + break; + case A_VI_INT_MASK ... A_VI_INT_MASK_1: + val =3D cmdqv->vi_int_mask[(offset - A_VI_INT_MASK) / 4]; + break; + case A_CMDQ_ERR_MAP_0 ... A_CMDQ_ERR_MAP_3: + val =3D cmdqv->cmdq_err_map[(offset - A_CMDQ_ERR_MAP_0) / 4]; + break; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: + val =3D cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4]; + break; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + val =3D tegra241_cmdqv_config_vintf_read(cmdqv, offset); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + } + +out: + trace_tegra241_cmdqv_read_mmio(offset, val, size); + return val; } =20 -static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t val= ue, - unsigned size) +static void tegra241_cmdqv_write_mmio(void *opaque, hwaddr offset, + uint64_t value, unsigned size) { + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x%x)\n", __func= __, + offset, TEGRA241_CMDQV_IO_LEN); + goto out; + } + + switch (offset) { + case A_CONFIG: + cmdqv->config =3D value; + if (value & R_CONFIG_CMDQV_EN_MASK) { + cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; + } else { + cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; + } + break; + case A_VI_INT_MASK ... A_VI_INT_MASK_1: + cmdqv->vi_int_mask[(offset - A_VI_INT_MASK) / 4] =3D value; + break; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: + cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; + break; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + } + +out: + trace_tegra241_cmdqv_write_mmio(offset, value, size); } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) @@ -84,8 +235,8 @@ static void tegra241_cmdqv_reset(SMMUv3State *s) } =20 static const MemoryRegionOps mmio_cmdqv_ops =3D { - .read =3D tegra241_cmdqv_read, - .write =3D tegra241_cmdqv_write, + .read =3D tegra241_cmdqv_read_mmio, + .write =3D tegra241_cmdqv_write_mmio, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 3457536fb0..8c61d66a26 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -72,6 +72,10 @@ smmuv3_accel_unset_iommu_device(int devfn, uint32_t devi= d) "devfn=3D0x%x (idev dev smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1= , uint64_t ste_0) "vSID=3D0x%x hwpt_id=3D0x%x ste=3D%"PRIx64":%"PRIx64 smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_i= d) "vSID=3D0x%x ste type=3D%s hwpt_id=3D0x%x" =20 +# tegra241-cmdqv +tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" +tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Tegra241 CMDQV exposes per-VCMDQ register windows through two MMIO apertures: CMDQV_CMDQ_BASE (0x10000/0x20000): VCMDQ Page0/Page1 CMDQV_VI_CMDQ_BASE (0x30000/0x40000): VINTF VCMDQ Page0/Page1 VINTF Page0 (0x30000) and VCMDQ Page0 (0x10000) are hardware aliases addressing the same underlying registers. Add read emulation for both apertures, backed by a register cache. VINTF Page0 reads are translated to their VCMDQ Page0 equivalent and served from the same cached state. Once IOMMU_HW_QUEUE_ALLOC and viommu_mmap are wired up in a subsequent patch, Page0 register reads will be served directly from the hardware backed mmap'd page instead of the cache. Page1 registers are always served from cache. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 185 ++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 73 ++++++++++++++++ 2 files changed, 258 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 965670066d..b8bd8cd8ff 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -29,6 +29,13 @@ */ #define TEGRA241_CMDQV_IO_LEN 0x50000 =20 +/* CMDQV MMIO aperture bases and VCMDQ stride */ +#define CMDQV_VCMDQ_PAGE0_BASE 0x10000 /* CMDQV_CMDQ_BASE */ +#define CMDQV_VCMDQ_PAGE1_BASE 0x20000 +#define CMDQV_VINTF_PAGE0_BASE 0x30000 /* CMDQV_VI_CMDQ_BASE */ +#define CMDQV_VINTF_PAGE1_BASE 0x40000 +#define CMDQV_VCMDQ_STRIDE 0x80 + typedef struct Tegra241CMDQV { struct iommu_viommu_tegra241_cmdqv cmdqv_data; SMMUv3AccelState *s_accel; @@ -49,6 +56,14 @@ typedef struct Tegra241CMDQV { uint32_t vintf_sid_match[16]; uint32_t vintf_sid_replace[16]; uint32_t vintf_cmdq_err_map[4]; + uint32_t vcmdq_cons_indx[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_prod_indx[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_config[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_status[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_gerror[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_gerrorn[TEGRA241_CMDQV_MAX_CMDQ]; + uint64_t vcmdq_base[TEGRA241_CMDQV_MAX_CMDQ]; + uint64_t vcmdq_cons_indx_base[TEGRA241_CMDQV_MAX_CMDQ]; } Tegra241CMDQV; =20 /* CMDQ-V Config page registers (offset 0x00000) */ @@ -160,6 +175,176 @@ SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(0, 0) /* MAP_1 and MAP_2 omitted; not referenced directly */ SMMU_CMDQV_VINTFi_LVCMDQ_ERR_MAP_(0, 3) =20 +/* + * VCMDQ register windows. + * + * Page 0 @ 0x10000: VCMDQ control and status registers + * Page 1 @ 0x20000: VCMDQ base and DRAM address registers + */ +#define A_VCMDQi_CONS_INDX(i) \ + REG32(VCMDQ##i##_CONS_INDX, 0x10000 + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +A_VCMDQi_CONS_INDX(0) +A_VCMDQi_CONS_INDX(1) + +#define V_VCMDQ_CONS_INDX_ERR_CERROR_NONE 0 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_OPCODE 1 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ABT 2 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ATC_INV_SYNC 3 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_ACCESS 4 + +#define A_VCMDQi_PROD_INDX(i) \ + REG32(VCMDQ##i##_PROD_INDX, 0x10000 + 0x4 + i * 0x80) \ + FIELD(VCMDQ##i##_PROD_INDX, WR, 0, 20) + +A_VCMDQi_PROD_INDX(0) +A_VCMDQi_PROD_INDX(1) + +#define A_VCMDQi_CONFIG(i) \ + REG32(VCMDQ##i##_CONFIG, 0x10000 + 0x8 + i * 0x80) \ + FIELD(VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +A_VCMDQi_CONFIG(0) +A_VCMDQi_CONFIG(1) + +#define A_VCMDQi_STATUS(i) \ + REG32(VCMDQ##i##_STATUS, 0x10000 + 0xc + i * 0x80) \ + FIELD(VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +A_VCMDQi_STATUS(0) +A_VCMDQi_STATUS(1) + +#define A_VCMDQi_GERROR(i) \ + REG32(VCMDQ##i##_GERROR, 0x10000 + 0x10 + i * 0x80) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +A_VCMDQi_GERROR(0) +A_VCMDQi_GERROR(1) + +#define A_VCMDQi_GERRORN(i) \ + REG32(VCMDQ##i##_GERRORN, 0x10000 + 0x14 + i * 0x80) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +A_VCMDQi_GERRORN(0) +A_VCMDQi_GERRORN(1) + +#define A_VCMDQi_BASE_L(i) \ + REG32(VCMDQ##i##_BASE_L, 0x20000 + i * 0x80) \ + FIELD(VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ + FIELD(VCMDQ##i##_BASE_L, ADDR, 5, 27) + +A_VCMDQi_BASE_L(0) +A_VCMDQi_BASE_L(1) + +#define A_VCMDQi_BASE_H(i) \ + REG32(VCMDQ##i##_BASE_H, 0x20000 + 0x4 + i * 0x80) \ + FIELD(VCMDQ##i##_BASE_H, ADDR, 0, 16) + +A_VCMDQi_BASE_H(0) +A_VCMDQi_BASE_H(1) + +#define A_VCMDQi_CONS_INDX_BASE_DRAM_L(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, 0x20000 + 0x8 + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +A_VCMDQi_CONS_INDX_BASE_DRAM_L(0) +A_VCMDQi_CONS_INDX_BASE_DRAM_L(1) + +#define A_VCMDQi_CONS_INDX_BASE_DRAM_H(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, 0x20000 + 0xc + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +A_VCMDQi_CONS_INDX_BASE_DRAM_H(0) +A_VCMDQi_CONS_INDX_BASE_DRAM_H(1) + +/* + * VI_VCMDQ register windows (VCMDQs mapped via VINTF). + * + * Page 0 @ 0x30000: VI_VCMDQ control and status registers + * Page 1 @ 0x40000: VI_VCMDQ base and DRAM address registers + */ +#define A_VI_VCMDQi_CONS_INDX(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX, 0x30000 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +A_VI_VCMDQi_CONS_INDX(0) +A_VI_VCMDQi_CONS_INDX(1) + +#define A_VI_VCMDQi_PROD_INDX(i) \ + REG32(VI_VCMDQ##i##_PROD_INDX, 0x30000 + 0x4 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_PROD_INDX, WR, 0, 20) + +A_VI_VCMDQi_PROD_INDX(0) +A_VI_VCMDQi_PROD_INDX(1) + +#define A_VI_VCMDQi_CONFIG(i) \ + REG32(VI_VCMDQ##i##_CONFIG, 0x30000 + 0x8 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +A_VI_VCMDQi_CONFIG(0) +A_VI_VCMDQi_CONFIG(1) + +#define A_VI_VCMDQi_STATUS(i) \ + REG32(VI_VCMDQ##i##_STATUS, 0x30000 + 0xc + i * 0x80) \ + FIELD(VI_VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +A_VI_VCMDQi_STATUS(0) +A_VI_VCMDQi_STATUS(1) + +#define A_VI_VCMDQi_GERROR(i) \ + REG32(VI_VCMDQ##i##_GERROR, 0x30000 + 0x10 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +A_VI_VCMDQi_GERROR(0) +A_VI_VCMDQi_GERROR(1) + +#define A_VI_VCMDQi_GERRORN(i) \ + REG32(VI_VCMDQ##i##_GERRORN, 0x30000 + 0x14 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +A_VI_VCMDQi_GERRORN(0) +A_VI_VCMDQi_GERRORN(1) + +#define A_VI_VCMDQi_BASE_L(i) \ + REG32(VI_VCMDQ##i##_BASE_L, 0x40000 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ + FIELD(VI_VCMDQ##i##_BASE_L, ADDR, 5, 27) + +A_VI_VCMDQi_BASE_L(0) +A_VI_VCMDQi_BASE_L(1) + +#define A_VI_VCMDQi_BASE_H(i) \ + REG32(VI_VCMDQ##i##_BASE_H, 0x40000 + 0x4 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_BASE_H, ADDR, 0, 16) + +A_VI_VCMDQi_BASE_H(0) +A_VI_VCMDQi_BASE_H(1) + +#define A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, 0x40000 + 0x8 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(0) +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(1) + +#define A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, 0x40000 + 0xc + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(0) +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(1) + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 3b08ed0ff3..35e6f0bbd6 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -15,6 +15,46 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +/* + * Read a VCMDQ register using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * All VCMDQ accesses return cached registers. + */ +static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr off= set0, + int index) +{ + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + return cmdqv->vcmdq_cons_indx[index]; + case A_VCMDQ0_PROD_INDX: + return cmdqv->vcmdq_prod_indx[index]; + case A_VCMDQ0_CONFIG: + return cmdqv->vcmdq_config[index]; + case A_VCMDQ0_STATUS: + return cmdqv->vcmdq_status[index]; + case A_VCMDQ0_GERROR: + return cmdqv->vcmdq_gerror[index]; + case A_VCMDQ0_GERRORN: + return cmdqv->vcmdq_gerrorn[index]; + case A_VCMDQ0_BASE_L: + return cmdqv->vcmdq_base[index]; + case A_VCMDQ0_BASE_H: + return cmdqv->vcmdq_base[index] >> 32; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + return cmdqv->vcmdq_cons_indx_base[index]; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + return cmdqv->vcmdq_cons_indx_base[index] >> 32; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled read access at 0x%" PRIx64 "\n", + __func__, offset0); + return 0; + } +} + static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv, hwaddr offset) { @@ -92,6 +132,7 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque, h= waddr offset, { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; uint64_t val =3D 0; + int index; =20 if (offset >=3D TEGRA241_CMDQV_IO_LEN) { qemu_log_mask(LOG_UNIMP, @@ -125,6 +166,38 @@ static uint64_t tegra241_cmdqv_read_mmio(void *opaque,= hwaddr offset, case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: val =3D tegra241_cmdqv_config_vintf_read(cmdqv, offset); break; + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: + /* + * VINTF Page0 registers have the same per-VCMDQ layout as the + * VCMDQ Page0 registers. Translate the VINTF aperture offset to t= he + * equivalent VCMDQ aperture offset, then fall through to reuse the + * common VCMDQ decoding logic below. + */ + offset -=3D CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: + /* + * Decode a per-VCMDQ register access. + * + * The hardware supports up to 128 identical VCMDQ instances; we + * currently expose TEGRA241_CMDQV_MAX_CMDQ (=3D 2). Each VCMDQ + * occupies a CMDQV_VCMDQ_STRIDE-byte window within the page. + * + * Extract the VCMDQ index and normalize to the VCMDQ0_* register + * offset. A single helper services all instances via @index. + */ + index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; + return tegra241_cmdqv_read_vcmdq(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index); + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above */ + offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same decode logic as VCMDQ Page0 case above */ + index =3D (offset - CMDQV_VCMDQ_PAGE1_BASE) / CMDQV_VCMDQ_STRIDE; + return tegra241_cmdqv_read_vcmdq(cmdqv, + offset - index * CMDQV_VCMDQ_STRIDE, index); default: qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", __func__, offset); --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250717; cv=pass; d=zohomail.com; s=zohoarc; b=Wz6CmJKyhEZSLawF8WlJxzYy1eiO/YlISiGW2GHrQ1Is4cq3aCMRUqJcdUhVa0Q+JZqwHoVm/ATNmLhWfsse88g5czo2katwjZOBrXvR/luV1SVS3Cy5MjSN+6SYeTH4v7r/Fz77jjLskY6Ru3oayI9NjbzkX+aPm5MfoeBCNbU= ARC-Message-Signature: i=2; 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charset="utf-8" From: Nicolin Chen This is the write side counterpart of the VCMDQ read emulation. Add write handling for both CMDQV_CMDQ_BASE and CMDQV_VI_CMDQ_BASE apertures using the same index decoding and VINTF-to-VCMDQ translation logic as the read path. VINTF aperture writes are translated to their CMDQV_CMDQ_BASE equivalent and update the same cached state. Page1 registers (BASE, CONS_INDX_BASE) always update the cache. Once IOMMU_HW_QUEUE_ALLOC and viommu_mmap are wired up in a subsequent patch, Page0 register writes will be forwarded to the hardware-backed mmap'd page. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 99 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 35e6f0bbd6..d4ba2ada92 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -55,6 +55,70 @@ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV = *cmdqv, hwaddr offset0, } } =20 +/* + * Write a VCMDQ register using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + */ +static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset= 0, + int index, uint64_t value, + unsigned size) +{ + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + cmdqv->vcmdq_cons_indx[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_PROD_INDX: + cmdqv->vcmdq_prod_indx[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_CONFIG: + if (value & R_VCMDQ0_CONFIG_CMDQ_EN_MASK) { + cmdqv->vcmdq_status[index] |=3D R_VCMDQ0_STATUS_CMDQ_EN_OK_MAS= K; + } else { + cmdqv->vcmdq_status[index] &=3D ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MA= SK; + } + cmdqv->vcmdq_config[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_GERRORN: + cmdqv->vcmdq_gerrorn[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_BASE_L: + if (size =3D=3D 8) { + cmdqv->vcmdq_base[index] =3D value; + } else { + cmdqv->vcmdq_base[index] =3D + (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) | + (value & 0xffffffffULL); + } + return; + case A_VCMDQ0_BASE_H: + cmdqv->vcmdq_base[index] =3D + (cmdqv->vcmdq_base[index] & 0xffffffffULL) | + ((uint64_t)value << 32); + return; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + if (size =3D=3D 8) { + cmdqv->vcmdq_cons_indx_base[index] =3D value; + } else { + cmdqv->vcmdq_cons_indx_base[index] =3D + (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffff00000000UL= L) | + (value & 0xffffffffULL); + } + return; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + cmdqv->vcmdq_cons_indx_base[index] =3D + (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffffULL) | + ((uint64_t)value << 32); + return; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled write access at 0x%" PRIx64 "\n", + __func__, offset0); + return; + } +} + static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv, hwaddr offset) { @@ -212,6 +276,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, uint64_t value, unsigned size) { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + int index; =20 if (offset >=3D TEGRA241_CMDQV_IO_LEN) { qemu_log_mask(LOG_UNIMP, @@ -238,6 +303,40 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hw= addr offset, case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); break; + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: + /* + * VINTF Page0 registers have the same per-VCMDQ layout as the + * VCMDQ Page0 registers. Translate the VINTF aperture offset to t= he + * equivalent VCMDQ aperture offset, then fall through to reuse the + * common VCMDQ decoding logic below. + */ + offset -=3D CMDQV_VINTF_PAGE0_BASE - CMDQV_VCMDQ_PAGE0_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: + /* + * Decode a per-VCMDQ register access. + * + * The hardware supports up to 128 identical VCMDQ instances; we + * currently expose TEGRA241_CMDQV_MAX_CMDQ (=3D 2). Each VCMDQ + * occupies a CMDQV_VCMDQ_STRIDE-byte window within the page. + * + * Extract the VCMDQ index and normalize to the VCMDQ0_* register + * offset. A single helper services all instances via @index. + */ + index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; + tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STR= IDE, + index, value, size); + break; + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same VINTF-to-VCMDQ translation as VINTF Page0 case above */ + offset -=3D CMDQV_VINTF_PAGE1_BASE - CMDQV_VCMDQ_PAGE1_BASE; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... 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charset="utf-8" From: Nicolin Chen The CMDQ-V CMDQ pages provide a VM wide view of all VCMDQs, while the VINTF pages expose a logical view local to a given VINTF. Although real hardware may support multiple VINTFs, the kernel currently exposes a single VINTF per VM. The kernel provides an mmap offset for the VINTF Page0 region during vIOMMU allocation. However, the logical-to-physical association between VCMDQs and a VINTF is only established after HW_QUEUE allocation. Prior to that, the mapped Page0 does not back any real VCMDQ state. When VINTF is enabled, mmap the kernel provided Page0 region and set ENABLE_OK only if the mmap succeeds. Unmap it when VINTF is disabled. This prepares the VINTF mapping in advance of subsequent patches that add VCMDQ allocation support. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 3 +++ hw/arm/tegra241-cmdqv.c | 47 ++++++++++++++++++++++++++++++++++++++--- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index b8bd8cd8ff..88572ad939 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -18,6 +18,8 @@ =20 #define TEGRA241_CMDQV_MAX_CMDQ (1U << CMDQV_NUM_CMDQ_LOG2) =20 +#define VINTF_PAGE_SIZE 0x10000 + /* * Tegra241 CMDQV MMIO layout (64KB pages) * @@ -42,6 +44,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDVeventq *veventq; + void *vintf_page0; =20 /* Register Cache */ uint32_t config; diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index d4ba2ada92..cdd941cec9 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -119,6 +119,39 @@ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *= cmdqv, hwaddr offset0, } } =20 +static bool +tegra241_cmdqv_munmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **errp) +{ + if (!cmdqv->vintf_page0) { + return true; + } + + if (munmap(cmdqv->vintf_page0, VINTF_PAGE_SIZE) < 0) { + error_setg_errno(errp, errno, "Failed to unmap VINTF page0"); + return false; + } + cmdqv->vintf_page0 =3D NULL; + return true; +} + +static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **= errp) +{ + IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; + + if (cmdqv->vintf_page0) { + return true; + } + + if (!iommufd_backend_viommu_mmap(viommu->iommufd, viommu->viommu_id, + VINTF_PAGE_SIZE, + cmdqv->cmdqv_data.out_vintf_mmap_offs= et, + &cmdqv->vintf_page0, errp)) { + return false; + } + + return true; +} + static uint64_t tegra241_cmdqv_config_vintf_read(Tegra241CMDQV *cmdqv, hwaddr offset) { @@ -151,7 +184,8 @@ static uint64_t tegra241_cmdqv_config_vintf_read(Tegra2= 41CMDQV *cmdqv, } =20 static void tegra241_cmdqv_config_vintf_write(Tegra241CMDQV *cmdqv, - hwaddr offset, uint64_t valu= e) + hwaddr offset, uint64_t valu= e, + Error **errp) { int i; =20 @@ -166,8 +200,11 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241= CMDQV *cmdqv, =20 cmdqv->vintf_config =3D value; if (value & R_VINTF0_CONFIG_ENABLE_MASK) { - cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + if (tegra241_cmdqv_mmap_vintf_page0(cmdqv, errp)) { + cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + } } else { + tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; } break; @@ -276,6 +313,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, uint64_t value, unsigned size) { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + Error *local_err =3D NULL; int index; =20 if (offset >=3D TEGRA241_CMDQV_IO_LEN) { @@ -301,7 +339,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; break; case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: - tegra241_cmdqv_config_vintf_write(cmdqv, offset, value); + tegra241_cmdqv_config_vintf_write(cmdqv, offset, value, &local_err= ); break; case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: /* @@ -343,6 +381,9 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, } =20 out: + if (local_err) { + error_report_err(local_err); + } trace_tegra241_cmdqv_write_mmio(offset, value, size); } =20 --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250931; cv=pass; d=zohomail.com; s=zohoarc; b=UOvZeXmmy1vUTnlhy4E2Dkk+at1zkPkbN7J9+o8ZfKyOI+iasJzuFgLUnq7abmnBb0ibinlTFtMs34YBH64RIvqwA/stI1fNh2y0gFHS4Ce0+NSCJ6G9TPFK2uEsWgHI3m++qdteRdP91MOkL1VgdUpSnssh27gFvSZHI3OkSdw= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776250931; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Introduce address_space_is_ram(), a helper to determine whether a guest physical address resolves to a RAM-backed MemoryRegion within an AddressSpace. Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/memory.h | 10 ++++++++++ system/physmem.c | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/system/memory.h b/include/system/memory.h index d7b18b632d..7aed255e81 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -2841,6 +2841,16 @@ bool address_space_access_valid(AddressSpace *as, hw= addr addr, hwaddr len, */ bool address_space_is_io(AddressSpace *as, hwaddr addr); =20 +/** + * address_space_is_ram: check whether a guest physical address whithin + * an address space is RAM. + * + * @as: #AddressSpace to be accessed + * @addr: address within that address space + */ + +bool address_space_is_ram(AddressSpace *as, hwaddr addr); + /* address_space_map: map a physical memory region into a host virtual add= ress * * May map a subset of the requested range, given by and returned in @plen. diff --git a/system/physmem.c b/system/physmem.c index 4e26f1a1d4..b67dde80fb 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3674,6 +3674,17 @@ bool address_space_is_io(AddressSpace *as, hwaddr ad= dr) return !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); 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charset="utf-8" From: Nicolin Chen Add support for allocating IOMMUFD hardware queues when the guest programs the VCMDQ BASE registers. VCMDQ_EN is part of the VCMDQ_CONFIG register, which is accessed through the VINTF Page0 region. A subsequent patch maps this region directly into the guest address space, so QEMU does not trap writes to VCMDQ_CONFIG. Since VCMDQ_EN writes are not trapped, QEMU cannot allocate the hardware queue based on that bit. Instead, allocate the IOMMUFD hardware queue when the guest writes a VCMDQ BASE register with a valid RAM-backed address and when CMDQV and VINTF are enabled. If a hardware queue was previously allocated for the same VCMDQ, free it before reallocation. Writes with invalid addresses are ignored. All allocated VCMDQs are freed when CMDQV or VINTF is disabled. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 11 +++++++ hw/arm/tegra241-cmdqv.c | 70 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 78 insertions(+), 3 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 88572ad939..039d86374f 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -44,6 +44,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDVeventq *veventq; + IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; void *vintf_page0; =20 /* Register Cache */ @@ -348,6 +349,16 @@ A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(1) A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(0) A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(1) =20 +static inline bool tegra241_cmdq_enabled(Tegra241CMDQV *cmdqv) +{ + return cmdqv->status & R_STATUS_CMDQV_ENABLED_MASK; +} + +static inline bool tegra241_vintf_enabled(Tegra241CMDQV *cmdqv) +{ + return cmdqv->vintf_status & R_VINTF0_STATUS_ENABLE_OK_MASK; +} + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index cdd941cec9..b5f2f74cf2 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -15,6 +15,66 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) +{ + IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; + IOMMUFDHWqueue *vcmdq =3D cmdqv->vcmdq[index]; + + if (!vcmdq) { + return; + } + iommufd_backend_free_id(viommu->iommufd, vcmdq->hw_queue_id); + g_free(vcmdq); + cmdqv->vcmdq[index] =3D NULL; +} + +static void tegra241_cmdqv_free_all_vcmdq(Tegra241CMDQV *cmdqv) +{ + /* Free in reverse order to avoid "resource busy" error */ + for (int i =3D (TEGRA241_CMDQV_MAX_CMDQ - 1); i >=3D 0; i--) { + tegra241_cmdqv_free_vcmdq(cmdqv, i); + } +} + +static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index, + Error **errp) +{ + SMMUv3AccelState *accel =3D cmdqv->s_accel; + uint64_t base_mask =3D (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK | + (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32; + uint64_t addr =3D cmdqv->vcmdq_base[index] & base_mask; + uint64_t log2 =3D cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_= MASK; + uint64_t size =3D 1ULL << (log2 + 4); + IOMMUFDViommu *viommu =3D accel->viommu; + IOMMUFDHWqueue *hw_queue; + uint32_t hw_queue_id; + + /* Ignore any invalid address. This may come as part of reset etc. */ + if (!address_space_is_ram(&address_space_memory, addr) || + !address_space_is_ram(&address_space_memory, addr + size - 1)) { + return true; + } + + if (!tegra241_cmdq_enabled(cmdqv) || !tegra241_vintf_enabled(cmdqv)) { + return true; + } + + tegra241_cmdqv_free_vcmdq(cmdqv, index); + + if (!iommufd_backend_alloc_hw_queue(viommu->iommufd, viommu->viommu_id, + IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV, + index, addr, size, &hw_queue_id, + errp)) { + return false; + } + hw_queue =3D g_new(IOMMUFDHWqueue, 1); + hw_queue->hw_queue_id =3D hw_queue_id; + hw_queue->viommu =3D viommu; + cmdqv->vcmdq[index] =3D hw_queue; + + return true; +} + /* * Read a VCMDQ register using VCMDQ0_* offsets. * @@ -63,7 +123,7 @@ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV = *cmdqv, hwaddr offset0, */ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset= 0, int index, uint64_t value, - unsigned size) + unsigned size, Error **errp) { switch (offset0) { case A_VCMDQ0_CONS_INDX: @@ -91,11 +151,13 @@ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *= cmdqv, hwaddr offset0, (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) | (value & 0xffffffffULL); } + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); return; case A_VCMDQ0_BASE_H: cmdqv->vcmdq_base[index] =3D (cmdqv->vcmdq_base[index] & 0xffffffffULL) | ((uint64_t)value << 32); + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); return; case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: if (size =3D=3D 8) { @@ -204,6 +266,7 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241C= MDQV *cmdqv, cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; } } else { + tegra241_cmdqv_free_all_vcmdq(cmdqv); tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; } @@ -329,6 +392,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, if (value & R_CONFIG_CMDQV_EN_MASK) { cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; } else { + tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; } break; @@ -363,7 +427,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, */ index =3D (offset - CMDQV_VCMDQ_PAGE0_BASE) / CMDQV_VCMDQ_STRIDE; tegra241_cmdqv_write_vcmdq(cmdqv, offset - index * CMDQV_VCMDQ_STR= IDE, - index, value, size); + index, value, size, &local_err); break; case A_VI_VCMDQ0_BASE_L ... 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charset="utf-8" Introduce tegra241_cmdqv_vintf_ptr() to route VCMDQ register accesses through the mmap'd VINTF page0 backing once a hardware queue has been allocated. There are two QEMU trapped MMIO apertures for VCMDQ registers: - Direct VCMDQ aperture (offset 0x10000) - VINTF Page0 (offset 0x30000) These are hardware aliases: they address the same underlying registers. A subsequent patch maps the VINTF aperture as a guest-direct RAM region; in this patch both remain QEMU-trapped. VCMDQ register accesses operate in one of two mutually exclusive modes, depending on whether a hardware queue (IOMMU_HW_QUEUE_ALLOC) has been allocated for the VCMDQ: Pre-alloc: vintf_ptr is NULL. Both apertures use QEMU's register cache. Hardware is not yet engaged; Post-alloc: vintf_ptr is valid. Both QEMU trapped apertures access registers directly via the mmap'd vintf_page0 pointer, bypassing the cache. Hardware is the single source of truth. The pre-to-post-alloc transition is triggered by the BASE register write that initiates IOMMU_HW_QUEUE_ALLOC. No cache-to-hardware synchronisation is needed at transition time. The hardware mandated init sequence requires BASE to be written first; PROD_INDX, CONS_INDX and CONFIG.CMDQ_EN are programmed only after BASE and are therefore always post-alloc. Any pre-alloc writes to those registers update only the register cache, which is discarded at the transition. CMDQV acceleration only becomes active once the guest enables VINTF and programs the VCMDQ BASE register. Until then, all VCMDQ accesses are served from the emulated register cache with no real hardware command processing. This matches the CMDQV hardware specification: if the logical CMDQ index does not map to any allocated Virtual CMDQ, "the access is dropped with no Fault/Interrupt". Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 48 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index b5f2f74cf2..eb619e1134 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -75,17 +75,45 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *c= mdqv, int index, return true; } =20 +static inline uint32_t *tegra241_cmdqv_vintf_ptr(Tegra241CMDQV *cmdqv, + int index, hwaddr offset0) +{ + if (!cmdqv->vcmdq[index] || !cmdqv->vintf_page0) { + return NULL; + } + return (uint32_t *)(cmdqv->vintf_page0 + + (index * CMDQV_VCMDQ_STRIDE) + + (offset0 - CMDQV_VCMDQ_PAGE0_BASE)); +} + /* * Read a VCMDQ register using VCMDQ0_* offsets. * * The caller normalizes the MMIO offset such that @offset0 always refers * to a VCMDQ0_* register, while @index selects the VCMDQ instance. * - * All VCMDQ accesses return cached registers. + * If the VCMDQ is allocated and VINTF page0 is mmap'd, read directly + * from the VINTF page0 backing. Otherwise, fall back to cached state. */ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr off= set0, int index) { + uint32_t *ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, offset0); + + if (ptr) { + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + case A_VCMDQ0_PROD_INDX: + case A_VCMDQ0_CONFIG: + case A_VCMDQ0_STATUS: + case A_VCMDQ0_GERROR: + case A_VCMDQ0_GERRORN: + return *ptr; + default: + break; + } + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: return cmdqv->vcmdq_cons_indx[index]; @@ -120,11 +148,29 @@ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMD= QV *cmdqv, hwaddr offset0, * * The caller normalizes the MMIO offset such that @offset0 always refers * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * If the VCMDQ is allocated and VINTF page0 is mmap'd, write directly + * to the VINTF page0 backing. Otherwise, update cached state. */ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset= 0, int index, uint64_t value, unsigned size, Error **errp) { + uint32_t *ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, offset0); + + if (ptr) { + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + case A_VCMDQ0_PROD_INDX: + case A_VCMDQ0_CONFIG: + case A_VCMDQ0_GERRORN: + *ptr =3D (uint32_t)value; + return; + default: + break; + } + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: cmdqv->vcmdq_cons_indx[index] =3D (uint32_t)value; --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250795; cv=pass; d=zohomail.com; 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charset="utf-8" Some RAM device regions created with memory_region_init_ram_device_ptr() are not intended to be P2P DMA targets. The VFIO listener currently treats all RAM device regions as DMA capable and attempts to map them into the IOMMU. For regions without dma-buf backing this fails and prints warnings such as: IOMMU_IOAS_MAP failed: Bad address, PCI BAR? Introduce a MemoryRegion flag (ram_device_skip_iommu_map) to mark RAM device regions that should not be IOMMU mapped. When set, the VFIO listener skips DMA mapping for that region. Signed-off-by: Shameer Kolothum --- include/system/memory.h | 2 ++ hw/vfio/listener.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/include/system/memory.h b/include/system/memory.h index 7aed255e81..9df15e833a 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -864,6 +864,8 @@ struct MemoryRegion { =20 /* For devices designed to perform re-entrant IO into their own IO MRs= */ bool disable_reentrancy_guard; + /* RAM device region that does not require IOMMU mapping for P2P */ + bool ram_device_skip_iommu_map; }; =20 struct IOMMUMemoryRegion { diff --git a/hw/vfio/listener.c b/hw/vfio/listener.c index 960da9e0a9..32d33a740a 100644 --- a/hw/vfio/listener.c +++ b/hw/vfio/listener.c @@ -614,6 +614,11 @@ void vfio_container_region_add(VFIOContainer *bcontain= er, } } =20 + if (memory_region_is_ram_device(section->mr) && + section->mr->ram_device_skip_iommu_map) { + return; + } + ret =3D vfio_container_dma_map(bcontainer, iova, int128_get64(llsize), vaddr, section->readonly, section->mr); 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charset="utf-8" From: Nicolin Chen Once a VCMDQ is allocated, map the mmap'd vintf_page0 region directly into the guest-visible MMIO space at offset 0x30000 as a RAM-backed MemoryRegion. This eliminates QEMU trapping for hot-path CONS/PROD index updates. After this patch, the two VCMDQ apertures use different access paths: the direct aperture (0x10000) remains QEMU-trapped and writes via vintf_ptr, while the VI aperture (0x30000) is a direct guest RAM mapping. Both paths write to the same underlying vintf_page0 memory, so no synchronisation between the apertures is needed. The mapping is installed lazily on first successful VCMDQ hardware queue allocation and removed when CMDQV or VINTF is disabled. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 1 + hw/arm/tegra241-cmdqv.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 039d86374f..2befa6205e 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -46,6 +46,7 @@ typedef struct Tegra241CMDQV { IOMMUFDVeventq *veventq; IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; void *vintf_page0; + MemoryRegion *mr_vintf_page0; =20 /* Register Cache */ uint32_t config; diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index eb619e1134..bf989dd51f 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -15,6 +15,40 @@ #include "tegra241-cmdqv.h" #include "trace.h" =20 +static void tegra241_cmdqv_guest_unmap_vintf_page0(Tegra241CMDQV *cmdqv) +{ + if (!cmdqv->mr_vintf_page0) { + return; + } + + memory_region_del_subregion(&cmdqv->mmio_cmdqv, cmdqv->mr_vintf_page0); + object_unparent(OBJECT(cmdqv->mr_vintf_page0)); + g_free(cmdqv->mr_vintf_page0); + cmdqv->mr_vintf_page0 =3D NULL; +} + +static void tegra241_cmdqv_guest_map_vintf_page0(Tegra241CMDQV *cmdqv) +{ + char *name; + + if (cmdqv->mr_vintf_page0) { + return; + } + + name =3D g_strdup_printf("%s vintf-page0", + memory_region_name(&cmdqv->mmio_cmdqv)); + cmdqv->mr_vintf_page0 =3D g_malloc0(sizeof(*cmdqv->mr_vintf_page0)); + memory_region_init_ram_device_ptr(cmdqv->mr_vintf_page0, + memory_region_owner(&cmdqv->mmio_cmd= qv), + name, VINTF_PAGE_SIZE, + cmdqv->vintf_page0); + cmdqv->mr_vintf_page0->ram_device_skip_iommu_map =3D true; + memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv, + CMDQV_VINTF_PAGE0_BASE, + cmdqv->mr_vintf_page0, 1); + g_free(name); +} + static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) { IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; @@ -72,6 +106,7 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cm= dqv, int index, hw_queue->viommu =3D viommu; cmdqv->vcmdq[index] =3D hw_queue; =20 + tegra241_cmdqv_guest_map_vintf_page0(cmdqv); return true; } =20 @@ -312,6 +347,7 @@ static void tegra241_cmdqv_config_vintf_write(Tegra241C= MDQV *cmdqv, cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; } } else { + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; @@ -438,6 +474,7 @@ static void tegra241_cmdqv_write_mmio(void *opaque, hwa= ddr offset, if (value & R_CONFIG_CMDQV_EN_MASK) { cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; } else { + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; } --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Move the vEVENTQ read and validation logic into a common helper smmuv3_accel_event_read_validate(). The helper performs the read(), checks for overflow and short reads, validates the sequence number, and updates the sequence state. This helper can be reused for Tegra241 CMDQV vEVENTQ support in a subsequent patch. Error handling is slightly adjusted: instead of reporting errors directly in the read handler, the helper now returns errors via Error **. Sequence gaps are reported as warnings. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 2 ++ hw/arm/smmuv3-accel-stubs.c | 11 ++++++ hw/arm/smmuv3-accel.c | 67 ++++++++++++++++++++++--------------- 3 files changed, 53 insertions(+), 27 deletions(-) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 28bceca061..448f47c0ca 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -71,6 +71,8 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd= , SMMUDevice *sdev, Error **errp); void smmuv3_accel_idr_override(SMMUv3State *s); bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp= ); void smmuv3_accel_reset(SMMUv3State *s); =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c index c08caa6fa4..e8f08dc833 100644 --- a/hw/arm/smmuv3-accel-stubs.c +++ b/hw/arm/smmuv3-accel-stubs.c @@ -41,6 +41,17 @@ void smmuv3_accel_idr_override(SMMUv3State *s) { } =20 +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp) +{ + return true; +} + +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp) +{ + return true; +} + void smmuv3_accel_reset(SMMUv3State *s) { } diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 9068e65e2b..230f608f03 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -436,47 +436,60 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void= *cmd, SMMUDevice *sdev, sizeof(Cmd), &entry_num, cmd, errp); } =20 -static void smmuv3_accel_event_read(void *opaque) +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp) { - SMMUv3State *s =3D opaque; - IOMMUFDVeventq *veventq =3D s->s_accel->veventq; - struct { - struct iommufd_vevent_header hdr; - struct iommu_vevent_arm_smmuv3 vevent; - } buf; - enum iommu_veventq_type type =3D IOMMU_VEVENTQ_TYPE_ARM_SMMUV3; - uint32_t id =3D veventq->veventq_id; uint32_t last_seq =3D veventq->last_event_seq; + uint32_t id =3D veventq->veventq_id; + struct iommufd_vevent_header *hdr; ssize_t bytes; =20 - bytes =3D read(veventq->veventq_fd, &buf, sizeof(buf)); + bytes =3D read(veventq->veventq_fd, buf, size); if (bytes <=3D 0) { if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { - return; + return true; } - error_report_once("vEVENTQ(type %u id %u): read failed (%m)", type= , id); - return; + error_setg(errp, "vEVENTQ(type %u id %u): read failed (%m)", type,= id); + return false; } - - if (bytes =3D=3D sizeof(buf.hdr) && - (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { - error_report_once("vEVENTQ(type %u id %u): overflowed", type, id); + hdr =3D (struct iommufd_vevent_header *)buf; + if (bytes =3D=3D sizeof(*hdr) && + (hdr->flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { + error_setg(errp, "vEVENTQ(type %u id %u): overflowed", type, id); veventq->event_start =3D false; - return; + return false; } - if (bytes < sizeof(buf)) { - error_report_once("vEVENTQ(type %u id %u): short read(%zd/%zd byte= s)", - type, id, bytes, sizeof(buf)); - return; + if (bytes < size) { + error_setg(errp, "vEVENTQ(type %u id %u): short read(%zd/%zd bytes= )", + type, id, bytes, size); + return false; } - /* Check sequence in hdr for lost events if any */ - if (veventq->event_start && (buf.hdr.sequence - last_seq !=3D 1)) { - error_report_once("vEVENTQ(type %u id %u): lost %u event(s)", - type, id, buf.hdr.sequence - last_seq - 1); + if (veventq->event_start && (hdr->sequence - last_seq !=3D 1)) { + warn_report("vEVENTQ(type %u id %u): lost %u event(s)", + type, id, hdr->sequence - last_seq - 1); } - veventq->last_event_seq =3D buf.hdr.sequence; + veventq->last_event_seq =3D hdr->sequence; veventq->event_start =3D true; + return true; +} + +static void smmuv3_accel_event_read(void *opaque) +{ + SMMUv3State *s =3D opaque; + IOMMUFDVeventq *veventq =3D s->s_accel->veventq; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_arm_smmuv3 vevent; + } buf; + Error *local_err =3D NULL; + + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, &= buf, + sizeof(buf), &local_err)) { + warn_report_err_once(local_err); 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Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5653 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=skolothumtho@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1776250719764154100 Install an event handler on the CMDQV vEVENTQ fd to read and propagate host received CMDQV errors to the guest. The handler runs in QEMU=E2=80=99s main loop, using a non-blocking fd regis= tered via qemu_set_fd_handler(). Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 55 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 2 files changed, 56 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index bf989dd51f..9c2fc02b92 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -11,6 +11,7 @@ #include "qemu/log.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/core/irq.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" #include "trace.h" @@ -534,6 +535,43 @@ out: trace_tegra241_cmdqv_write_mmio(offset, value, size); } =20 +static void tegra241_cmdqv_event_read(void *opaque) +{ + Tegra241CMDQV *cmdqv =3D opaque; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_tegra241_cmdqv vevent; + } buf; + Error *local_err =3D NULL; + + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQ= V, + &buf, sizeof(buf), &local_err)) { + warn_report_err_once(local_err); + return; + } + + if (buf.vevent.lvcmdq_err_map[0] || buf.vevent.lvcmdq_err_map[1]) { + cmdqv->vintf_cmdq_err_map[0] =3D + buf.vevent.lvcmdq_err_map[0] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[1] =3D + (buf.vevent.lvcmdq_err_map[0] >> 32) & 0xffffffff; + cmdqv->vintf_cmdq_err_map[2] =3D + buf.vevent.lvcmdq_err_map[1] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[3] =3D + (buf.vevent.lvcmdq_err_map[1] >> 32) & 0xffffffff; + for (int i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D cmdqv->vintf_cmdq_err_map[i]; + } + cmdqv->vi_err_map[0] |=3D 0x1; + qemu_irq_pulse(cmdqv->irq); + trace_tegra241_cmdqv_err_map( + cmdqv->vintf_cmdq_err_map[3], cmdqv->vintf_cmdq_err_map[2], + cmdqv->vintf_cmdq_err_map[1], cmdqv->vintf_cmdq_err_map[0]); + } +} + static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { SMMUv3AccelState *accel =3D s->s_accel; @@ -545,6 +583,7 @@ static void tegra241_cmdqv_free_viommu(SMMUv3State *s) return; } if (veventq) { + qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL); close(veventq->veventq_fd); iommufd_backend_free_id(viommu->iommufd, veventq->veventq_id); g_free(veventq); @@ -560,6 +599,7 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; uint32_t viommu_id, veventq_id, veventq_fd; IOMMUFDVeventq *veventq; + int flags; =20 if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, @@ -577,14 +617,29 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMU= DeviceIOMMUFD *idev, goto free_viommu; } =20 + flags =3D fcntl(veventq_fd, F_GETFL); + if (flags < 0) { + error_setg(errp, "Failed to get flags for vEVENTQ fd"); + goto free_veventq; + } + if (fcntl(veventq_fd, F_SETFL, O_NONBLOCK | flags) < 0) { + error_setg(errp, "Failed to set O_NONBLOCK on vEVENTQ fd"); + goto free_veventq; + } + veventq =3D g_new(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; cmdqv->veventq =3D veventq; =20 + /* Set up event handler for veventq fd */ + qemu_set_fd_handler(veventq_fd, tegra241_cmdqv_event_read, NULL, cmdqv= ); *out_viommu_id =3D viommu_id; return true; =20 +free_veventq: + close(veventq_fd); + iommufd_backend_free_id(idev->iommufd, veventq_id); free_viommu: iommufd_backend_free_id(idev->iommufd, viommu_id); return false; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 8c61d66a26..fd6441bfa7 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -75,6 +75,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS # tegra241-cmdqv tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" +tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Introduce a reset handler for the Tegra241 CMDQV and initialize its register state. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 2 ++ hw/arm/tegra241-cmdqv.c | 50 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 3 files changed, 53 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 2befa6205e..b2a444daef 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -79,6 +79,8 @@ FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) FIELD(CONFIG, CONS_DRAM_EN, 20, 1) =20 +#define V_CONFIG_RESET 0x00020403 + REG32(PARAM, 0x4) FIELD(PARAM, CMDQV_VER, 0, 4) FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 9c2fc02b92..af68add2f0 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,6 +8,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/log.h" =20 #include "hw/arm/smmuv3.h" @@ -645,8 +646,57 @@ free_viommu: return false; } =20 +static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) +{ + int i; + + cmdqv->config =3D V_CONFIG_RESET; + cmdqv->param =3D FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2, + CMDQV_NUM_CMDQ_LOG2); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VI_= LOG2, + CMDQV_NUM_SID_PER_VI_LOG2); + trace_tegra241_cmdqv_init_regs(cmdqv->param); + cmdqv->status =3D R_STATUS_CMDQV_ENABLED_MASK; + for (i =3D 0; i < 2; i++) { + cmdqv->vi_err_map[i] =3D 0; + cmdqv->vi_int_mask[i] =3D 0; + cmdqv->cmdq_err_map[i] =3D 0; + } + cmdqv->cmdq_err_map[2] =3D 0; + cmdqv->cmdq_err_map[3] =3D 0; + cmdqv->vintf_config =3D 0; + cmdqv->vintf_status =3D 0; + for (i =3D 0; i < 4; i++) { + cmdqv->vintf_cmdq_err_map[i] =3D 0; + } + for (i =3D 0; i < TEGRA241_CMDQV_MAX_CMDQ; i++) { + cmdqv->cmdq_alloc_map[i] =3D 0; + cmdqv->vcmdq_cons_indx[i] =3D 0; + cmdqv->vcmdq_prod_indx[i] =3D 0; + cmdqv->vcmdq_config[i] =3D 0; + cmdqv->vcmdq_status[i] =3D 0; + cmdqv->vcmdq_gerror[i] =3D 0; + cmdqv->vcmdq_gerrorn[i] =3D 0; + cmdqv->vcmdq_base[i] =3D 0; + cmdqv->vcmdq_cons_indx_base[i] =3D 0; + } +} + static void tegra241_cmdqv_reset(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + + if (!cmdqv) { + return; + } + + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); + tegra241_cmdqv_munmap_vintf_page0(cmdqv, NULL); + tegra241_cmdqv_free_all_vcmdq(cmdqv); + + tegra241_cmdqv_init_regs(s, cmdqv); } =20 static const MemoryRegionOps mmio_cmdqv_ops =3D { diff --git a/hw/arm/trace-events b/hw/arm/trace-events index fd6441bfa7..6f602b9eda 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -76,6 +76,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS tegra241_cmdqv_read_mmio(uint64_t offset, uint64_t val, unsigned size) "of= fset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_write_mmio(uint64_t offset, uint64_t val, unsigned size) "o= ffset: 0x%"PRIx64" val: 0x%"PRIx64" size: 0x%x" tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" +tegra241_cmdqv_init_regs(uint32_t param) "hw info received. param: 0x%04X" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen CMDQV HW reads guest queue memory in its host physical address setup via IOMMUFD. This requires the guest queue memory is not only contiguous in guest PA space but also in host PA space. With Tegra241 CMDQV enabled, we must only advertise a CMDQS that the host can safely back with physically contiguous memory. Allowing a queue larger than the host page size could cause the hardware to DMA across page boundaries, leading to faults. Walk the RAMBlock list to find the smallest memory-backend page size, then limit IDR1.CMDQS so the guest cannot configure a command queue that exceeds that contiguous backing. Fall back to the real host page size if no memory-backend RAM blocks are found. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index af68add2f0..2870886783 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -14,6 +14,9 @@ #include "hw/arm/smmuv3.h" #include "hw/core/irq.h" #include "smmuv3-accel.h" +#include "smmuv3-internal.h" +#include "system/ramblock.h" +#include "system/ramlist.h" #include "tegra241-cmdqv.h" #include "trace.h" =20 @@ -646,9 +649,38 @@ free_viommu: return false; } =20 +static size_t tegra241_cmdqv_min_ram_pagesize(void) +{ + RAMBlock *rb; + size_t pg, min_pg =3D SIZE_MAX; + + RAMBLOCK_FOREACH(rb) { + MemoryRegion *mr =3D rb->mr; + + /* Only consider real RAM regions */ + if (!mr || !memory_region_is_ram(mr)) { + continue; + } + + /* Skip RAM regions that are not backed by a memory-backend */ + if (!object_dynamic_cast(mr->owner, TYPE_MEMORY_BACKEND)) { + continue; + } + + pg =3D qemu_ram_pagesize(rb); + if (pg && pg < min_pg) { + min_pg =3D pg; + } + } + + return (min_pg =3D=3D SIZE_MAX) ? qemu_real_host_page_size() : min_pg; +} + static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) { int i; + size_t pgsize; + uint32_t val; =20 cmdqv->config =3D V_CONFIG_RESET; cmdqv->param =3D FIELD_DP32(0, PARAM, CMDQV_VER, CMDQV_VER); @@ -681,6 +713,15 @@ static void tegra241_cmdqv_init_regs(SMMUv3State *s, T= egra241CMDQV *cmdqv) cmdqv->vcmdq_base[i] =3D 0; cmdqv->vcmdq_cons_indx_base[i] =3D 0; } + + /* + * CMDQ must not cross a physical RAM backend page. Adjust CMDQS so the + * queue fits entirely within the smallest backend page size, ensuring + * the command queue is physically contiguous in host memory. + */ + pgsize =3D tegra241_cmdqv_min_ram_pagesize(); + val =3D FIELD_EX32(s->idr[1], IDR1, CMDQS); + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, MIN(ctz64(pgsize) - 4= , val)); } =20 static void tegra241_cmdqv_reset(SMMUv3State *s) --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250951; cv=pass; d=zohomail.com; s=zohoarc; b=NroD7KMfiit5q0PCXi1eqV+zTk2YZDSkNfzJXfGeuCL/XgkxLf6vFK4Z4AKxNKY+Uc/Z3kL1f4OjAJan7/CtBVvgRrwpWcTkpQCpH2LCGsQWD3Uyr05eFTQWkIPdZqLnPxH33s+znBavK0ZgKu1PYLOvbg+s+6ju8ssNl8mh8I4= ARC-Message-Signature: i=2; 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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F69.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5915 Received-SPF: permerror client-ip=2a01:111:f403:c105::1; envelope-from=skolothumtho@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1776250952672158500 Content-Type: text/plain; charset="utf-8" Add an "identifier" property to the SMMUv3 device and use it when building the ACPI IORT SMMUv3 node Identifier field. This avoids relying on device enumeration order and provides a stable per-device identifier. A subsequent patch will use the same identifier when generating the DSDT description for Tegra241 CMDQV, ensuring that the IORT and DSDT entries refer to the same SMMUv3 instance. The identifier is assigned at pre-plug time, accounting for the ITS Group node that build_iort() places before SMMUv3 nodes in the IORT table, so that identifiers are globally unique across all IORT nodes. No functional change: IORT blob content for bios-tables qtest is identical to before. Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/hw/arm/smmuv3.h | 1 + hw/arm/smmuv3.c | 2 ++ hw/arm/virt-acpi-build.c | 5 ++++- hw/arm/virt.c | 12 ++++++++++++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index aa6a79237a..0fce564619 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -64,6 +64,7 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + uint8_t identifier; =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 682d89c3ea..1d6fdd776c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2144,6 +2144,8 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + /* Identifier used for ACPI IORT SMMUv3 (and DSDT for CMDQV) generatio= n */ + DEFINE_PROP_UINT8("identifier", SMMUv3State, identifier, 0), DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 521443de87..65ccc96349 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -342,6 +342,7 @@ static int iort_idmap_compare(gconstpointer a, gconstpo= inter b) typedef struct AcpiIortSMMUv3Dev { int irq; hwaddr base; + uint8_t id; GArray *rc_smmu_idmaps; /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; @@ -404,6 +405,7 @@ static int populate_smmuv3_dev(VirtMachineState *vms, G= Array *sdev_blob) &error_abort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); + sdev.id =3D object_property_get_uint(obj, "identifier", &error_abo= rt); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -630,7 +632,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); build_append_int_noprefix(table_data, node_size, 2); /* Length */ build_append_int_noprefix(table_data, 4, 1); /* Revision */ - build_append_int_noprefix(table_data, id++, 4); /* Identifier */ + build_append_int_noprefix(table_data, sdev->id, 4); /* Identifier = */ + id++; /* advance shared counter for RC/RMR node uniqueness */ /* Number of ID mappings */ build_append_int_noprefix(table_data, smmu_mapping_count, 4); /* Reference to ID Array */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6c5e51af37..22d6b9eec9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -240,6 +240,9 @@ static MemMapEntry extended_memmap[] =3D { /* Any CXL Fixed memory windows come here */ }; =20 +/* Counts SMMUv3 devices plugged; used to assign stable IORT identifiers */ +static uint8_t smmuv3_dev_id; + static const int a15irqmap[] =3D { [VIRT_UART0] =3D 1, [VIRT_RTC] =3D 2, @@ -3226,6 +3229,15 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, OBJECT(vms->sysmem), NULL); object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->secure_sysmem), NULL); + /* + * In build_iort(), the ITS node(id=3D0) precedes SMMUv3 nodes + * when present. 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charset="utf-8" Introduce a SMMUv3AccelCmdqvType enum and a helper to query the CMDQV implementation type associated with an accelerated SMMUv3 instance. A subsequent patch will use this helper when generating the Tegra241 CMDQV DSDT. Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 7 +++++++ hw/arm/smmuv3-accel-stubs.c | 5 +++++ hw/arm/smmuv3-accel.c | 12 ++++++++++++ hw/arm/tegra241-cmdqv.c | 6 ++++++ 4 files changed, 30 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 448f47c0ca..3ed94ed05c 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -16,6 +16,11 @@ #include #endif =20 +typedef enum SMMUv3AccelCmdqvType { + SMMUV3_CMDQV_NONE =3D 0, + SMMUV3_CMDQV_TEGRA241, +} SMMUv3AccelCmdqvType; + /* * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to * support multiple VCMDQs with virtualization capabilities. @@ -29,6 +34,7 @@ typedef struct SMMUv3AccelCmdqvOps { uint32_t *out_viommu_id, Error **errp); void (*free_viommu)(SMMUv3State *s); + SMMUv3AccelCmdqvType (*get_type)(void); void (*reset)(SMMUv3State *s); } SMMUv3AccelCmdqvOps; =20 @@ -74,5 +80,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **e= rrp); bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, void *buf, size_t size, Error **errp= ); void smmuv3_accel_reset(SMMUv3State *s); +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj); =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c index e8f08dc833..08de01d909 100644 --- a/hw/arm/smmuv3-accel-stubs.c +++ b/hw/arm/smmuv3-accel-stubs.c @@ -55,3 +55,8 @@ bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *vev= entq, uint32_t type, void smmuv3_accel_reset(SMMUv3State *s) { } + +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) +{ + return SMMUV3_CMDQV_NONE; +} diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 230f608f03..a58815ded2 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -1049,6 +1049,18 @@ static void smmuv3_accel_as_init(SMMUv3State *s) address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem"); } =20 +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) +{ + SMMUv3State *s =3D ARM_SMMUV3(obj); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel || !accel->cmdqv_ops || !accel->cmdqv_ops->get_type) { + return SMMUV3_CMDQV_NONE; + } + + return accel->cmdqv_ops->get_type(); +} + bool smmuv3_accel_init(SMMUv3State *s, Error **errp) { SMMUState *bs =3D ARM_SMMU(s); diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 2870886783..71f89abcb4 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -762,6 +762,11 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error = **errp) return true; } =20 +static SMMUv3AccelCmdqvType tegra241_cmdqv_get_type(void) +{ + return SMMUV3_CMDQV_TEGRA241; +} + static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, Error **errp) { @@ -802,6 +807,7 @@ static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D= { .init =3D tegra241_cmdqv_init, .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, .free_viommu =3D tegra241_cmdqv_free_viommu, + .get_type =3D tegra241_cmdqv_get_type, .reset =3D tegra241_cmdqv_reset, }; =20 --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Add ACPI DSDT support for Tegra241 CMDQV when the SMMUv3 instance is created with tegra241-cmdqv. The SMMUv3 device identifier is used as the ACPI _UID. This matches the Identifier field of the corresponding SMMUv3 IORT node, allowing the CMDQV DSDT device to be correctly associated with its SMMU. Signed-off-by: Nicolin Chen Co-developed-by: Shameer Kolothum Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 52 ++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 2 files changed, 53 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 65ccc96349..fbc793d06e 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -65,6 +65,9 @@ #include "target/arm/cpu.h" #include "target/arm/multiprocessing.h" =20 +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + #define ARM_SPI_BASE 32 =20 #define ACPI_BUILD_TABLE_SIZE 0x20000 @@ -1114,6 +1117,51 @@ static void build_fadt_rev6(GArray *table_data, BIOS= Linker *linker, build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); } =20 +static void acpi_dsdt_add_tegra241_cmdqv(Aml *scope, VirtMachineState *vms) +{ + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + Object *obj =3D OBJECT(g_ptr_array_index(vms->smmuv3_devices, i)); + PlatformBusDevice *pbus; + Aml *dev, *crs, *addr; + SysBusDevice *sbdev; + hwaddr base; + uint32_t id; + int irq; + + if (smmuv3_accel_cmdqv_type(obj) !=3D SMMUV3_CMDQV_TEGRA241) { + continue; + } + id =3D object_property_get_uint(obj, "identifier", &error_abort); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + base =3D platform_bus_get_mmio_addr(pbus, sbdev, 1); + base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + irq =3D platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS); + irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + irq +=3D ARM_SPI_BASE; + + dev =3D aml_device("CV%.02u", id); + aml_append(dev, aml_name_decl("_HID", aml_string("NVDA200C"))); + aml_append(dev, aml_name_decl("_UID", aml_int(id))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + crs =3D aml_resource_template(); + addr =3D aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_F= IXED, + AML_CACHEABLE, AML_READ_WRITE, 0x0, base, + base + TEGRA241_CMDQV_IO_LEN - 0x1, 0x0, + TEGRA241_CMDQV_IO_LEN); + aml_append(crs, addr); + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE, + AML_ACTIVE_HIGH, AML_EXCLUSIVE, + (uint32_t *)&irq, 1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); + + trace_virt_acpi_dsdt_tegra241_cmdqv(id, base, irq); + } +} + /* DSDT */ static void build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -1178,6 +1226,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, V= irtMachineState *vms) acpi_dsdt_add_tpm(scope, vms); #endif =20 + if (!vms->legacy_smmuv3_present) { + acpi_dsdt_add_tegra241_cmdqv(scope, vms); + } + aml_append(dsdt, scope); =20 pci0_scope =3D aml_scope("\\_SB.PCI0"); diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 6f602b9eda..e5e4e93324 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -9,6 +9,7 @@ omap1_lpg_led(const char *onoff) "omap1 LPG: LED is %s" =20 # virt-acpi-build.c virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." +virt_acpi_dsdt_tegra241_cmdqv(int smmu_id, uint64_t base, uint32_t irq) "D= SDT: add cmdqv node for (id=3D%d), base=3D0x%" PRIx64 ", irq=3D%d" =20 # smmu-common.c smmu_add_mr(const char *name) "%s" --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1776250930; cv=pass; d=zohomail.com; s=zohoarc; b=aHiFgO+0IlffRnYZIJR8kxDzxwj8ZFPEiF5Zh4Ws4jO6kSvhM4Co+e4nny6N31SjQ3FZTPJvUaB59LjCwk/PrMuSLgPoVHRaONV1p1fRnUUENTkmxLVjB6KghqwpgJTfDRDNrmO1S17kVE/IGQJdGQ9P1bz6HKLQJWqITdX2+F8= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776250930; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" When CMDQV is active, the first cold-plugged VFIO device establishes the viommu to host SMMUv3 association. Block its hot-unplug to preserve this association and the guest's boot time CMDQV configuration. Also abort at machine_done if cmdqv=3Don is requested but no cold-plugged VFIO device was present to initialize it. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 1 + hw/arm/smmuv3-accel.c | 12 ++++++++++++ hw/arm/smmuv3.c | 6 ++++++ 3 files changed, 19 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 3ed94ed05c..c4441d5b3f 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -65,6 +65,7 @@ typedef struct SMMUv3AccelDevice { IOMMUFDVdev *vdev; QLIST_ENTRY(SMMUv3AccelDevice) next; SMMUv3AccelState *s_accel; + Error *unplug_blocker; /* set when CMDQV is active to block hot-unplug= */ } SMMUv3AccelDevice; =20 bool smmuv3_accel_init(SMMUv3State *s, Error **errp); diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index a58815ded2..f381702a08 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -754,6 +754,18 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, return false; } =20 + /* + * CMDQV is active: block hot-unplug of the device that established the + * viommu association. Removing it would cause the vIOMMU to host SMMU= v3 + * association be changed via device hot-plug. + */ + if (s->s_accel->cmdqv_ops) { + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); + error_setg(&accel_dev->unplug_blocker, + "CMDQV is active: removing the device that established = the " + "viommu association would break the guest CMDQV"); + qdev_add_unplug_blocker(DEVICE(pdev), accel_dev->unplug_blocker); + } done: accel_dev->idev =3D idev; accel_dev->s_accel =3D s->s_accel; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 1d6fdd776c..c9ff6298f5 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2020,6 +2020,12 @@ static void smmuv3_machine_done(Notifier *notifier, = void *data) "at least one cold-plugged VFIO device"); exit(1); } + + if (s->cmdqv =3D=3D ON_OFF_AUTO_ON && !accel->cmdqv) { + error_report("arm-smmuv3 cmdqv=3Don requires at least one cold-plu= gged " + "VFIO device"); + exit(1); + } } =20 static void smmu_realize(DeviceState *d, Error **errp) --=20 2.43.0 From nobody Thu Apr 16 17:38:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Introduce a "cmdqv" property to enable Tegra241 CMDQV support. This is only enabled for accelerated SMMUv3 devices. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c9ff6298f5..51b7d01da5 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1993,6 +1993,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ssidsize can only be set if accel=3Don"); return false; } + if (s->cmdqv =3D=3D ON_OFF_AUTO_ON) { + error_setg(errp, "cmdqv can only be enabled if accel=3Don"); + return false; + } return true; } =20 @@ -2161,6 +2165,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_AUTO), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_AUTO), + DEFINE_PROP_ON_OFF_AUTO("cmdqv", SMMUv3State, cmdqv, ON_OFF_AUTO_AUTO), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2200,6 +2205,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Valid range is 0-20, where 0 disables SubstreamID support. " "Defaults to auto. A value greater than 0 is required to enable " "PASID support."); + object_class_property_set_description(klass, "cmdqv", + "Enable/disable CMDQ-Virtualisation support (for accel=3Don)"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, --=20 2.43.0