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Provide an interfaces for machines to describe a discontiguous low/high RAM scheme for this purpose. Signed-off-by: Nicholas Piggin Reviewed-by: Daniel Henrique Barboza Signed-off-by: Joel Stanley --- include/hw/riscv/boot.h | 7 +++++++ hw/riscv/boot.c | 11 +++++++++++ 2 files changed, 18 insertions(+) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f00b3ca12245..115e3222174f 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -28,6 +28,10 @@ #define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" =20 typedef struct RISCVBootInfo { + /* First contiguous RAM region. If size is zero then assume entire RAM= */ + hwaddr ram_low_start; + hwaddr ram_low_size; + ssize_t kernel_size; hwaddr image_low_addr; hwaddr image_high_addr; @@ -43,6 +47,9 @@ bool riscv_is_32bit(RISCVHartArrayState *harts); char *riscv_plic_hart_config_string(int hart_count); =20 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); +void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info, + RISCVHartArrayState *harts, + hwaddr start, hwaddr size); vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, hwaddr firmware_end_addr); hwaddr riscv_find_and_load_firmware(MachineState *machine, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e5490beda007..9babb85b0458 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -69,11 +69,22 @@ char *riscv_plic_hart_config_string(int hart_count) =20 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) { + info->ram_low_start =3D 0; + info->ram_low_size =3D 0; info->kernel_size =3D 0; info->initrd_size =3D 0; info->is_32bit =3D riscv_is_32bit(harts); } =20 +void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info, + RISCVHartArrayState *harts, + hwaddr start, hwaddr size) +{ + riscv_boot_info_init(info, harts); + info->ram_low_start =3D start; + info->ram_low_size =3D size; +} + vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, hwaddr firmware_end_addr) { if (info->is_32bit) { --=20 2.47.3 From nobody Fri Apr 17 20:22:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177623579757663.34967919675205; Tue, 14 Apr 2026 23:49:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wCu3f-0001Lj-HR; Wed, 15 Apr 2026 02:49:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wCu3Z-0001L7-JA for qemu-devel@nongnu.org; Wed, 15 Apr 2026 02:49:01 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wCu3X-0001jD-J8 for qemu-devel@nongnu.org; Wed, 15 Apr 2026 02:49:01 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2b458ca2296so21993605ad.0 for ; Tue, 14 Apr 2026 23:48:59 -0700 (PDT) Received: from donnager-debian.. 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Signed-off-by: Nicholas Piggin Reviewed-by: Daniel Henrique Barboza Signed-off-by: Joel Stanley --- include/hw/riscv/boot.h | 5 ++++- hw/riscv/boot.c | 18 ++++++++++++------ hw/riscv/microchip_pfsoc.c | 6 ++++-- hw/riscv/opentitan.c | 6 ++++-- hw/riscv/shakti_c.c | 6 +++++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 6 ++++-- hw/riscv/virt.c | 7 ++++--- hw/riscv/xiangshan_kmh.c | 6 +++++- 9 files changed, 44 insertions(+), 19 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 115e3222174f..fb90bf12399e 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -53,13 +53,16 @@ void riscv_boot_info_init_discontig_mem(RISCVBootInfo *= info, vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, hwaddr firmware_end_addr); hwaddr riscv_find_and_load_firmware(MachineState *machine, + RISCVBootInfo *info, const char *default_machine_firmware, hwaddr *firmware_load_addr, symbol_fn_t sym_cb); const char *riscv_default_firmware_name(RISCVHartArrayState *harts); char *riscv_find_firmware(const char *firmware_filename, const char *default_machine_firmware); -hwaddr riscv_load_firmware(const char *firmware_filename, +hwaddr riscv_load_firmware(MachineState *machine, + RISCVBootInfo *info, + const char *firmware_filename, hwaddr *firmware_load_addr, symbol_fn_t sym_cb); void riscv_load_kernel(MachineState *machine, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 9babb85b0458..f3857e984240 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -145,6 +145,7 @@ char *riscv_find_firmware(const char *firmware_filename, } =20 hwaddr riscv_find_and_load_firmware(MachineState *machine, + RISCVBootInfo *info, const char *default_machine_firmware, hwaddr *firmware_load_addr, symbol_fn_t sym_cb) @@ -157,7 +158,8 @@ hwaddr riscv_find_and_load_firmware(MachineState *machi= ne, =20 if (firmware_filename) { /* If not "none" load the firmware */ - firmware_end_addr =3D riscv_load_firmware(firmware_filename, + firmware_end_addr =3D riscv_load_firmware(machine, info, + firmware_filename, firmware_load_addr, sym_cb= ); g_free(firmware_filename); } @@ -165,10 +167,13 @@ hwaddr riscv_find_and_load_firmware(MachineState *mac= hine, return firmware_end_addr; } =20 -hwaddr riscv_load_firmware(const char *firmware_filename, +hwaddr riscv_load_firmware(MachineState *machine, + RISCVBootInfo *info, + const char *firmware_filename, hwaddr *firmware_load_addr, symbol_fn_t sym_cb) { + uint64_t mem_size =3D info->ram_low_size ?: machine->ram_size; uint64_t firmware_entry, firmware_end; ssize_t firmware_size; =20 @@ -183,7 +188,7 @@ hwaddr riscv_load_firmware(const char *firmware_filenam= e, =20 firmware_size =3D load_image_targphys_as(firmware_filename, *firmware_load_addr, - current_machine->ram_size, NULL, + mem_size, NULL, NULL); =20 if (firmware_size > 0) { @@ -197,7 +202,7 @@ hwaddr riscv_load_firmware(const char *firmware_filenam= e, static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info) { const char *filename =3D machine->initrd_filename; - uint64_t mem_size =3D machine->ram_size; + uint64_t mem_size =3D info->ram_low_size ?: machine->ram_size; void *fdt =3D machine->fdt; hwaddr start, end; ssize_t size; @@ -243,6 +248,7 @@ void riscv_load_kernel(MachineState *machine, bool load_initrd, symbol_fn_t sym_cb) { + uint64_t mem_size =3D info->ram_low_size ?: machine->ram_size; const char *kernel_filename =3D machine->kernel_filename; ssize_t kernel_size; void *fdt =3D machine->fdt; @@ -274,7 +280,7 @@ void riscv_load_kernel(MachineState *machine, } =20 kernel_size =3D load_image_targphys_as(kernel_filename, kernel_start_a= ddr, - current_machine->ram_size, NULL, = NULL); + mem_size, NULL, NULL); if (kernel_size > 0) { info->kernel_size =3D kernel_size; info->image_low_addr =3D kernel_start_addr; @@ -370,7 +376,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwadd= r dram_size, dtb_start =3D QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); =20 if (dtb_start_limit && (dtb_start < dtb_start_limit)) { - error_report("No enough memory to place DTB after kernel/initrd"); + error_report("Not enough memory to place DTB after kernel/initrd"); exit(1); } =20 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 743f31f00578..1d1ddb05a882 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -618,18 +618,20 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) firmware_load_addr =3D RESET_VECTOR; } =20 + riscv_boot_info_init(&boot_info, &s->soc.u_cpus); + /* Load the firmware if necessary */ firmware_end_addr =3D firmware_load_addr; if (firmware_name) { char *filename =3D riscv_find_firmware(firmware_name, NULL); if (filename) { - firmware_end_addr =3D riscv_load_firmware(filename, + firmware_end_addr =3D riscv_load_firmware(machine, &boot_info, + filename, &firmware_load_addr, N= ULL); g_free(filename); } } =20 - riscv_boot_info_init(&boot_info, &s->soc.u_cpus); if (machine->kernel_filename) { kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr= ); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 309125e854bc..8cd660dd4154 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -99,12 +99,14 @@ static void opentitan_machine_init(MachineState *machin= e) memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_RAM].base, machine->ram); =20 + riscv_boot_info_init(&boot_info, &s->soc.cpus); + if (machine->firmware) { hwaddr firmware_load_addr =3D memmap[IBEX_DEV_RAM].base; - riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); + riscv_load_firmware(machine, &boot_info, machine->firmware, + &firmware_load_addr, NULL); } =20 - riscv_boot_info_init(&boot_info, &s->soc.cpus); if (machine->kernel_filename) { riscv_load_kernel(machine, &boot_info, memmap[IBEX_DEV_RAM].base, diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 49a39b30212d..eb720d9cdf5d 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -45,6 +45,7 @@ static void shakti_c_machine_state_init(MachineState *mst= ate) { ShaktiCMachineState *sms =3D RISCV_SHAKTI_MACHINE(mstate); MemoryRegion *system_memory =3D get_system_memory(); + RISCVBootInfo boot_info; hwaddr firmware_load_addr =3D shakti_c_memmap[SHAKTI_C_RAM].base; =20 /* Initialize SoC */ @@ -57,8 +58,11 @@ static void shakti_c_machine_state_init(MachineState *ms= tate) shakti_c_memmap[SHAKTI_C_RAM].base, mstate->ram); =20 + riscv_boot_info_init(&boot_info, &sms->soc.cpus); + if (mstate->firmware) { - riscv_load_firmware(mstate->firmware, &firmware_load_addr, NULL); + riscv_load_firmware(mstate, &boot_info, mstate->firmware, + &firmware_load_addr, NULL); } =20 /* ROM reset vector */ diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7ec67b256514..4c526f73edf6 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -590,7 +590,8 @@ static void sifive_u_machine_init(MachineState *machine) } =20 firmware_name =3D riscv_default_firmware_name(&s->soc.u_cpus); - firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, + firmware_end_addr =3D riscv_find_and_load_firmware(machine, &boot_info, + firmware_name, &start_addr, NULL); =20 riscv_boot_info_init(&boot_info, &s->soc.u_cpus); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 35c696f891d8..6ee915a8ba4e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -281,9 +281,12 @@ static void spike_board_init(MachineState *machine) } } =20 + riscv_boot_info_init(&boot_info, &s->soc[0]); + /* Load firmware */ if (firmware_name) { - firmware_end_addr =3D riscv_load_firmware(firmware_name, + firmware_end_addr =3D riscv_load_firmware(machine, &boot_info, + firmware_name, &firmware_load_addr, htif_symbol_callback); g_free(firmware_name); @@ -293,7 +296,6 @@ static void spike_board_init(MachineState *machine) create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); =20 /* Load kernel */ - riscv_boot_info_init(&boot_info, &s->soc[0]); if (machine->kernel_filename) { kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr= ); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a1c323e66dfd..4501d5581b62 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1457,7 +1457,10 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) } } =20 - firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, + riscv_boot_info_init(&boot_info, &s->soc[0]); + + firmware_end_addr =3D riscv_find_and_load_firmware(machine, &boot_info, + firmware_name, &start_addr, NULL); =20 pflash_blk0 =3D pflash_cfi01_get_blk(s->flash[0]); @@ -1480,8 +1483,6 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) } } =20 - riscv_boot_info_init(&boot_info, &s->soc[0]); - if (machine->kernel_filename && !kernel_entry) { kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr= ); diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 436e51c1c593..247a0b5d1f21 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -166,6 +166,7 @@ static void xiangshan_kmh_machine_init(MachineState *ma= chine) const MemMapEntry *memmap =3D xiangshan_kmh_memmap; MemoryRegion *system_memory =3D get_system_memory(); hwaddr start_addr =3D memmap[XIANGSHAN_KMH_DRAM].base; + RISCVBootInfo boot_info; =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, @@ -177,13 +178,16 @@ static void xiangshan_kmh_machine_init(MachineState *= machine) memmap[XIANGSHAN_KMH_DRAM].base, machine->ram); =20 + riscv_boot_info_init(&boot_info, &s->soc.cpus); + /* ROM reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc.cpus, start_addr, memmap[XIANGSHAN_KMH_ROM].base, memmap[XIANGSHAN_KMH_ROM].size, 0, 0); if (machine->firmware) { - riscv_load_firmware(machine->firmware, &start_addr, NULL); + riscv_load_firmware(machine, &boot_info, machine->firmware, + &start_addr, NULL); } =20 /* Note: dtb has been integrated into firmware(OpenSBI) when compiling= */ --=20 2.47.3 From nobody Fri Apr 17 20:22:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776235785555940.7556451908688; Tue, 14 Apr 2026 23:49:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wCu3j-0001N9-4t; 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Print a warning in this case because it is likely that it is not intended. Signed-off-by: Nicholas Piggin Reviewed-by: Daniel Henrique Barboza Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index f3857e984240..3ea95c175c14 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -179,13 +179,27 @@ hwaddr riscv_load_firmware(MachineState *machine, =20 g_assert(firmware_filename !=3D NULL); =20 - if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, - &firmware_entry, NULL, &firmware_end, NULL, - 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { + firmware_size =3D load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, + &firmware_entry, NULL, &firmware_end, + NULL, 0, EM_RISCV, 1, 0, NULL, false, + sym_cb); + if (firmware_size > 0) { *firmware_load_addr =3D firmware_entry; return firmware_end; } =20 + if (firmware_size !=3D ELF_LOAD_NOT_ELF) { + /* + * If the user specified an ELF format firmware that could not be + * loaded as an ELF, it's possible that loading it as a binary is + * not what was intended. + */ + warn_report("could not load ELF format firmware '%s' (%s). " + "Attempting to load as binary.", + firmware_filename, + load_elf_strerror(firmware_size)); + } + firmware_size =3D load_image_targphys_as(firmware_filename, *firmware_load_addr, mem_size, NULL, @@ -195,7 +209,8 @@ hwaddr riscv_load_firmware(MachineState *machine, return *firmware_load_addr + firmware_size; } =20 - error_report("could not load firmware '%s'", firmware_filename); + error_report("could not load firmware '%s': %s", firmware_filename, + load_elf_strerror(firmware_size)); exit(1); } =20 --=20 2.47.3 From nobody Fri Apr 17 20:22:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776235785298680.8140018883372; Tue, 14 Apr 2026 23:49:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wCu3m-0001OL-Vc; Wed, 15 Apr 2026 02:49:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wCu3i-0001ND-9z for qemu-devel@nongnu.org; Wed, 15 Apr 2026 02:49:11 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wCu3g-0001lf-Nx for qemu-devel@nongnu.org; Wed, 15 Apr 2026 02:49:10 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2a7a9b8ed69so49059805ad.2 for ; Tue, 14 Apr 2026 23:49:08 -0700 (PDT) Received: from donnager-debian.. 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If no kernel payload is provided to QEMU, the next stage address is NULL, and the riscv virt machine memory map ends up covering the 0 address with the catch all S-mode RWX region and so OpenSBI prints console messages and does not hang until the next stage boot. The soon to be added Tenstorrent Atlantis board address map has RAM starting at 0 and it loads OpenSBI there, so it is M-mode and not accessible by S-mode, tripping the early check and hang. Add a helper to set up a simple payload that gets OpenSBI messages to console. Signed-off-by: Nicholas Piggin Reviewed-by: Daniel Henrique Barboza Signed-off-by: Joel Stanley --- v2: Update commit message to clarfiy that Atlantis isn't in the tree yet include/hw/riscv/boot.h | 2 ++ hw/riscv/boot.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index fb90bf12399e..d1d7258a2179 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -78,6 +78,8 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RIS= CVHartArrayState *harts hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, uint64_t fdt_load_addr); +void riscv_setup_halting_payload(MachineState *machine, + RISCVBootInfo *info, hwaddr addr); void riscv_rom_copy_firmware_info(MachineState *machine, RISCVHartArrayState *harts, hwaddr rom_base, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 3ea95c175c14..fc8a39a8d913 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -518,6 +518,27 @@ void riscv_setup_rom_reset_vec(MachineState *machine, = RISCVHartArrayState *harts kernel_entry); } =20 +/* Simple payload so OpenSBI does not hang early with no output */ +void riscv_setup_halting_payload(MachineState *machine, + RISCVBootInfo *info, hwaddr addr) +{ + int i; + uint32_t payload_vec[] =3D { + 0x10500073, /* 1: wfi */ + 0xffdff06f, /* j 1b */ + }; + /* copy in the payload vector in little_endian byte order */ + for (i =3D 0; i < ARRAY_SIZE(payload_vec); i++) { + payload_vec[i] =3D cpu_to_le32(payload_vec[i]); + } + rom_add_blob_fixed_as("mrom.payload", payload_vec, sizeof(payload_vec), + addr, &address_space_memory); + + info->kernel_size =3D sizeof(payload_vec); + info->image_low_addr =3D addr; + info->image_high_addr =3D info->image_low_addr + info->kernel_size; +} + void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) { CPUState *cs; --=20 2.47.3