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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d63e5c981sm45430513f8f.33.2026.04.14.14.31.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 14 Apr 2026 14:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1776202278; x=1776807078; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LE3VYdOYbKH0q08XzJYCU8QcyOKkKUY9kY9CRanYTyY=; b=EVmb7ByrORc6uVK2jiT9Qi2Ro90P3fS5GBxD7m5Ov3uxdHy4PQt8NxctDir2VX3+Ra yeXKOUTl6nhqUyHnFPD8zX44orinFELMsUKad1T2o3tkvKbMQuuw8iCImt/8xwjCzbQd 9CMSQlxSySmBA//7MXKseK2mvubP7DOJNspzTHTYkEansUMnAZMZ+ckoFdn6zwgBerID rx8KpdEITqt0sgLjl4CsVXiU5BwD+tPkEr83guynClEtWFTvliuBwW1pP4ck7bJ7cMol 6EXjjXfuP1+X3GO7M0/xuVu+VDtfbHruwLhW6E8fUgzpQhFyk2+Q8ioIEb6v601FZD0U n7WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776202278; x=1776807078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LE3VYdOYbKH0q08XzJYCU8QcyOKkKUY9kY9CRanYTyY=; b=llJjQs3jQubrwAfP6qUal7FRtoLQFSgRcowXpbXAl/ZeP+m1mWCrJMa5u9NXgw+b5i HO8pyJBzQCjj52eCyJxz5yQxrDoPgb2Ygg3qlwaPY0s3YcbWbMQId2DcYLw7xc1C18UN 7WLvvspWG3XdSkXQyDqYMAaOGQMh8LRyubPGzlsQ3W3qZM2e9o+36PvYnt6zH0KzyECJ x3Kz2twG1Mgrew7PAzzJsrKsEjjftpxCd8nal4dyk9ZEjTpJdEmy76tMFuvhLSrn0i2k koibv6G0UsNba2XBhPqg/L2dy9/zae8LnjuSBJLrjp6nX4xf83thGdkSIzyIM3lb62hw OPjg== X-Gm-Message-State: AOJu0YzJkfBJUuCr/mKGngr6HhRV57fpi2K830QTi1hMXj0RJFTYmdBS /Md1Xo0YpkueC7lwHjGLbxjDt8tLsgDKFe2Jw5EOusMtikuAsYqDnwK/nNWhO4ISV4cWwZvrysJ ojTONrlw= X-Gm-Gg: AeBDiesqxkZ/D/cH9YbWP95FMqY0dsmdS0jE23CnnY7NCwTTR71PMP3WczuO3NMkl0d FpCwxbbe4RbbmuTKsFq4bZEDl4pNfHsLTfk5rC+5/NkNYnfhpOQvxe0y+4dAm6D0+XZGcE94lGi krM7EaZK1KdvwQqCvv95qKXdzBj4aG5RFxZHY8eLx3WRpn//c2J3hcL2ADyv2ISVk1mhTEQEicg dq+O1GY7jSjbaAVNvoxnK4Z0Ma174kcg4mYZJCIZZe0MTi4QxpYmaLkvnHYslOe0NUi6MKcFgoX fsxGxdO/14h9fs5eJJF/4ASFxakZmBIWY+K+qxw+o3Ubyc0XIOW9mZ1JzN68RrTpMnMNzn6Rq0o 6mY0CyS5v7AasNzPe67egyf7uoGHxMqr22hjewJRC1TpQaE7U+8jQD/mDg3I4EXkIrrjmgdWja5 QQ2VQMX4nBcZvHutTjPskf4lQMoYeBlaBIlND9lEeyaj2966Bi5OT/6IBCaBzTTaMJktML6wX1D 8jredAxsIk= X-Received: by 2002:a05:6000:1379:b0:43d:6787:9934 with SMTP id ffacd0b85a97d-43d67879a5emr18138837f8f.9.1776202278274; Tue, 14 Apr 2026 14:31:18 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Cc: Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v4 1/2] target/mips: Translate MSA vector load opcode (LD.df) Date: Tue, 14 Apr 2026 23:31:07 +0200 Message-ID: <20260414213108.66786-2-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260414213108.66786-1-philmd@linaro.org> References: <20260414213108.66786-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1776202339737154100 Replace helpers by translation. Remove legacy cpu_ld*_data_ra() calls, replacing by tcg_gen_qemu_ld() which allow to respect atomicity. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/msa_helper.h.inc | 1 - target/mips/tcg/msa_helper.c | 69 -------------------------------- target/mips/tcg/msa_translate.c | 44 +++++++++++++++++++- 3 files changed, 43 insertions(+), 71 deletions(-) diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.= h.inc index 4963d1553a0..7ede16f327a 100644 --- a/target/mips/tcg/msa_helper.h.inc +++ b/target/mips/tcg/msa_helper.h.inc @@ -434,7 +434,6 @@ DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) =20 #define MSALDST_PROTO(type) \ -DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) MSALDST_PROTO(b) MSALDST_PROTO(h) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index f554b3d10ee..3a0ba420b9d 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8223,75 +8223,6 @@ static inline uint64_t bswap32x2(uint64_t x) return ror64(bswap64(x), 32); } =20 -void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - uintptr_t ra =3D GETPC(); - uint64_t d0, d1; - - /* Load 8 bytes at a time. Vector element ordering makes this LE. */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); - pwd->d[0] =3D d0; - pwd->d[1] =3D d1; -} - -void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - uintptr_t ra =3D GETPC(); - uint64_t d0, d1; - - /* - * Load 8 bytes at a time. Use little-endian load, then for - * big-endian target, we must then swap the four halfwords. - */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); - if (mips_env_is_bigendian(env)) { - d0 =3D bswap16x4(d0); - d1 =3D bswap16x4(d1); - } - pwd->d[0] =3D d0; - pwd->d[1] =3D d1; -} - -void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - uintptr_t ra =3D GETPC(); - uint64_t d0, d1; - - /* - * Load 8 bytes at a time. Use little-endian load, then for - * big-endian target, we must then bswap the two words. - */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); - if (mips_env_is_bigendian(env)) { - d0 =3D bswap32x2(d0); - d1 =3D bswap32x2(d1); - } - pwd->d[0] =3D d0; - pwd->d[1] =3D d1; -} - -void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - uintptr_t ra =3D GETPC(); - uint64_t d0, d1; - - d0 =3D cpu_ldq_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_data_ra(env, addr + 8, ra); - pwd->d[0] =3D d0; - pwd->d[1] =3D d1; -} - #define MSA_PAGESPAN(x) \ ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) =20 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 82b149922fa..0ad8c2c0dc9 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -758,6 +758,49 @@ TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_= df); TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df); TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df); =20 +static bool trans_LD(DisasContext *ctx, arg_msa_i *a) +{ + TCGv_va addr; + TCGv_i128 d16; + MemOp mop; + int d0 =3D a->wd << 1; + int d1 =3D d0 + 1; + + if (!check_msa_enabled(ctx)) { + return true; + } + + addr =3D tcgv_va_temp_new(); + gen_base_offset_addr(ctx, addr, a->ws, a->sa << a->df); + + mop =3D MO_128 | MO_LE; + if (a->df =3D=3D 0) { + mop |=3D MO_ATOM_NONE; + } else if (a->df =3D=3D 3) { + mop |=3D MO_ATOM_IFALIGN_PAIR; + } else { + mop |=3D MO_ATOM_SUBALIGN; /* slightly stronger than required */ + } + mop |=3D a->df << MO_ASHIFT; /* MO_ALIGN */ + + d16 =3D tcg_temp_new_i128(); + tcg_gen_qemu_ld_i128(d16, addr, ctx->mem_idx, mop); + + tcg_gen_st_i128(d16, tcg_env, offsetof(CPUMIPSState, active_fpu.fpr[d0= ])); + + if (mo_endian(ctx) !=3D MO_LE) { + if (a->df =3D=3D 1) { + tcg_gen_hswap_i64(msa_wr_d[d0], msa_wr_d[d0]); + tcg_gen_hswap_i64(msa_wr_d[d1], msa_wr_d[d1]); + } else if (a->df =3D=3D 2) { + tcg_gen_wswap_i64(msa_wr_d[d0], msa_wr_d[d0]); + tcg_gen_wswap_i64(msa_wr_d[d1], msa_wr_d[d1]); + } + } + + return true; +} + static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, gen_helper_piv *gen_msa_ldst) { @@ -775,7 +818,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i= *a, return true; } =20 -TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld); TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); =20 static bool trans_LSA(DisasContext *ctx, arg_r *a) --=20 2.53.0 From nobody Thu Apr 30 00:40:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1776202341; cv=none; d=zohomail.com; s=zohoarc; b=g7OlLh3cPy75kjjQMUZ6XCMzR7WDYLJQ0NDHTycPLqeFT3VsMo+bJ5Ioys0uMMvN3W93NR4wlp6mikpHM7132m6A6gMXALtuY52nW5dm9jskInu9/WXhphiELQBuaEou61Z0208I1yfHIhx5EnJrtlzJHpSC6F4Xb5TNRPVYKyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776202341; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5CRMRZ6KwHmBSM4nIFrY3AvrZBRDI1zoFU0Uy2HkTeQ=; b=RllG6iE4930Ae0VrLuDW2gAfT79rJKHicqfY8S0iJSuk1IOBemM/wAA6VfHJWBC+Z8GLd0+HV0l3UiSJlgTQJij0U7I3KLW5Php7j/JBUdiHKkMelhFSXWzsHiD2JHNPJDdgVK9hJ9mUEWxdZtXRo28iXZHT7uUVH4dTcJGJYIw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1776202341636209.52817134628742; Tue, 14 Apr 2026 14:32:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wClM4-0000Ok-6V; Tue, 14 Apr 2026 17:31:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wClM2-0000OZ-Cw for qemu-devel@nongnu.org; Tue, 14 Apr 2026 17:31:30 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wClM0-0003I3-C5 for qemu-devel@nongnu.org; Tue, 14 Apr 2026 17:31:30 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-488a9033b2cso73880235e9.2 for ; Tue, 14 Apr 2026 14:31:27 -0700 (PDT) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Remove legacy cpu_st*_data_ra() calls, replacing by tcg_gen_qemu_st() which allow to respect atomicity. Remove the ensure_writable_pages() hack and the bswap NxM helpers. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/msa_helper.h.inc | 8 --- target/mips/tcg/msa_helper.c | 104 ------------------------------- target/mips/tcg/msa_translate.c | 54 ++++++++++++---- 3 files changed, 42 insertions(+), 124 deletions(-) diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.= h.inc index 7ede16f327a..e994353056f 100644 --- a/target/mips/tcg/msa_helper.h.inc +++ b/target/mips/tcg/msa_helper.h.inc @@ -432,11 +432,3 @@ DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) - -#define MSALDST_PROTO(type) \ -DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) -MSALDST_PROTO(b) -MSALDST_PROTO(h) -MSALDST_PROTO(w) -MSALDST_PROTO(d) -#undef MSALDST_PROTO diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 3a0ba420b9d..28148ea9c8b 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8205,107 +8205,3 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint3= 2_t df, uint32_t wd, =20 msa_move_v(pwd, pwx); } - -/* Data format min and max values */ -#define DF_BITS(df) (1 << ((df) + 3)) - -/* Element-by-element access macros */ -#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) - -static inline uint64_t bswap16x4(uint64_t x) -{ - uint64_t m =3D 0x00ff00ff00ff00ffull; - return ((x & m) << 8) | ((x >> 8) & m); -} - -static inline uint64_t bswap32x2(uint64_t x) -{ - return ror64(bswap64(x), 32); -} - -#define MSA_PAGESPAN(x) \ - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) - -static inline void ensure_writable_pages(CPUMIPSState *env, - target_ulong addr, - int mmu_idx, - uintptr_t retaddr) -{ - /* FIXME: Probe the actual accesses (pass and use a size) */ - if (unlikely(MSA_PAGESPAN(addr))) { - /* first page */ - probe_write(env, addr, 0, mmu_idx, retaddr); - /* second page */ - addr =3D (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - probe_write(env, addr, 0, mmu_idx, retaddr); - } -} - -void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D mips_env_mmu_index(env); - uintptr_t ra =3D GETPC(); - - ensure_writable_pages(env, addr, mmu_idx, ra); - - /* Store 8 bytes at a time. Vector element ordering makes this LE. */ - cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra); -} - -void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D mips_env_mmu_index(env); - uintptr_t ra =3D GETPC(); - uint64_t d0, d1; - - ensure_writable_pages(env, addr, mmu_idx, ra); - - /* Store 8 bytes at a time. See helper_msa_ld_h. */ - d0 =3D pwd->d[0]; - d1 =3D pwd->d[1]; - if (mips_env_is_bigendian(env)) { - d0 =3D bswap16x4(d0); - d1 =3D bswap16x4(d1); - } - cpu_stq_le_data_ra(env, addr + 0, d0, ra); - cpu_stq_le_data_ra(env, addr + 8, d1, ra); -} - -void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D mips_env_mmu_index(env); - uintptr_t ra =3D GETPC(); - uint64_t d0, d1; - - ensure_writable_pages(env, addr, mmu_idx, ra); - - /* Store 8 bytes at a time. See helper_msa_ld_w. */ - d0 =3D pwd->d[0]; - d1 =3D pwd->d[1]; - if (mips_env_is_bigendian(env)) { - d0 =3D bswap32x2(d0); - d1 =3D bswap32x2(d1); - } - cpu_stq_le_data_ra(env, addr + 0, d0, ra); - cpu_stq_le_data_ra(env, addr + 8, d1, ra); -} - -void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D mips_env_mmu_index(env); - uintptr_t ra =3D GETPC(); - - ensure_writable_pages(env, addr, mmu_idx, GETPC()); - - cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra); -} diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 0ad8c2c0dc9..c48e5108fe9 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -164,7 +164,6 @@ static inline bool check_msa_enabled(DisasContext *ctx) return true; } =20 -typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv); typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv= _i32); @@ -175,9 +174,6 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_= i32, TCGv_i32, TCGv_i32); }; \ TRANS(NAME, trans_func, NAME##_tab[a->df]) =20 -#define TRANS_DF_iv(NAME, trans_func, gen_func) \ - TRANS_DF_x(iv, NAME, trans_func, gen_func) - #define TRANS_DF_ii(NAME, trans_func, gen_func) \ TRANS_DF_x(ii, NAME, trans_func, gen_func) =20 @@ -801,25 +797,59 @@ static bool trans_LD(DisasContext *ctx, arg_msa_i *a) return true; } =20 -static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a, - gen_helper_piv *gen_msa_ldst) +static bool trans_ST(DisasContext *ctx, arg_msa_i *a) { - TCGv taddr; + TCGv_va addr; + TCGv_i128 d16; + MemOp mop; + int d0 =3D a->wd << 1; + int d1 =3D d0 + 1; =20 if (!check_msa_enabled(ctx)) { return true; } =20 - taddr =3D tcg_temp_new(); + addr =3D tcgv_va_temp_new(); + gen_base_offset_addr(ctx, addr, a->ws, a->sa << a->df); =20 - gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); - gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr); + mop =3D MO_128 | MO_LE; + if (a->df =3D=3D 0) { + mop |=3D MO_ATOM_NONE; + } else if (a->df =3D=3D 3) { + mop |=3D MO_ATOM_IFALIGN_PAIR; + } else { + mop |=3D MO_ATOM_SUBALIGN; /* slightly stronger than required */ + } + mop |=3D a->df << MO_ASHIFT; /* MO_ALIGN */ + + d16 =3D tcg_temp_new_i128(); + + if (mo_endian(ctx) !=3D MO_LE) { + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + + if (a->df =3D=3D 1) { + tcg_gen_hswap_i64(t0, msa_wr_d[d0]); + tcg_gen_hswap_i64(t1, msa_wr_d[d1]); + tcg_gen_concat_i64_i128(d16, t0, t1); + } else if (a->df =3D=3D 2) { + tcg_gen_wswap_i64(t0, msa_wr_d[d0]); + tcg_gen_wswap_i64(t1, msa_wr_d[d1]); + tcg_gen_concat_i64_i128(d16, t0, t1); + } else { + tcg_gen_ld_i128(d16, tcg_env, + offsetof(CPUMIPSState, active_fpu.fpr[d0])); + } + } else { + tcg_gen_ld_i128(d16, tcg_env, + offsetof(CPUMIPSState, active_fpu.fpr[d0])); + } + + tcg_gen_qemu_st_i128(d16, addr, ctx->mem_idx, mop); =20 return true; } =20 -TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st); - static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1); --=20 2.53.0