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Because this bit is never set, guest applications cannot distinguish if a fault was due to missing executable permissions. This patch ensures that when a page fault occurs during an instruction fetch, the PF_INSTR flag is properly populated in the signal context. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3384 Signed-off-by: Simon Scherer --- VERSION | 2 +- target/i386/tcg/user/excp_helper.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/VERSION b/VERSION index de760e732f..340ebebb29 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -10.2.92 +10.2.93 diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp= _helper.c index 98fab4cbc3..6c5df5e0e8 100644 --- a/target/i386/tcg/user/excp_helper.c +++ b/target/i386/tcg/user/excp_helper.c @@ -36,9 +36,10 @@ void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr, * signal and set exception_index to EXCP_INTERRUPT. */ env->cr[2] =3D addr; - env->error_code =3D ((access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W= _BIT) - | (maperr ? 0 : PG_ERROR_P_MASK) - | PG_ERROR_U_MASK; + env->error_code =3D (maperr ? 0 : PG_ERROR_P_MASK) + | ((access_type =3D=3D MMU_DATA_STORE) << PG_ERROR_W_B= IT) + | PG_ERROR_U_MASK + | ((access_type =3D=3D MMU_INST_FETCH) ? PG_ERROR_I_D_= MASK : 0); cs->exception_index =3D EXCP0E_PAGE; =20 /* Disable do_interrupt_user. */ --=20 2.53.0