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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488d5cf2e51sm66157615e9.1.2026.04.10.13.06.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Apr 2026 13:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1775851604; x=1776456404; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IyXjMsUTJvXsk6WJZ8zIGjY1UJ9t5arRWrXPWYyPqt0=; b=bS/aignY0qeB9R6bHhV4V/MzcXsHruiUs5EjbGaDftYTIC+pz/YPYP209Sdw7dibHV AJ/7FLo6yf9ugwiH8PA5T6aDtUuAWIycHNiqq1VMIkzLj8eA5L2N4LuwxWrl5NLo4M4r tNxMrO23wHn1IZz3afweBQhbEllqtujAndwMbxhCnnfnckz3uL0njHscgqf+P1Hrjn9d k6PUC//YtKTTgq1nYtMnGQR3Ed9LGlErBYIKje7aer3MiIkEJ96ZXGgIAv5aO+QQZ4vn mHYEmcZdebOekW1YjoHwZwBor5XhL0/6ndHiYuFYwNjwZBaXHH+q1xLiYk7pYQS+3Jx5 oncw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775851604; x=1776456404; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=IyXjMsUTJvXsk6WJZ8zIGjY1UJ9t5arRWrXPWYyPqt0=; b=gWkeTIV2D1TrVorUj63jEjhbhZ0gyoTJDick92XqV+Tb9rp4HXCjVKEkn7se0EvIXE kAEPII222GLCsgHOm0MJ51USY4LkcpdY8H93y8ShMge4PiYafV+BASsBGPUBRlvhxLkZ pHo7peV/WLN67Bktd1KNGcKefWpIxF0jvrXDHdUCxTIW03Mp72zkfJ4rzR6h1WuNa5ld lQWo6Aybn2zKHE8tTUIfj74DnSNOrBjtBQAinFoOyohg3hTE1YnfD6iFszZqyTt4x9UJ 845Bl9/90AAHzeXp3JR6i20CVC1ydWvCM5Jgf7uNc9qp6/JONe87K1WL7A947CmYsjFj CVcw== X-Gm-Message-State: AOJu0YyXci+YdkqDASPm/ZVk9wDBzr18+ZH20c/mV9ecTqv45oH7MkMd /tfqqkY9ACGLEBJb1jnFVI0HfjfAlQ1J2PAJqSyyrZ3wqzgihlLPQ+ckoCGJD6xXzaMns3Ke42q yfuW1Xj0= X-Gm-Gg: AeBDievv2eHcQzpWrdPatjmlOUgKOmEFJAPjkZlv9ycWZS8ctEb3Ve2E1Nve7bUiTx1 BouvUpUZ++NoLlMyNJnW3RxraQrCF31V0vO02/3ZPIESrA8tYZkTQ7u8vdwu+GZ6R+Etx2pT6Tx YF4MjVsHJ/VSbsRtgZSCv4CRl0ViM1HqsVGtHoWDQwAAbvRQn+6Kdb7roqMaVrIQqt4CAj8lTb7 bX46hy0l7RZQkkmD3ljiNdNYs2lAciiK7UWZalKyQLSfN4JNdG7D7xCSuZngWBDbh6wf/wLXLIB SQYBvlEmU21hDCtJC6zSLBvfdUs5e9ihgveJME+gy4XRML0E3Y7St8H3wC2lnq4IlXv3B44XKmC 61RAOcQJE0jqG+UAgLDhaBtNlbpXlANaueJTH1QdbqPbFfzdbdzIdFI2K1NNLkTc7Qkiv4tuF4t hb0ujGpSMQYHIg8yDfbTIF3y71eyafgm+CrHaDGLvtbxRv2Nw6FqFlsUAxZa9212qtga8TMRB3 X-Received: by 2002:a05:600c:8706:b0:488:a62d:76d7 with SMTP id 5b1f17b1804b1-488d67df53cmr61706965e9.1.1775851604030; Fri, 10 Apr 2026 13:06:44 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/9] target/arm: Explode MO_TExx -> MO_TE | MO_xx Date: Fri, 10 Apr 2026 22:06:21 +0200 Message-ID: <20260410200628.19378-3-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260410200628.19378-1-philmd@linaro.org> References: <20260410200628.19378-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1775851690527154100 Extract the implicit MO_TE definition in order to replace it in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/arm); \ done Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/m_helper.c | 6 +-- target/arm/tcg/mve_helper.c | 79 ++++++++++++++++++++----------------- 2 files changed, 45 insertions(+), 40 deletions(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index a0cb8cb021e..f5954ce9bf9 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -634,7 +634,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) =20 /* Note that these stores can throw exceptions on MPU faults */ ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); cpu_stl_mmu(env, sp, nextinst, oi, GETPC()); cpu_stl_mmu(env, sp + 4, saved_psr, oi, GETPC()); @@ -1055,7 +1055,7 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fpt= r) bool lspact =3D env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; uintptr_t ra =3D GETPC(); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); =20 assert(env->v7m.secure); @@ -1131,7 +1131,7 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) ARMCPU *cpu =3D env_archcpu(env); uintptr_t ra =3D GETPC(); ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, arm_to_core_mmu_idx(mmu_idx)); =20 /* fptr is the value of Rn, the frame pointer we load the FP regs from= */ diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index a67d90d6c75..cc58e0502f5 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -194,23 +194,23 @@ static void mve_advance_vpt(CPUARMState *env) } =20 DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t) -DO_VLDR(vldrh, MO_TEUW, 2, uint16_t, ldw, 2, uint16_t) -DO_VLDR(vldrw, MO_TEUL, 4, uint32_t, ldl, 4, uint32_t) +DO_VLDR(vldrh, MO_TE | MO_UW, 2, uint16_t, ldw, 2, uint16_t) +DO_VLDR(vldrw, MO_TE | MO_UL, 4, uint32_t, ldl, 4, uint32_t) =20 DO_VSTR(vstrb, MO_UB, 1, stb, 1, uint8_t) -DO_VSTR(vstrh, MO_TEUW, 2, stw, 2, uint16_t) -DO_VSTR(vstrw, MO_TEUL, 4, stl, 4, uint32_t) +DO_VSTR(vstrh, MO_TE | MO_UW, 2, stw, 2, uint16_t) +DO_VSTR(vstrw, MO_TE | MO_UL, 4, stl, 4, uint32_t) =20 DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t) DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t) DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t) DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t) -DO_VLDR(vldrh_sw, MO_TESW, 2, int16_t, ldw, 4, int32_t) -DO_VLDR(vldrh_uw, MO_TEUW, 2, uint16_t, ldw, 4, uint32_t) +DO_VLDR(vldrh_sw, MO_TE | MO_SW, 2, int16_t, ldw, 4, int32_t) +DO_VLDR(vldrh_uw, MO_TE | MO_UW, 2, uint16_t, ldw, 4, uint32_t) =20 DO_VSTR(vstrb_h, MO_UB, 1, stb, 2, int16_t) DO_VSTR(vstrb_w, MO_UB, 1, stb, 4, int32_t) -DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) +DO_VSTR(vstrh_w, MO_TE | MO_UW, 2, stw, 4, int32_t) =20 #undef DO_VLDR #undef DO_VSTR @@ -295,7 +295,7 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ if (!(eci_mask & 1)) { \ continue; \ @@ -321,7 +321,7 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) unsigned e; \ uint32_t addr; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4, eci_mask >>=3D 4) { = \ if (!(eci_mask & 1)) { \ continue; \ @@ -345,42 +345,47 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t) =20 DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD= , false) DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD= , false) -DO_VLDR_SG(vldrh_sg_sw, MO_TESW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_= ADD, false) +DO_VLDR_SG(vldrh_sg_sw, MO_TE | MO_SW, int16_t, ldw, 4, + int32_t, uint32_t, ADDR_ADD, false) =20 DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD= , false) DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_A= DD, false) DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_A= DD, false) -DO_VLDR_SG(vldrh_sg_uh, MO_TEUW, uint16_t, ldw, 2, uint16_t, uint16_t, ADD= R_ADD, false) -DO_VLDR_SG(vldrh_sg_uw, MO_TEUW, uint16_t, ldw, 4, uint32_t, uint32_t, ADD= R_ADD, false) -DO_VLDR_SG(vldrw_sg_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADD= R_ADD, false) +DO_VLDR_SG(vldrh_sg_uh, MO_TE | MO_UW, uint16_t, ldw, 2, + uint16_t, uint16_t, ADDR_ADD, false) +DO_VLDR_SG(vldrh_sg_uw, MO_TE | MO_UW, uint16_t, ldw, 4, + uint32_t, uint32_t, ADDR_ADD, false) +DO_VLDR_SG(vldrw_sg_uw, MO_TE | MO_UL, uint32_t, ldl, 4, + uint32_t, uint32_t, ADDR_ADD, false) DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false) =20 -DO_VLDR_SG(vldrh_sg_os_sw, MO_TESW, int16_t, ldw, 4, +DO_VLDR_SG(vldrh_sg_os_sw, MO_TE | MO_SW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrh_sg_os_uh, MO_TEUW, uint16_t, ldw, 2, +DO_VLDR_SG(vldrh_sg_os_uh, MO_TE | MO_UW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrh_sg_os_uw, MO_TEUW, uint16_t, ldw, 4, +DO_VLDR_SG(vldrh_sg_os_uw, MO_TE | MO_UW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, false) -DO_VLDR_SG(vldrw_sg_os_uw, MO_TEUL, uint32_t, ldl, 4, +DO_VLDR_SG(vldrw_sg_os_uw, MO_TE | MO_UL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false) DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false) =20 DO_VSTR_SG(vstrb_sg_ub, MO_UB, stb, 1, uint8_t, ADDR_ADD, false) DO_VSTR_SG(vstrb_sg_uh, MO_UB, stb, 2, uint16_t, ADDR_ADD, false) DO_VSTR_SG(vstrb_sg_uw, MO_UB, stb, 4, uint32_t, ADDR_ADD, false) -DO_VSTR_SG(vstrh_sg_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD, false) -DO_VSTR_SG(vstrh_sg_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD, false) -DO_VSTR_SG(vstrw_sg_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD, false) +DO_VSTR_SG(vstrh_sg_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD, false) +DO_VSTR_SG(vstrw_sg_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, false) DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false) =20 -DO_VSTR_SG(vstrh_sg_os_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD_OSH, false) -DO_VSTR_SG(vstrh_sg_os_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD_OSH, false) -DO_VSTR_SG(vstrw_sg_os_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD_OSW, false) +DO_VSTR_SG(vstrh_sg_os_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD_OSH, = false) +DO_VSTR_SG(vstrh_sg_os_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD_OSH, = false) +DO_VSTR_SG(vstrw_sg_os_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD_OSW, = false) DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false) =20 -DO_VLDR_SG(vldrw_sg_wb_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, = ADDR_ADD, true) +DO_VLDR_SG(vldrw_sg_wb_uw, MO_TE | MO_UL, uint32_t, ldl, 4, + uint32_t, uint32_t, ADDR_ADD, true) DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true) -DO_VSTR_SG(vstrw_sg_wb_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, true) +DO_VSTR_SG(vstrw_sg_wb_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, true) DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) =20 /* @@ -408,7 +413,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ uint32_t addr, data; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -434,7 +439,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) int y; /* y counts 0 2 0 2 */ \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -461,7 +466,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true) uint32_t *qd; \ int y; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -500,7 +505,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) uint32_t addr, data; \ uint8_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -526,7 +531,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) int e; \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -551,7 +556,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9) uint32_t addr, data; \ uint32_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -582,7 +587,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) static const uint8_t off[4] =3D { O1, O2, O3, O4 }; \ uint32_t addr, data; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -609,7 +614,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) int y; /* y counts 0 2 0 2 */ \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0, y =3D 0; beat < 4; beat++, mask >>=3D 4, y ^=3D 2= ) { \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -635,7 +640,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20) uint32_t *qd; \ int y; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -674,7 +679,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) uint32_t addr, data; \ uint8_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -701,7 +706,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) int e; \ uint16_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ @@ -727,7 +732,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9) uint32_t addr, data; \ uint32_t *qd; \ int mmu_idx =3D arm_to_core_mmu_idx(arm_mmu_idx(env)); \ - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\ for (beat =3D 0; beat < 4; beat++, mask >>=3D 4) { = \ if ((mask & 1) =3D=3D 0) { = \ /* ECI says skip this beat */ \ --=20 2.53.0