From nobody Sat Apr 11 17:09:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775793815867585.527208451319; Thu, 9 Apr 2026 21:03:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wB35S-00013i-FX; Fri, 10 Apr 2026 00:03:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wB35N-00013a-CI for qemu-devel@nongnu.org; Fri, 10 Apr 2026 00:03:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wB35K-0004kP-46 for qemu-devel@nongnu.org; Fri, 10 Apr 2026 00:03:13 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Dx98F3dthp990jAA--.1073S3; Fri, 10 Apr 2026 12:03:03 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJCxPMJ0dthpWhdqAA--.3585S2; Fri, 10 Apr 2026 12:03:01 +0800 (CST) From: Song Gao To: maobibo@loongson.cn Cc: qemu-devel@nongnu.org, philmd@linaro.org, richard.henderson@linaro.org, lixianglai@loongson.cn, yijun@loongson.cn, chenhuacai@loongson.cn Subject: [PATCH v2] target/loongarch: Add support for dbar hint variants Date: Fri, 10 Apr 2026 11:37:23 +0800 Message-Id: <20260410033723.1225983-1-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxPMJ0dthpWhdqAA--.3585S2 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1775793819854154100 Content-Type: text/plain; charset="utf-8" LoongArch architecture (since LA664) introduces fine-grained dbar hints that allow controlling which memory accesses are ordered by the barrier. Previously, all dbar instructions were treated as a full barrier (TCG_MO_ALL | TCG_BAR_SC). This patch adds support for decoding dbar hints and emitting the appropriate TCG memory barrier flags. For CPUs that do not advertise the DBAR_HINTS feature (cpucfg3.DBAR_HINTS =3D 0), all dbar hints fall back to a full barrier, preserving compatibility. The hint encoding follows the LoongArch v1.10 specification: * Bit3: barrier for previous read (0: true, 1: false) * Bit2: barrier for previous write (0: true, 1: false) * Bit1: barrier for succeeding read (0: true, 1: false) * Bit0: barrier for succeeding write (0: true, 1: false) The mapping to TCG memory order flags is as follows: TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_LD_ST; TCG_BAR_SC |TCG_MO_ST_LD | TCG_MO_ST_ST; TCG_BAR_SC |TCG_MO_LD_LD | TCG_MO_ST_LD; TCG_BAR_SC |TCG_MO_ST_ST | TCG_MO_LD_ST; Special hint handling: - hint 0x700: LL/SC loop barrier, treated as a full barrier as recommended. - hint 0xf and 0x1f: reserved/no-op, treated as no operation Signed-off-by: Song Gao --- target/loongarch/cpu.c | 4 ++ .../tcg/insn_trans/trans_memory.c.inc | 62 ++++++++++++++++++- target/loongarch/tcg/translate.c | 1 + target/loongarch/translate.h | 3 + 4 files changed, 68 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index e22568c84a..d8d106b07e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -455,6 +455,10 @@ static void loongarch_max_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG2, LLACQ_SCREL, 1); data =3D FIELD_DP32(data, CPUCFG2, SCQ, 1); cpu->env.cpucfg[2] =3D data; + + data =3D cpu->env.cpucfg[3]; + data =3D FIELD_DP32(data, CPUCFG3, DBAR_HINTS, 1); + cpu->env.cpucfg[3] =3D data; } } =20 diff --git a/target/loongarch/tcg/insn_trans/trans_memory.c.inc b/target/lo= ongarch/tcg/insn_trans/trans_memory.c.inc index e287d46363..e1146fe9ec 100644 --- a/target/loongarch/tcg/insn_trans/trans_memory.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_memory.c.inc @@ -137,11 +137,69 @@ static bool trans_preldx(DisasContext *ctx, arg_preld= x * a) return true; } =20 +/* + * Decode dbar hint and emit appropriate TCG memory barrier. + * + * The hint is a 5-bit field (0-31) encoded in the instruction. + * For hint 0x700 (special LL/SC loop barrier), treat as full barrier. + * + * See LoongArch Reference Manual v1.10, Section 4.2.2 for details. + */ static bool trans_dbar(DisasContext *ctx, arg_dbar * a) { - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + int hint =3D a->imm; + TCGBar bar_flags =3D 0; + + /* Reserved/no-op hints: 0xf and 0x1f */ + if (hint =3D=3D 0xf || hint =3D=3D 0x1f) { + return true; + } + + /* If the CPU does not support fine-grained hints,or for the special L= L/SC + * loop barrier (0x700), emit a full barrier. + */ + if (!avail_DBAR_HINT(ctx) || hint =3D=3D 0x700) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; + } + + /* + * Fine-grained hint decoding: + * Bits 3-0 control which accesses must be ordered. + * Bit3: barrier for previous read (0: true, 1: false) + * Bit2: barrier for previous write (0: true, 1: false) + * Bit1: barrier for succeeding read (0: true, 1: false) + * Bit0: barrier for succeeding write (0: true, 1: false) + * + * For each combination, we set the corresponding TCG_MO_* flag if both + * sides of the barrier require ordering. + */ + + bool prev_rd =3D !(hint & 0x08); /* bit3 */ + bool prev_wr =3D !(hint & 0x04); /* bit2 */ + bool succ_rd =3D !(hint & 0x02); /* bit1 */ + bool succ_wr =3D !(hint & 0x01); /* bit0 */ + + if (prev_rd) { + bar_flags |=3D TCG_MO_LD_LD | TCG_MO_LD_ST; + } + if (prev_wr) { + bar_flags |=3D TCG_MO_ST_LD | TCG_MO_ST_ST; + } + if (succ_rd) { + bar_flags |=3D TCG_MO_LD_LD | TCG_MO_ST_LD; + } + if (succ_wr) { + bar_flags |=3D TCG_MO_ST_ST | TCG_MO_LD_ST; + } + + if (bar_flags =3D=3D 0) { + bar_flags =3D TCG_MO_ALL; + } + + tcg_gen_mb(bar_flags | TCG_BAR_SC); return true; -} + } =20 static bool trans_ibar(DisasContext *ctx, arg_ibar *a) { diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index b9ed13d19c..49280b1dd3 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -149,6 +149,7 @@ static void loongarch_tr_init_disas_context(DisasContex= tBase *dcbase, =20 ctx->cpucfg1 =3D env->cpucfg[1]; ctx->cpucfg2 =3D env->cpucfg[2]; + ctx->cpucfg3 =3D env->cpucfg[3]; } =20 static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index ba1c89e57b..8aa8325dc6 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -43,6 +43,8 @@ #define avail_LLACQ_SCREL(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LLACQ_S= CREL)) #define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C)) =20 +#define avail_DBAR_HINT(C) (FIELD_EX32((C)->cpucfg3, CPUCFG3, DBAR_HINTS)) + /* * If an operation is being performed on less than TARGET_LONG_BITS, * it may require the inputs to be sign- or zero-extended; which will @@ -66,6 +68,7 @@ typedef struct DisasContext { bool va32; /* 32-bit virtual address */ uint32_t cpucfg1; uint32_t cpucfg2; + uint32_t cpucfg3; } DisasContext; =20 void generate_exception(DisasContext *ctx, int excp); --=20 2.47.3