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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775676028435154100 From: Brian Cain Some header includes are modified here: these are uniquely required for basic system emulation functionality and had not been required for linux-us= er. Acked-by: Markus Armbruster Co-authored-by: Mike Lambert Co-authored-by: Sid Manning Signed-off-by: Brian Cain --- MAINTAINERS | 2 + include/hw/hexagon/hexagon.h | 150 +++++++++++++++++++++++ hw/hexagon/machine_cfg_v66g_1024.h.inc | 64 ++++++++++ hw/hexagon/hexagon_dsp.c | 161 +++++++++++++++++++++++++ system/qdev-monitor.c | 2 +- target/hexagon/translate.c | 1 + hw/Kconfig | 1 + hw/hexagon/Kconfig | 5 + hw/hexagon/meson.build | 6 + hw/meson.build | 1 + 10 files changed, 392 insertions(+), 1 deletion(-) create mode 100644 include/hw/hexagon/hexagon.h create mode 100644 hw/hexagon/machine_cfg_v66g_1024.h.inc create mode 100644 hw/hexagon/hexagon_dsp.c create mode 100644 hw/hexagon/Kconfig create mode 100644 hw/hexagon/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 4055fbe3c21..b9a7c553dfa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -246,6 +246,8 @@ Hexagon TCG CPUs M: Brian Cain S: Supported F: target/hexagon/ +F: hw/hexagon/ +F: include/hw/hexagon/ X: target/hexagon/idef-parser/ X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h new file mode 100644 index 00000000000..996f5423c39 --- /dev/null +++ b/include/hw/hexagon/hexagon.h @@ -0,0 +1,150 @@ +/* + * Hexagon Baseboard System emulation. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + +#ifndef HW_HEXAGON_H +#define HW_HEXAGON_H + +#include "system/memory.h" + +struct hexagon_board_boot_info { + uint64_t ram_size; + const char *kernel_filename; + uint32_t kernel_elf_flags; +}; + +typedef enum { + unknown_rev =3D 0, + v66_rev =3D 0xa666, + v67_rev =3D 0x2667, + v68_rev =3D 0x8d68, + v69_rev =3D 0x8c69, + v71_rev =3D 0x8c71, + v73_rev =3D 0x8c73, + v73m_rev =3D 0xcc73, +} Rev_t; +#define HEXAGON_LATEST_REV v73 +#define HEXAGON_LATEST_REV_UPPER V73 + +/* + * Config table address bases represent bits [35:16]. + */ +#define HEXAGON_CFG_ADDR_BASE(addr) (((addr) >> 16) & 0x0fffff) + +#define HEXAGON_CFGSPACE_ENTRIES (128) + +union hexagon_config_table { + struct { + /* Base address of L2TCM space */ + uint32_t l2tcm_base; + uint32_t reserved0; + /* Base address of subsystem space */ + uint32_t subsystem_base; + /* Base address of ETM space */ + uint32_t etm_base; + /* Base address of L2 configuration space */ + uint32_t l2cfg_base; + uint32_t reserved1; + /* Base address of L1S */ + uint32_t l1s0_base; + /* Base address of AXI2 */ + uint32_t axi2_lowaddr; + /* Base address of streamer base */ + uint32_t streamer_base; + uint32_t reserved2; + /* Base address of fast L2VIC */ + uint32_t fastl2vic_base; + /* Number of entries in JTLB */ + uint32_t jtlb_size_entries; + /* Coprocessor type */ + uint32_t coproc_present; + /* Number of extension execution contexts available */ + uint32_t ext_contexts; + /* Base address of Hexagon Vector Tightly Coupled Memory (VTCM) */ + uint32_t vtcm_base; + /* Size of VTCM (in KB) */ + uint32_t vtcm_size_kb; + /* L2 tag size */ + uint32_t l2tag_size; + /* Amount of physical L2 memory in released version */ + uint32_t l2ecomem_size; + /* Hardware threads available on the core */ + uint32_t thread_enable_mask; + /* Base address of the ECC registers */ + uint32_t eccreg_base; + /* L2 line size */ + uint32_t l2line_size; + /* Small Core processor (also implies audio extension) */ + uint32_t tiny_core; + /* Size of L2TCM */ + uint32_t l2itcm_size; + /* Base address of L2-ITCM */ + uint32_t l2itcm_base; + uint32_t reserved3; + /* DTM is present */ + uint32_t dtm_present; + /* Version of the DMA */ + uint32_t dma_version; + /* Native HVX vector length in log of bytes */ + uint32_t hvx_vec_log_length; + /* Core ID of the multi-core */ + uint32_t core_id; + /* Number of multi-core cores */ + uint32_t core_count; + uint32_t coproc2_reg0; + uint32_t coproc2_reg1; + /* Supported HVX vector length */ + uint32_t v2x_mode; + uint32_t coproc2_reg2; + uint32_t coproc2_reg3; + uint32_t coproc2_reg4; + uint32_t coproc2_reg5; + uint32_t coproc2_reg6; + uint32_t coproc2_reg7; + /* Voltage droop mitigation technique parameter */ + uint32_t acd_preset; + /* Voltage droop mitigation technique parameter */ + uint32_t mnd_preset; + /* L1 data cache size (in KB) */ + uint32_t l1d_size_kb; + /* L1 instruction cache size in (KB) */ + uint32_t l1i_size_kb; + /* L1 data cache write policy: see HexagonL1WritePolicy */ + uint32_t l1d_write_policy; + /* VTCM bank width */ + uint32_t vtcm_bank_width; + uint32_t reserved4; + uint32_t reserved5; + uint32_t reserved6; + uint32_t coproc2_cvt_mpy_size; + uint32_t consistency_domain; + uint32_t capacity_domain; + uint32_t axi3_lowaddr; + uint32_t coproc2_int8_subcolumns; + uint32_t corecfg_present; + uint32_t coproc2_fp16_acc_exp; + uint32_t AXIM2_secondary_base; + }; + uint32_t raw[HEXAGON_CFGSPACE_ENTRIES]; +}; + +struct hexagon_machine_config { + /* Base address of config table */ + uint32_t cfgbase; + /* Size of L2 TCM */ + uint32_t l2tcm_size; + /* Base address of L2VIC */ + uint32_t l2vic_base; + /* Size of L2VIC region */ + uint32_t l2vic_size; + /* QTimer csr base */ + uint32_t csr_base; + uint32_t qtmr_region; + union hexagon_config_table cfgtable; +}; + +#endif diff --git a/hw/hexagon/machine_cfg_v66g_1024.h.inc b/hw/hexagon/machine_cf= g_v66g_1024.h.inc new file mode 100644 index 00000000000..cc4d89b89c9 --- /dev/null +++ b/hw/hexagon/machine_cfg_v66g_1024.h.inc @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +static const struct hexagon_machine_config v66g_1024 =3D { + .cfgbase =3D 0xd8180000, + .l2tcm_size =3D 0x00000000, + .l2vic_base =3D 0xfc910000, + .l2vic_size =3D 0x00001000, + .csr_base =3D 0xfc900000, + .qtmr_region =3D 0xfc921000, + .cfgtable =3D { + .l2tcm_base =3D 0x0000d800, + .reserved0 =3D 0x0000d400, + .subsystem_base =3D 0x0000fc90, + .etm_base =3D 0x0000d805, + .l2cfg_base =3D 0x0000d81a, + .reserved1 =3D 0x00000000, + .l1s0_base =3D 0x0000d820, + .axi2_lowaddr =3D 0x00003000, + .streamer_base =3D 0x00000000, + .reserved2 =3D 0x0000d819, + .fastl2vic_base =3D 0x0000d81e, + .jtlb_size_entries =3D 0x00000080, + .coproc_present =3D 0x00000001, + .ext_contexts =3D 0x00000004, + .vtcm_base =3D 0x0000d820, + .vtcm_size_kb =3D 0x00000100, + .l2tag_size =3D 0x00000400, + .l2ecomem_size =3D 0x00000400, + .thread_enable_mask =3D 0x0000000f, + .eccreg_base =3D 0x0000d81f, + .l2line_size =3D 0x00000080, + .tiny_core =3D 0x00000000, + .l2itcm_size =3D 0x00000000, + .l2itcm_base =3D 0x0000d820, + .reserved3 =3D 0x00000000, + .dtm_present =3D 0x00000000, + .dma_version =3D 0x00000000, + .hvx_vec_log_length =3D 0x00000080, + .core_id =3D 0x00000000, + .core_count =3D 0x00000000, + .coproc2_reg0 =3D 0x00000000, + .coproc2_reg1 =3D 0x00000000, + .v2x_mode =3D 0x00000000, + .coproc2_reg2 =3D 0x00000000, + .coproc2_reg3 =3D 0x00000000, + .coproc2_reg4 =3D 0x00000000, + .coproc2_reg5 =3D 0x00000000, + .coproc2_reg6 =3D 0x00000000, + .coproc2_reg7 =3D 0x00000000, + .acd_preset =3D 0x00000000, + .mnd_preset =3D 0x00000000, + .l1d_size_kb =3D 0x00000000, + .l1i_size_kb =3D 0x00000000, + .l1d_write_policy =3D 0x00000000, + .vtcm_bank_width =3D 0x00000000, + .reserved4 =3D 0x00000000, + .reserved5 =3D 0x00000000, + .reserved6 =3D 0x00000000, + .coproc2_cvt_mpy_size =3D 0x00000000, + .consistency_domain =3D 0x00000000, + .capacity_domain =3D 0x00000000, + .axi3_lowaddr =3D 0x00000000, + }, +}; diff --git a/hw/hexagon/hexagon_dsp.c b/hw/hexagon/hexagon_dsp.c new file mode 100644 index 00000000000..d5df87605f4 --- /dev/null +++ b/hw/hexagon/hexagon_dsp.c @@ -0,0 +1,161 @@ +/* + * Hexagon DSP Subsystem emulation. This represents a generic DSP + * subsystem with few peripherals, like the Compute DSP. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "system/address-spaces.h" +#include "hw/core/boards.h" +#include "hw/core/qdev-properties.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/hexagon_globalreg.h" +#include "hw/core/loader.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "elf.h" +#include "cpu.h" +#include "migration/cpu.h" +#include "system/system.h" +#include "target/hexagon/internal.h" +#include "system/reset.h" + +#include "machine_cfg_v66g_1024.h.inc" + +static void hex_symbol_callback(const char *st_name, int st_info, + uint64_t st_value, uint64_t st_size) +{ +} + +/* Board init. */ +static struct hexagon_board_boot_info hexagon_binfo; + +static void hexagon_load_kernel(HexagonCPU *cpu) +{ + uint64_t pentry; + long kernel_size; + + kernel_size =3D load_elf_ram_sym(hexagon_binfo.kernel_filename, NULL, = NULL, + NULL, &pentry, NULL, NULL, + &hexagon_binfo.kernel_elf_flags, 0, EM_HEXAGON, 0, 0, + &address_space_memory, false, hex_symbol_callback); + + if (kernel_size <=3D 0) { + error_report("no kernel file '%s'", + hexagon_binfo.kernel_filename); + exit(1); + } + + qdev_prop_set_uint32(DEVICE(cpu), "exec-start-addr", pentry); +} + +static void hexagon_init_bootstrap(MachineState *machine, HexagonCPU *cpu) +{ + if (machine->kernel_filename) { + hexagon_load_kernel(cpu); + } +} + +static void do_cpu_reset(void *opaque) +{ + HexagonCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + cpu_reset(cs); +} + +static void hexagon_common_init(MachineState *machine, Rev_t rev, + const struct hexagon_machine_config *m_cfg) +{ + MemoryRegion *address_space; + MemoryRegion *sram; + DeviceState *glob_regs_dev; + + memset(&hexagon_binfo, 0, sizeof(hexagon_binfo)); + if (machine->kernel_filename) { + hexagon_binfo.ram_size =3D machine->ram_size; + hexagon_binfo.kernel_filename =3D machine->kernel_filename; + } + + machine->enable_graphics =3D 0; + + address_space =3D get_system_memory(); + + sram =3D g_new(MemoryRegion, 1); + memory_region_init_ram(sram, NULL, "ddr.ram", + machine->ram_size, &error_fatal); + memory_region_add_subregion(address_space, 0x0, sram); + + glob_regs_dev =3D qdev_new(TYPE_HEXAGON_GLOBALREG); + qdev_prop_set_uint64(glob_regs_dev, "config-table-addr", m_cfg->cfgbas= e); + sysbus_realize_and_unref(SYS_BUS_DEVICE(glob_regs_dev), &error_fatal); + + for (int i =3D 0; i < machine->smp.cpus; i++) { + HexagonCPU *cpu =3D HEXAGON_CPU(object_new(machine->cpu_type)); + qemu_register_reset(do_cpu_reset, cpu); + + /* + * CPU #0 is the only CPU running at boot, others must be + * explicitly enabled via start instruction. + */ + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", (i !=3D 0)); + if (i =3D=3D 0) { + hexagon_init_bootstrap(machine, cpu); + if (!qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal)) { + return; + } + } else if (!qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal= )) { + return; + } + + } +} + +static void init_mc(MachineClass *mc) +{ + mc->block_default_type =3D IF_SD; + mc->default_ram_size =3D 4 * GiB; + mc->no_parallel =3D 1; + mc->no_floppy =3D 1; + mc->no_cdrom =3D 1; + mc->no_serial =3D 1; + mc->is_default =3D false; + mc->max_cpus =3D 8; +} + +/* ----------------------------------------------------------------- */ +/* Core-specific configuration settings are defined below this line. */ +/* Config table values defined in machine_configs.h.inc */ +/* ----------------------------------------------------------------- */ + +static void v66g_1024_config_init(MachineState *machine) +{ + hexagon_common_init(machine, v66_rev, &v66g_1024); +} + +static void v66g_1024_init(ObjectClass *oc, const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Hexagon V66G_1024"; + mc->init =3D v66g_1024_config_init; + init_mc(mc); + mc->is_default =3D true; + mc->default_cpu_type =3D TYPE_HEXAGON_CPU_V66; + mc->default_cpus =3D 4; +} + +static const TypeInfo hexagon_machine_types[] =3D { + { + .name =3D MACHINE_TYPE_NAME("V66G_1024"), + .parent =3D TYPE_MACHINE, + .class_init =3D v66g_1024_init, + }, +}; + +DEFINE_TYPES(hexagon_machine_types) diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c index 1ac6d9a8575..72abc9182a9 100644 --- a/system/qdev-monitor.c +++ b/system/qdev-monitor.c @@ -69,7 +69,7 @@ typedef struct QDevAlias QEMU_ARCH_SPARC | \ QEMU_ARCH_XTENSA) #define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X) -#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K) +#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K | QEMU_ARCH_HEXAGON) =20 /* Please keep this table sorted by typename. */ static const QDevAlias qdev_alias_table[] =3D { diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index ae980c087f0..15258a203b3 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -32,6 +32,7 @@ #include "translate.h" #include "genptr.h" #include "printinsn.h" +#include "exec/target_page.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/hw/Kconfig b/hw/Kconfig index b3ed092f7a8..dda3139be74 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -54,6 +54,7 @@ source arm/Kconfig source cpu/Kconfig source alpha/Kconfig source avr/Kconfig +source hexagon/Kconfig source hppa/Kconfig source i386/Kconfig source loongarch/Kconfig diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig new file mode 100644 index 00000000000..7b9577f68f7 --- /dev/null +++ b/hw/hexagon/Kconfig @@ -0,0 +1,5 @@ +config HEX_DSP + bool + default y + depends on HEXAGON && TCG + imply PTIMER diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build new file mode 100644 index 00000000000..f528d2bc4ab --- /dev/null +++ b/hw/hexagon/meson.build @@ -0,0 +1,6 @@ +hexagon_ss =3D ss.source_set() +hexagon_ss.add(files('hexagon_tlb.c')) +hexagon_ss.add(files('hexagon_globalreg.c')) +hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c')) + +hw_arch +=3D {'hexagon': hexagon_ss} diff --git a/hw/meson.build b/hw/meson.build index ef65ba51950..7fa81db453e 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -3,6 +3,7 @@ subdir('alpha') subdir('arm') subdir('avr') subdir('hppa') +subdir('hexagon') subdir('xenpv') # i386 uses it subdir('i386') subdir('loongarch') --=20 2.34.1