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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775676434687154100 From: Brian Cain iassign{r,w} are the "Interrupt to thread assignment {read,write}" instructions. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/op_helper.c | 56 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 04d9f1286c9..7e6e04e512a 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1416,12 +1416,64 @@ void HELPER(cswi)(CPUHexagonState *env, uint32_t ma= sk) =20 void HELPER(iassignw)(CPUHexagonState *env, uint32_t src) { - g_assert_not_reached(); + uint32_t modectl; + uint32_t thread_enabled_mask; + CPUState *cpu; + HexagonCPU *hex_cpu; + + BQL_LOCK_GUARD(); + hex_cpu =3D env_archcpu(env); + modectl =3D hex_cpu->globalregs ? + hexagon_globalreg_read(hex_cpu->globalregs, HEX_SREG_MODECTL, + env->threadId) : 0; + thread_enabled_mask =3D GET_FIELD(MODECTL_E, modectl); + + CPU_FOREACH(cpu) { + CPUHexagonState *thread_env =3D &(HEXAGON_CPU(cpu)->env); + uint32_t thread_id_mask =3D 0x1 << thread_env->threadId; + if (thread_enabled_mask & thread_id_mask) { + uint32_t imask =3D thread_env->t_sreg[HEX_SREG_IMASK]; + uint32_t intbitpos =3D (src >> 16) & 0xF; + uint32_t val =3D (src >> thread_env->threadId) & 0x1; + imask =3D deposit32(imask, intbitpos, 1, val); + thread_env->t_sreg[HEX_SREG_IMASK] =3D imask; + + qemu_log_mask(CPU_LOG_INT, "%s: thread " TARGET_FMT_ld + ", new imask 0x%" PRIx32 "\n", __func__, + thread_env->threadId, imask); + } + } + hex_interrupt_update(env); } =20 uint32_t HELPER(iassignr)(CPUHexagonState *env, uint32_t src) { - g_assert_not_reached(); + uint32_t modectl; + uint32_t thread_enabled_mask; + uint32_t intbitpos; + uint32_t dest_reg; + CPUState *cpu; + HexagonCPU *hex_cpu; + + BQL_LOCK_GUARD(); + hex_cpu =3D env_archcpu(env); + modectl =3D hex_cpu->globalregs ? + hexagon_globalreg_read(hex_cpu->globalregs, HEX_SREG_MODECTL, + env->threadId) : 0; + thread_enabled_mask =3D GET_FIELD(MODECTL_E, modectl); + /* src fields are in same position as modectl, but mean different thin= gs */ + intbitpos =3D GET_FIELD(MODECTL_W, src); + dest_reg =3D 0; + CPU_FOREACH(cpu) { + CPUHexagonState *thread_env =3D &(HEXAGON_CPU(cpu)->env); + uint32_t thread_id_mask =3D 0x1 << thread_env->threadId; + if (thread_enabled_mask & thread_id_mask) { + uint32_t imask =3D thread_env->t_sreg[HEX_SREG_IMASK]; + dest_reg |=3D ((imask >> intbitpos) & 0x1) << thread_env->thre= adId; + } + } + + return dest_reg; } =20 void HELPER(start)(CPUHexagonState *env, uint32_t imask) --=20 2.34.1