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charset="utf-8" Implement APIC IRR interrupt priorities. Even with kernel-irqchip=3Doff, Hyper-V is aware of interrupt priorities and implements CR8/TPR, with the InterruptPriority field being followed. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 7a31dc6427..8cd81fffee 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -1588,6 +1588,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) UINT32 reg_count =3D 0; WHV_REGISTER_VALUE reg_values[3]; WHV_REGISTER_NAME reg_names[3]; + int irr =3D apic_get_highest_priority_irr(x86_cpu->apic_state); =20 memset(&new_int, 0, sizeof(new_int)); memset(reg_values, 0, sizeof(reg_values)); @@ -1623,10 +1624,20 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } } =20 + if (irr =3D=3D -1) { + if (pic_get_output(isa_pic)) { + /* In case it's a PIC interrupt */ + irr =3D 0; + } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { + abort(); + } + } + /* Get pending hard interruption or replay one that was overwritten */ if (!whpx_irqchip_in_kernel()) { if (!vcpu->interruption_pending && - vcpu->interruptable && (env->eflags & IF_MASK)) { + vcpu->interruptable && (env->eflags & IF_MASK) + && (vcpu->tpr < irr || irr =3D=3D 0)) { assert(!new_int.InterruptionPending); if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); @@ -1683,13 +1694,17 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } =20 /* Update the state of the interrupt delivery notification */ - if (!vcpu->window_registered && + if ((!vcpu->window_registered || + (vcpu->window_priority < irr && vcpu->window_priority !=3D 0) || + (irr =3D=3D 0 && vcpu->window_priority !=3D 0)) && cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { reg_values[reg_count].DeliverabilityNotifications =3D (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) { - .InterruptNotification =3D 1 + .InterruptNotification =3D 1, + .InterruptPriority =3D irr >> 4 }; vcpu->window_registered =3D 1; + vcpu->window_priority =3D irr; reg_names[reg_count] =3D WHvX64RegisterDeliverabilityNotifications; reg_count +=3D 1; } @@ -1703,7 +1718,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) reg_names, reg_count, reg_values); if (FAILED(hr)) { error_report("WHPX: Failed to set interrupt state registers," - " hr=3D%08lx", hr); + " hr=3D%08lx, InterruptPriority=3D%i", hr, irr >>= 4); } } } @@ -1919,6 +1934,7 @@ int whpx_vcpu_run(CPUState *cpu) case WHvRunVpExitReasonX64InterruptWindow: vcpu->ready_for_pic_interrupt =3D 1; vcpu->window_registered =3D 0; + vcpu->window_priority =3D 0; ret =3D 0; break; =20 --=20 2.50.1 (Apple Git-155)