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At this point, we don't need to do anything for aarch64_translator_ops since it's just an external symbol. We can now include target/arm/tcg/translate.h from common code, since all target specific bits have been removed, or can be specialized with specific defines. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/tcg/translate.h | 10 ---------- target/arm/tcg/stubs32.c | 17 +++++++++++++++++ target/arm/tcg/meson.build | 1 + 3 files changed, 18 insertions(+), 10 deletions(-) create mode 100644 target/arm/tcg/stubs32.c diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index e28eac54afb..77fdc5f3a17 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -357,19 +357,9 @@ static inline int curr_insn_len(DisasContext *s) /* CPU state was modified dynamically; no need to exit, but do not chain. = */ #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 =20 -#ifdef TARGET_AARCH64 void a64_translate_init(void); void gen_a64_update_pc(DisasContext *s, int64_t diff); extern const TranslatorOps aarch64_translator_ops; -#else -static inline void a64_translate_init(void) -{ -} - -static inline void gen_a64_update_pc(DisasContext *s, int64_t diff) -{ -} -#endif =20 void arm_test_cc(DisasCompare *cmp, int cc); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); diff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c new file mode 100644 index 00000000000..c5a0bc61f47 --- /dev/null +++ b/target/arm/tcg/stubs32.c @@ -0,0 +1,17 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "target/arm/tcg/translate.h" + + +void gen_a64_update_pc(DisasContext *s, int64_t diff) +{ + g_assert_not_reached(); +} + +void a64_translate_init(void) +{ + /* Don't initialize for 32 bits. Call site will be fixed later. */ +} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 5f591560551..3e96c77df73 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -21,6 +21,7 @@ gen_a32 =3D [ =20 arm_ss.add(gen_a32) arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64) +arm_ss.add(when: 'TARGET_AARCH64', if_false: files('stubs32.c')) =20 arm_ss.add(files( 'cpu32.c', --=20 2.47.3