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Signed-off-by: Pierrick Bouvier --- target/arm/tcg/translate.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index ebcf68aea97..6ea48efbac2 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -22,7 +22,8 @@ =20 #include "translate.h" #include "translate-a32.h" -#include "tcg/tcg-op.h" +#define TCG_ADDRESS_BITS 32 +#include "tcg/tcg-op-mem.h" #include "qemu/log.h" #include "arm_ldst.h" #include "semihosting/semihost.h" @@ -909,14 +910,14 @@ MemOp pow2_align(unsigned i) * that the address argument is TCGv_i32 rather than TCGv. */ =20 -static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) +static TCGv_va gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) { - TCGv addr =3D tcg_temp_new(); - tcg_gen_extu_i32_tl(addr, a32); + TCGv_va addr =3D tcgv_va_temp_new(); + tcg_gen_mov_i32(addr, a32); =20 /* Not needed for user-mode BE32, where we use MO_BE instead. */ if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) { - tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE))); + tcg_gen_xori_i32(addr, addr, 4 - (1 << (op & MO_SIZE))); } return addr; } @@ -928,21 +929,21 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a= 32, MemOp op) void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr =3D gen_aa32_addr(s, a32, opc); + TCGv_va addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(val, addr, index, opc); } =20 void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr =3D gen_aa32_addr(s, a32, opc); + TCGv_va addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(val, addr, index, opc); } =20 void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr =3D gen_aa32_addr(s, a32, opc); + TCGv_va addr =3D gen_aa32_addr(s, a32, opc); =20 tcg_gen_qemu_ld_i64(val, addr, index, opc); =20 @@ -955,7 +956,7 @@ void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64= val, void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, int index, MemOp opc) { - TCGv addr =3D gen_aa32_addr(s, a32, opc); + TCGv_va addr =3D gen_aa32_addr(s, a32, opc); =20 /* Not needed for user-mode BE32, where we use MO_BE instead. */ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) =3D=3D MO_64) { @@ -2035,7 +2036,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, * architecturally 64-bit access, but instead do a 64-bit access * using MO_BE if appropriate and then split the two halves. */ - TCGv taddr =3D gen_aa32_addr(s, addr, opc); + TCGv_va taddr =3D gen_aa32_addr(s, addr, opc); =20 tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc); tcg_gen_mov_i64(cpu_exclusive_val, t64); @@ -2064,7 +2065,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, { TCGv_i32 t0, t1, t2; TCGv_i64 extaddr; - TCGv taddr; + TCGv_va taddr; TCGLabel *done_label; TCGLabel *fail_label; MemOp opc =3D size | MO_ALIGN | s->be_data; @@ -3791,7 +3792,7 @@ static void do_ldrd_load(DisasContext *s, TCGv_i32 ad= dr, int rt, int rt2) */ int mem_idx =3D get_mem_index(s); MemOp opc =3D MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; - TCGv taddr =3D gen_aa32_addr(s, addr, opc); + TCGv_va taddr =3D gen_aa32_addr(s, addr, opc); TCGv_i64 t64 =3D tcg_temp_new_i64(); TCGv_i32 tmp =3D tcg_temp_new_i32(); TCGv_i32 tmp2 =3D tcg_temp_new_i32(); @@ -3846,7 +3847,7 @@ static void do_strd_store(DisasContext *s, TCGv_i32 a= ddr, int rt, int rt2) */ int mem_idx =3D get_mem_index(s); MemOp opc =3D MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; - TCGv taddr =3D gen_aa32_addr(s, addr, opc); + TCGv_va taddr =3D gen_aa32_addr(s, addr, opc); TCGv_i32 t1 =3D load_reg(s, rt); TCGv_i32 t2 =3D load_reg(s, rt2); TCGv_i64 t64 =3D tcg_temp_new_i64(); @@ -4067,7 +4068,7 @@ DO_LDST(STRH, store, MO_UW) static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc) { TCGv_i32 addr, tmp; - TCGv taddr; + TCGv_va taddr; =20 opc |=3D s->be_data; addr =3D load_reg(s, a->rn); @@ -6881,6 +6882,7 @@ void arm_translate_code(CPUState *cpu, TranslationBlo= ck *tb, DisasContext dc =3D { }; const TranslatorOps *ops =3D &arm_translator_ops; CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(tb); + TCGType addr_type =3D is_a64(cpu_env(cpu)) ? TCG_TYPE_I64 : TCG_TYPE_I= 32; =20 if (EX_TBFLAG_AM32(tb_flags, THUMB)) { ops =3D &thumb_translator_ops; @@ -6891,6 +6893,5 @@ void arm_translate_code(CPUState *cpu, TranslationBlo= ck *tb, } #endif =20 - translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base, - tcg_default_addr_type()); + translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base, addr_t= ype); } --=20 2.47.3