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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.52; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276499302158500 Content-Type: text/plain; charset="utf-8" Instead of just the command number, include the instruction name to make de= bugging easier. Signed-off-by: Mohamed Mediouni --- target/i386/emulate/x86_emu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c index 55b1a68eb6..c2da1a133f 100644 --- a/target/i386/emulate/x86_emu.c +++ b/target/i386/emulate/x86_emu.c @@ -1399,8 +1399,8 @@ static void init_cmd_handler(void) bool exec_instruction(CPUX86State *env, struct x86_decode *ins) { if (!_cmd_handler[ins->cmd].handler) { - printf("Unimplemented handler (" TARGET_FMT_lx ") for %d (%x %x)\n= ", - env->eip, + printf("Unimplemented handler (" TARGET_FMT_lx ") for %s - %d (%x = %x)\n", + env->eip, decode_cmd_to_string(ins->cmd), ins->cmd, ins->opcode[0], ins->opcode_len > 1 ? ins->opcode[1] : 0); env->eip +=3D ins->len; --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sat, 04 Apr 2026 04:20:22 +0000 (UTC) Received: from localhost.localdomain (unknown [17.42.251.67]) by p00-icloudmta-asmtp-us-east-1a-10-percent-0 (Postfix) with ESMTPSA id 929071800148; Sat, 04 Apr 2026 04:20:20 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; t=1775276425; x=1777868425; bh=zl2db1VwfCW29E4LtwT7zz4buZdQP1VZYTXVu1kcs+o=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=fz8bzEf4cpzrpa6pUfLh63e79i0Do5CG6PYHm39CcVyB4eB2fPlUfsj4GMOufg62cgKMYc0OMay6gtDhjgRl1hHQYG0sTu1tDnp0b7t66GjUpWBGh3kcuPfdGxMp3lAEV+KJvaM99hTkRy8+7ojUS6rk+Q/GIaPkaOlbI2Vv2OK2M2dXxWHEZyoi35DCVTRvvNarAzH2VlXQuFtxCUYsTQmV0XaR2XYqWvEHf2g/eLpH1IhB2U2kIuvNbzX5gzUYXoYx4b1G6gOhDO82xApxzfAaMIfeUVnroEmFOHFICykm8tbpROdER/yxd5vAmml+r9tyG+5uyraVDjHFEgIAaA== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Wei Liu , Roman Bolshakov , Pedro Barbuda , Mohamed Mediouni , Phil Dennis-Jordan , Paolo Bonzini , Zhao Liu Subject: [PATCH v6 02/11] whpx: i386: x2apic emulation Date: Sat, 4 Apr 2026 06:20:06 +0200 Message-ID: <20260404042015.86580-3-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260404042015.86580-1-mohamed@unpredictable.fr> References: <20260404042015.86580-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: xIYV4e9xy6v-Nx_jBBiUlGjvillw0kr6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA0MDAzNCBTYWx0ZWRfX6i2K96GlZio+ WDjxYaUrwuLQSjy8LyrknFwHb7IxHtZqomZoHdYaRGmhhKEzjxRbfvivdR2gbqqoEJrHnwFowYK MMLw993SPgzUP5ooyKKqEtsBhPYE+KK8vhZbY7GZd+gXJ6Eg/92W3qSF8XrgPKTYenIzmJl9KAn sguQz74/CfW6Zk+d4PjUbSvH4OqmgTuQMN9RFy0B/FGHg/uiA6r1Yk19h1HecV/eCQfAuwDNlIa 8UKmCXfjk1iaTr4YcZKPGPBZX5MgpErGQy7dDxwTKNmV3VE2HHJTQ65WQ6I57xaRSqgg/ESGLAB ff12Xdqqhb3cY+SZ5SksAvraY/qbmUNeO5ZnTt1R3rzRnnMIf5RDVFs93pNkTA= X-Proofpoint-GUID: xIYV4e9xy6v-Nx_jBBiUlGjvillw0kr6 X-Authority-Info-Out: v=2.4 cv=KuBAGGWN c=1 sm=1 tr=0 ts=69d09187 cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117 a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=nj4AhdDZwDx412jv8JQA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_07,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 clxscore=1030 spamscore=0 phishscore=0 bulkscore=0 mlxscore=0 mlxlogscore=733 suspectscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2604040034 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.76; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276542765158500 Content-Type: text/plain; charset="utf-8" Add x2apic emulation to WHPX for the kernel-irqchip=3Doff case. Unfortunately, it looks like there isn't a workaround available for proper behavior of PIC interrupts when kernel-irqchip=3Don for Windows 10. The OS is out of support outside of extended security updates so this will not be addressed. The performance boost is quite visible for multicore guests. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 134 +++++++++++++++++++++++++++++++++++- 1 file changed, 133 insertions(+), 1 deletion(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index e56ae2b343..4127440c0c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -1082,6 +1082,8 @@ HRESULT whpx_set_exception_exit_bitmap(UINT64 excepti= ons) /* Register for MSR and CPUID exits */ memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); prop.ExtendedVmExits.X64MsrExit =3D 1; + prop.ExtendedVmExits.X64CpuidExit =3D 1; + if (exceptions !=3D 0) { prop.ExtendedVmExits.ExceptionExit =3D 1; } @@ -1898,6 +1900,18 @@ int whpx_vcpu_run(CPUState *cpu) WHV_REGISTER_NAME reg_names[3]; UINT32 reg_count; bool is_known_msr =3D 0;=20 + uint64_t val; + + if (vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) { + val =3D ((uint32_t)vcpu->exit_ctx.MsrAccess.Rax) | + ((uint64_t)(vcpu->exit_ctx.MsrAccess.Rdx) << 32); + } else { + /* + * Workaround for [-Werror=3Dmaybe-uninitialized] + * with GCC. Not needed with Clang. + */ + val =3D 0; + } =20 reg_names[0] =3D WHvX64RegisterRip; reg_names[1] =3D WHvX64RegisterRax; @@ -1911,7 +1925,47 @@ int whpx_vcpu_run(CPUState *cpu) && !vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite && !whpx_irqchip_in_kernel()) { is_known_msr =3D 1; - reg_values[1].Reg32 =3D (uint32_t)X86_CPU(cpu)->env.apic_b= us_freq; + val =3D X86_CPU(cpu)->env.apic_bus_freq; + } + + if (!whpx_irqchip_in_kernel() && + vcpu->exit_ctx.MsrAccess.MsrNumber =3D=3D MSR_IA32_APICBAS= E) { + is_known_msr =3D 1; + if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) { + /* Read path unreachable on Hyper-V */ + abort(); + } else { + WHV_REGISTER_VALUE reg =3D {.Reg64 =3D val}; + int msr_ret =3D cpu_set_apic_base(X86_CPU(cpu)->apic_s= tate, val); + if (msr_ret < 0) { + x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0= D_GPF, 0); + } + whpx_set_reg(cpu, WHvX64RegisterApicBase, reg); + } + } + + if (!whpx_irqchip_in_kernel() && + vcpu->exit_ctx.MsrAccess.MsrNumber >=3D MSR_APIC_START && + vcpu->exit_ctx.MsrAccess.MsrNumber <=3D MSR_APIC_END) { + int index =3D vcpu->exit_ctx.MsrAccess.MsrNumber - MSR_API= C_START; + int msr_ret; + is_known_msr =3D 1; + if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) { + bql_lock(); + msr_ret =3D apic_msr_read(X86_CPU(cpu)->apic_state, in= dex, &val); + bql_unlock(); + reg_values[1].Reg64 =3D val; + if (msr_ret < 0) { + x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0= D_GPF, 0); + } + } else { + bql_lock(); + msr_ret =3D apic_msr_write(X86_CPU(cpu)->apic_state, i= ndex, val); + bql_unlock(); + if (msr_ret < 0) { + x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0= D_GPF, 0); + } + } } /* * For all unsupported MSR access we: @@ -1921,6 +1975,11 @@ int whpx_vcpu_run(CPUState *cpu) reg_count =3D vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite ? 1 : 3; =20 + if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) { + reg_values[1].Reg32 =3D (uint32_t)val; + reg_values[2].Reg32 =3D (uint32_t)(val >> 32); + } + if (!is_known_msr) { trace_whpx_unsupported_msr_access(vcpu->exit_ctx.MsrAccess= .MsrNumber, vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite); @@ -1939,6 +1998,47 @@ int whpx_vcpu_run(CPUState *cpu) ret =3D 0; break; } + case WHvRunVpExitReasonX64Cpuid: { + WHV_REGISTER_VALUE reg_values[5] =3D {0}; + WHV_REGISTER_NAME reg_names[5]; + UINT32 reg_count =3D 5; + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + + reg_names[0] =3D WHvX64RegisterRip; + reg_names[1] =3D WHvX64RegisterRax; + reg_names[2] =3D WHvX64RegisterRcx; + reg_names[3] =3D WHvX64RegisterRdx; + reg_names[4] =3D WHvX64RegisterRbx; + + reg_values[0].Reg64 =3D + vcpu->exit_ctx.VpContext.Rip + + vcpu->exit_ctx.VpContext.InstructionLength; + + reg_values[1].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRax; + reg_values[2].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRcx; + reg_values[3].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRdx; + reg_values[4].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRbx; + + if (vcpu->exit_ctx.CpuidAccess.Rax =3D=3D 1) { + if (cpu_has_x2apic_feature(env)) { + reg_values[2].Reg64 |=3D CPUID_EXT_X2APIC; + } + } + + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( + whpx->partition, + cpu->cpu_index, + reg_names, reg_count, + reg_values); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set CpuidAccess state " + " registers, hr=3D%08lx", hr); + } + ret =3D 0; + break; + } case WHvRunVpExitReasonException: whpx_get_registers(cpu, WHPX_LEVEL_FULL_STATE); =20 @@ -2136,6 +2236,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) WHV_PROCESSOR_FEATURES_BANKS processor_features; WHV_PROCESSOR_PERFMON_FEATURES perfmon_features; bool is_legacy_os =3D false; + UINT32 cpuidExitList[] =3D {1}; =20 whpx =3D &whpx_global; =20 @@ -2354,6 +2455,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) /* Register for MSR and CPUID exits */ memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); prop.ExtendedVmExits.X64MsrExit =3D 1; + prop.ExtendedVmExits.X64CpuidExit =3D 1; =20 hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, @@ -2366,6 +2468,36 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 + memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); + prop.X64MsrExitBitmap.UnhandledMsrs =3D 1; + if (!whpx_irqchip_in_kernel()) { + prop.X64MsrExitBitmap.ApicBaseMsrWrite =3D 1; + } + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeX64MsrExitBitmap, + &prop, + sizeof(WHV_PARTITION_PROPERTY)); + if (FAILED(hr)) { + error_report("WHPX: Failed to set MSR exit bitmap, hr=3D%08lx", hr= ); + ret =3D -EINVAL; + goto error; + } + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeCpuidExitList, + cpuidExitList, + RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set partition CpuidExitList hr=3D%08= lx", + hr); + ret =3D -EINVAL; + goto error; + } + /* * We do not want to intercept any exceptions from the guest, * until we actually start debugging with gdb. --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.104; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276503359154100 Content-Type: text/plain; charset="utf-8" Windows 10 doesn't have the API for this, so using this only for Windows 11. Signed-off-by: Mohamed Mediouni --- include/system/whpx-internal.h | 9 ++++ target/i386/cpu.c | 25 ++++++++++++ target/i386/whpx/whpx-all.c | 75 ++++++++++++++++++++++++++++++++-- target/i386/whpx/whpx-i386.h | 4 ++ 4 files changed, 109 insertions(+), 4 deletions(-) create mode 100644 target/i386/whpx/whpx-i386.h diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 8482901f71..5902124b63 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -73,6 +73,14 @@ void whpx_apic_get(APICCommonState *s); X(HRESULT, WHvGetVirtualProcessorRegisters, (WHV_PARTITION_HANDLE Partit= ion, UINT32 VpIndex, const WHV_REGISTER_NAME* RegisterNames, UINT32 Registe= rCount, WHV_REGISTER_VALUE* RegisterValues)) \ X(HRESULT, WHvSetVirtualProcessorRegisters, (WHV_PARTITION_HANDLE Partit= ion, UINT32 VpIndex, const WHV_REGISTER_NAME* RegisterNames, UINT32 Registe= rCount, const WHV_REGISTER_VALUE* RegisterValues)) \ =20 +#ifdef __x86_64__ +#define LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL_ARCH(X) \ + X(HRESULT, WHvGetVirtualProcessorCpuidOutput, \ + (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, UINT32 Eax, \ + UINT32 Ecx, WHV_CPUID_OUTPUT *CpuidOutput)) +#else +#define LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL_ARCH(X) +#endif /* * These are supplemental functions that may not be present * on all versions and are not critical for basic functionality. @@ -89,6 +97,7 @@ void whpx_apic_get(APICCommonState *s); UINT32 StateSize)) \ X(HRESULT, WHvResetPartition, \ (WHV_PARTITION_HANDLE Partition)) \ + LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL_ARCH(X) =20 #define WHP_DEFINE_TYPE(return_type, function_name, signature) \ typedef return_type (WINAPI *function_name ## _t) signature; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c6fd1dc00e..0000093fa3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -26,6 +26,8 @@ #include "tcg/helper-tcg.h" #include "exec/translation-block.h" #include "system/hvf.h" +#include "system/whpx.h" +#include "whpx/whpx-i386.h" #include "hvf/hvf-i386.h" #include "kvm/kvm_i386.h" #include "kvm/tdx.h" @@ -8087,6 +8089,17 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w) r =3D hvf_get_supported_cpuid(wi->cpuid.eax, wi->cpuid.ecx, wi->cpuid.reg); + } else if (whpx_enabled()) { + if (wi->type !=3D CPUID_FEATURE_WORD) { + return 0; + } + if (whpx_is_legacy_os()) { + r =3D wi->tcg_features; + } else { + r =3D whpx_get_supported_cpuid(wi->cpuid.eax, + wi->cpuid.ecx, + wi->cpuid.reg); + } } else if (tcg_enabled() || qtest_enabled()) { r =3D wi->tcg_features; } else { @@ -8168,6 +8181,18 @@ static void x86_cpu_get_supported_cpuid(uint32_t fun= c, uint32_t index, *ebx =3D hvf_get_supported_cpuid(func, index, R_EBX); *ecx =3D hvf_get_supported_cpuid(func, index, R_ECX); *edx =3D hvf_get_supported_cpuid(func, index, R_EDX); + } else if (whpx_enabled()) { + if (whpx_is_legacy_os()) { + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + } else { + *eax =3D whpx_get_supported_cpuid(func, index, R_EAX); + *ebx =3D whpx_get_supported_cpuid(func, index, R_EBX); + *ecx =3D whpx_get_supported_cpuid(func, index, R_ECX); + *edx =3D whpx_get_supported_cpuid(func, index, R_EDX); + } } else { *eax =3D 0; *ebx =3D 0; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 4127440c0c..2d527b90dd 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -36,6 +36,7 @@ #include "system/whpx-accel-ops.h" #include "system/whpx-all.h" #include "system/whpx-common.h" +#include "whpx-i386.h" =20 #include "emulate/x86_decode.h" #include "emulate/x86_emu.h" @@ -49,6 +50,8 @@ /* for kernel-irqchip=3Doff */ #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 =20 +static bool is_modern_os =3D true; + static const WHV_REGISTER_NAME whpx_register_names[] =3D { =20 /* X64 General purpose registers */ @@ -1062,6 +1065,71 @@ static void whpx_init_emu(void) init_emu(&whpx_x86_emul_ops); } =20 +bool whpx_is_legacy_os(void) +{ + return !is_modern_os; +} + +uint32_t whpx_get_supported_cpuid(uint32_t func, uint32_t idx, int reg) +{ + WHV_CPUID_OUTPUT output; + uint32_t eax, ebx, ecx, edx; + uint32_t cpu_index =3D 0; + bool temp_cpu =3D true; + HRESULT hr; + + hr =3D whp_dispatch.WHvCreateVirtualProcessor( + whpx_global.partition, cpu_index, 0); + + /* This means that the CPU already exists... */ + if (FAILED(hr)) { + temp_cpu =3D false; + } + + hr =3D whp_dispatch.WHvGetVirtualProcessorCpuidOutput(whpx_global.part= ition, + cpu_index, func, idx, &output); + + if (FAILED(hr)) { + abort(); + } + + if (temp_cpu) { + hr =3D whp_dispatch.WHvDeleteVirtualProcessor(whpx_global.partitio= n, cpu_index); + if (FAILED(hr)) { + abort(); + } + } + + eax =3D output.Eax; + ebx =3D output.Ebx; + ecx =3D output.Ecx; + edx =3D output.Edx; + + /* + * We can emulate X2APIC even for the kernel-irqchip=3Doff case. + * CPUID_EXT_HYPERVISOR and CPUID_HT should be considered present + * always, so report them as unconditionally supported here. + */ + if (func =3D=3D 1) { + ecx |=3D CPUID_EXT_X2APIC; + ecx |=3D CPUID_EXT_HYPERVISOR; + edx |=3D CPUID_HT; + } + + switch (reg) { + case R_EAX: + return eax; + case R_EBX: + return ebx; + case R_ECX: + return ecx; + case R_EDX: + return edx; + default: + return 0; + } +} + /* * Controls whether we should intercept various exceptions on the guest, * namely breakpoint/single-step events. @@ -2235,7 +2303,6 @@ int whpx_accel_init(AccelState *as, MachineState *ms) WHV_CAPABILITY_FEATURES features =3D {0}; WHV_PROCESSOR_FEATURES_BANKS processor_features; WHV_PROCESSOR_PERFMON_FEATURES perfmon_features; - bool is_legacy_os =3D false; UINT32 cpuidExitList[] =3D {1}; =20 whpx =3D &whpx_global; @@ -2395,7 +2462,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) if (FAILED(hr)) { warn_report("WHPX: Failed to get performance " "monitoring features, hr=3D%08lx", hr); - is_legacy_os =3D true; + is_modern_os =3D false; } else { hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, @@ -2435,7 +2502,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) synthetic_features.Bank0.DirectSyntheticTimers =3D 1; } =20 - if (!is_legacy_os && whpx->hyperv_enlightenments_allowed) { + if (is_modern_os && whpx->hyperv_enlightenments_allowed) { hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks, @@ -2446,7 +2513,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) ret =3D -EINVAL; goto error; } - } else if (is_legacy_os && whpx->hyperv_enlightenments_required) { + } else if (!is_modern_os && whpx->hyperv_enlightenments_required) { error_report("Hyper-V enlightenments not available on legacy Windo= ws"); ret =3D -EINVAL; goto error; diff --git a/target/i386/whpx/whpx-i386.h b/target/i386/whpx/whpx-i386.h new file mode 100644 index 0000000000..6db9a75d39 --- /dev/null +++ b/target/i386/whpx/whpx-i386.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +uint32_t whpx_get_supported_cpuid(uint32_t func, uint32_t idx, int reg); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.64; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276532646158500 Content-Type: text/plain; charset="utf-8" AccessHypercallRegs was present twice so clean that up. Remove TbFlushHypercalls (and its extended Gva range sub-feature) from the user-mode LAPIC case as it behaves oddly there. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 2d527b90dd..0908dfd134 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2489,10 +2489,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) synthetic_features.Bank0.AccessPartitionReferenceTsc =3D 1; synthetic_features.Bank0.AccessHypercallRegs =3D 1; synthetic_features.Bank0.AccessFrequencyRegs =3D 1; - synthetic_features.Bank0.EnableExtendedGvaRangesForFlushVirtualAddress= List =3D 1; synthetic_features.Bank0.AccessVpIndex =3D 1; - synthetic_features.Bank0.AccessHypercallRegs =3D 1; - synthetic_features.Bank0.TbFlushHypercalls =3D 1; =20 if (whpx_irqchip_in_kernel()) { synthetic_features.Bank0.AccessSynicRegs =3D 1; @@ -2500,6 +2497,12 @@ int whpx_accel_init(AccelState *as, MachineState *ms) synthetic_features.Bank0.AccessIntrCtrlRegs =3D 1; synthetic_features.Bank0.SyntheticClusterIpi =3D 1; synthetic_features.Bank0.DirectSyntheticTimers =3D 1; + /* + * These technically work without the Hyper-V LAPIC + * but behave oddly for multi-core VMs. + */ + synthetic_features.Bank0.TbFlushHypercalls =3D 1; + synthetic_features.Bank0.EnableExtendedGvaRangesForFlushVirtualAdd= ressList =3D 1; } =20 if (is_modern_os && whpx->hyperv_enlightenments_allowed) { --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1775276498; cv=none; d=zohomail.com; s=zohoarc; b=audKPgkgJnXmLr79YyV67P8tJ+ZDjHTLgf4k6RxLflZUa0zZEiVsxx713KTA7P4IBAXBSZULKA+zaCh+xP1N7ssqbrGS5CuLWdtUBkBRSE1wiyu1c4G8PxpvLxazTQhzETSet5cM5j3M7TYUqb/U3ksdoLoHS0b/rEXW5klp+bM= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.35; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276503868154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 0908dfd134..66f263558f 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2281,11 +2281,18 @@ error: return ret; } =20 +static PropValue whpx_default_props[] =3D { + { "x2apic", "on" }, + { NULL, NULL }, +}; + + void whpx_cpu_instance_init(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 host_cpu_instance_init(cpu); + x86_cpu_apply_props(cpu, whpx_default_props); } =20 /* --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1775276527; cv=none; d=zohomail.com; s=zohoarc; b=W51wTkh7BWQ96dfHcw3xguTiWitQgAd0h8rbwugNRCGdIWzmwjuXgOnrRa26cdX7w3l0HeNZreBUfBwPjkCJKvUdGy4xyF85mi4+eLzIqy7q1E4nVq91kr3zGV5naPsxlmYsfPs1x1iopF6mNY7BYl1fBbFacqR2pPvwn+7kF5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775276527; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.35; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276528919158500 Content-Type: text/plain; charset="utf-8" Was removed in 2c08624 but it's still useful for Windows 10 so reintroduce it there. And this time, actually make it work by reporting the hypervisor bit in CPUID. Also pretend to be KVM, with the only capability reported being X2APIC support. Although looks like Linux doesn't use that vmware leaf... Signed-off-by: Mohamed Mediouni --- accel/whpx/whpx-common.c | 2 ++ include/system/whpx-internal.h | 1 + target/arm/whpx/whpx-all.c | 1 + target/i386/whpx/whpx-all.c | 55 ++++++++++++++++++++++++++++------ 4 files changed, 50 insertions(+), 9 deletions(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index b813a5d9d2..59be996aef 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -550,6 +550,8 @@ static void whpx_accel_instance_init(Object *obj) =20 whpx->hyperv_enlightenments_allowed =3D true; whpx->hyperv_enlightenments_required =3D false; + /* Value determined at whpx_accel_init */ + whpx->hyperv_enlightenments_enabled =3D false; } =20 static const TypeInfo whpx_accel_type =3D { diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 5902124b63..cf782cf5f8 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -45,6 +45,7 @@ struct whpx_state { =20 bool hyperv_enlightenments_allowed; bool hyperv_enlightenments_required; + bool hyperv_enlightenments_enabled; =20 }; =20 diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index bbf0f6be96..4019a513aa 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -968,6 +968,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) * as they're not needed for performance. */ if (whpx->hyperv_enlightenments_required) { + whpx->hyperv_enlightenments_enabled =3D true; hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks, diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 66f263558f..03233d1b94 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2083,14 +2083,49 @@ int whpx_vcpu_run(CPUState *cpu) vcpu->exit_ctx.VpContext.Rip + vcpu->exit_ctx.VpContext.InstructionLength; =20 - reg_values[1].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRax; - reg_values[2].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRcx; - reg_values[3].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRdx; - reg_values[4].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRbx; - - if (vcpu->exit_ctx.CpuidAccess.Rax =3D=3D 1) { - if (cpu_has_x2apic_feature(env)) { - reg_values[2].Reg64 |=3D CPUID_EXT_X2APIC; + if (whpx_is_legacy_os()) { + reg_values[1].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Default= ResultRax; + reg_values[2].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Default= ResultRcx; + reg_values[3].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Default= ResultRdx; + reg_values[4].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Default= ResultRbx; + } else { + cpu_x86_cpuid(env, vcpu->exit_ctx.CpuidAccess.Rax, + vcpu->exit_ctx.CpuidAccess.Rcx, + (UINT32 *)®_values[1].Reg32, + (UINT32 *)®_values[4].Reg32, (UINT32 *)®_values[= 2].Reg32, + (UINT32 *)®_values[3].Reg32); + } + + if (!whpx->hyperv_enlightenments_enabled) { + switch (vcpu->exit_ctx.CpuidAccess.Rax) { + case 1: + if (cpu_has_x2apic_feature(env)) { + reg_values[2].Reg64 |=3D CPUID_EXT_X2APIC; + } + reg_values[2].Reg64 |=3D CPUID_EXT_HYPERVISOR; + break; + case 0x40000000: + /* report KVM */ + if (x86_cpu->vmware_cpuid_freq) { + reg_values[1].Reg64 =3D 0x40000010; + } else { + reg_values[1].Reg64 =3D 0x40000001; + } + reg_values[4].Reg64 =3D 0x4b4d564b; + reg_values[2].Reg64 =3D 0x564b4d56; + reg_values[3].Reg64 =3D 0x4d; + break; + case 0x40000001: + /* report X2APIC */ + reg_values[1].Reg64 =3D reg_values[4].Reg64 =3D + reg_values[2].Reg64 =3D 1 << 15; + break; + case 0x40000010: + if (x86_cpu->vmware_cpuid_freq) { + reg_values[1].Reg64 =3D env->tsc_khz; + reg_values[4].Reg64 =3D env->apic_bus_freq / 1000;= /* Hz to KHz */ + } + break; } } =20 @@ -2311,6 +2346,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) WHV_PROCESSOR_FEATURES_BANKS processor_features; WHV_PROCESSOR_PERFMON_FEATURES perfmon_features; UINT32 cpuidExitList[] =3D {1}; + UINT32 cpuidExitList_nohyperv[] =3D {1, 0x40000000, 0x40000001, 0x4000= 0010}; =20 whpx =3D &whpx_global; =20 @@ -2513,6 +2549,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) } =20 if (is_modern_os && whpx->hyperv_enlightenments_allowed) { + whpx->hyperv_enlightenments_enabled =3D true; hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks, @@ -2565,7 +2602,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, WHvPartitionPropertyCodeCpuidExitList, - cpuidExitList, + whpx->hyperv_enlightenments_enabled ? cpuidExitList : cpuidExitLis= t_nohyperv, RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32)); =20 if (FAILED(hr)) { --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1775276521; cv=none; d=zohomail.com; s=zohoarc; b=mOlMRLAfIVqDvnue0CXqsKVPcrxaIeO3ICz1XRXK9jgFiEzBYLRcZw1+61wkzmN5t8OOnwIhWzs6hlhLymmHYTORQKCRn8U7/YdDQzQxnjgxdn9dXSnoODM4XXpCVOjb5TfFaEefVKA9GSalVUMzXlApS8s262XdrrDsvu/fejE= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.105; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276524620154100 Content-Type: text/plain; charset="utf-8" Unlike the implementation in QEMU 10.2, this one works. It's not optimal though as it doesn't use the Hyper-V support for this. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 39 ++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 03233d1b94..3e006496be 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2127,6 +2127,35 @@ int whpx_vcpu_run(CPUState *cpu) } break; } + } else { + switch (vcpu->exit_ctx.CpuidAccess.Rax) { + case 0x40000000: + case 0x40000001: + case 0x40000010: + reg_values[1].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Def= aultResultRax; + reg_values[2].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Def= aultResultRcx; + reg_values[3].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Def= aultResultRdx; + reg_values[4].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Def= aultResultRbx; + break; + } + } + + /* Dynamic depending on XCR0 and XSS, so query DefaultResult */ + if (vcpu->exit_ctx.CpuidAccess.Rax =3D=3D 0x07 + && vcpu->exit_ctx.CpuidAccess.Rcx =3D=3D 0) { + if (vcpu->exit_ctx.CpuidAccess.DefaultResultRdx + & CPUID_7_0_EDX_CET_IBT) { + reg_values[3].Reg32 |=3D CPUID_7_0_EDX_CET_IBT; + } else { + reg_values[3].Reg32 &=3D ~CPUID_7_0_EDX_CET_IBT; + } + + if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx + & CPUID_7_0_ECX_CET_SHSTK) { + reg_values[2].Reg32 |=3D CPUID_7_0_ECX_CET_SHSTK; + } else { + reg_values[2].Reg32 &=3D ~CPUID_7_0_ECX_CET_SHSTK; + } } =20 hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( @@ -2345,8 +2374,12 @@ int whpx_accel_init(AccelState *as, MachineState *ms) WHV_CAPABILITY_FEATURES features =3D {0}; WHV_PROCESSOR_FEATURES_BANKS processor_features; WHV_PROCESSOR_PERFMON_FEATURES perfmon_features; - UINT32 cpuidExitList[] =3D {1}; - UINT32 cpuidExitList_nohyperv[] =3D {1, 0x40000000, 0x40000001, 0x4000= 0010}; + + UINT32 cpuidExitList[] =3D {0x0, 0x1, 0x6, 0x7, 0x14, 0x24, 0x29, 0x1E, + 0x40000000, 0x40000001, 0x40000010, 0x80000000, 0x80000001, + 0x80000002, 0x80000003, 0x80000004, 0x80000007, 0x80000008, + 0x8000000A, 0x80000021, 0x80000022, 0xC0000000, 0xC0000001}; + UINT32 cpuidExitList_legacy_os[] =3D {1, 0x40000000, 0x40000001, 0x400= 00010}; =20 whpx =3D &whpx_global; =20 @@ -2602,7 +2635,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, WHvPartitionPropertyCodeCpuidExitList, - whpx->hyperv_enlightenments_enabled ? cpuidExitList : cpuidExitLis= t_nohyperv, + !whpx_is_legacy_os() ? cpuidExitList : cpuidExitList_legacy_os, RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32)); =20 if (FAILED(hr)) { --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1775276503; cv=none; d=zohomail.com; s=zohoarc; b=En3fJGAA1wNViXRfeIvwMAMm2qnYRNNULOeZQYy+JJUhYchDu+y5MylDZ3KpJOJ2vXplsvyYa76T508yqmnmO5Yt85tq+Y78bnJAzpq85K5uBAvcD6At71dfX6Bs7P9JPZ1jzezAcE0zQAlImAGMPaxXskE4wh+z7aRcr11zmFk= ARC-Message-Signature: i=1; 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charset="utf-8" This was really... quite broken. After fixing this, Windows boots with kernel-irqchip=3Doff. Signed-off-by: Mohamed Mediouni --- include/system/whpx-common.h | 1 + target/i386/whpx/whpx-all.c | 54 ++++++++++-------------------------- 2 files changed, 15 insertions(+), 40 deletions(-) diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h index 04289afd97..3406c20fec 100644 --- a/include/system/whpx-common.h +++ b/include/system/whpx-common.h @@ -4,6 +4,7 @@ =20 struct AccelCPUState { bool window_registered; + int window_priority; bool interruptable; bool ready_for_pic_interrupt; uint64_t tpr; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 3e006496be..97284b954b 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -371,28 +371,6 @@ static int whpx_set_tsc(CPUState *cpu) return 0; } =20 -/* - * The CR8 register in the CPU is mapped to the TPR register of the APIC, - * however, they use a slightly different encoding. Specifically: - * - * APIC.TPR[bits 7:4] =3D CR8[bits 3:0] - * - * This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64 - * and IA-32 Architectures Software Developer's Manual. - * - * The functions below translate the value of CR8 to TPR and vice versa. - */ - -static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr) -{ - return tpr >> 4; -} - -static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) -{ - return cr8 << 4; -} - void whpx_set_registers(CPUState *cpu, WHPXStateLevel level) { struct whpx_state *whpx =3D &whpx_global; @@ -421,7 +399,7 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel l= evel) v86 =3D (env->eflags & VM_MASK); r86 =3D !(env->cr[0] & CR0_PE_MASK); =20 - vcpu->tpr =3D whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_stat= e)); + vcpu->tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state); vcpu->apic_base =3D cpu_get_apic_base(x86_cpu->apic_state); =20 idx =3D 0; @@ -692,17 +670,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel = level) hr); } =20 - if (whpx_irqchip_in_kernel()) { - /* - * Fetch the TPR value from the emulated APIC. It may get overwrit= ten - * below with the value from CR8 returned by - * WHvGetVirtualProcessorRegisters(). - */ - whpx_apic_get(x86_cpu->apic_state); - vcpu->tpr =3D whpx_apic_tpr_to_cr8( - cpu_get_apic_tpr(x86_cpu->apic_state)); - } - idx =3D 0; =20 /* Indexes for first 16 registers match between HV and QEMU definition= s */ @@ -751,7 +718,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) tpr =3D vcxt.values[idx++].Reg64; if (tpr !=3D vcpu->tpr) { vcpu->tpr =3D tpr; - cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr)); + cpu_set_apic_tpr(x86_cpu->apic_state, tpr); } =20 /* 8 Debug Registers - Skipped */ @@ -1605,6 +1572,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) UINT32 reg_count =3D 0; WHV_REGISTER_VALUE reg_values[3]; WHV_REGISTER_NAME reg_names[3]; + int irr =3D apic_get_highest_priority_irr(x86_cpu->apic_state); =20 memset(&new_int, 0, sizeof(new_int)); memset(reg_values, 0, sizeof(reg_values)); @@ -1643,7 +1611,8 @@ static void whpx_vcpu_pre_run(CPUState *cpu) /* Get pending hard interruption or replay one that was overwritten */ if (!whpx_irqchip_in_kernel()) { if (!vcpu->interruption_pending && - vcpu->interruptable && (env->eflags & IF_MASK)) { + vcpu->interruptable && (env->eflags & IF_MASK) + && (irr =3D=3D -1 || vcpu->tpr < irr)) { assert(!new_int.InterruptionPending); if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); @@ -1690,7 +1659,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } =20 /* Sync the TPR to the CR8 if was modified during the intercept */ - tpr =3D whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state)); + tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state); if (tpr !=3D vcpu->tpr) { vcpu->tpr =3D tpr; reg_values[reg_count].Reg64 =3D tpr; @@ -1700,13 +1669,18 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } =20 /* Update the state of the interrupt delivery notification */ - if (!vcpu->window_registered && + if ((!vcpu->window_registered || vcpu->window_priority < irr) && cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { + if (irr =3D=3D -1) { + irr =3D 0; + } reg_values[reg_count].DeliverabilityNotifications =3D (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) { - .InterruptNotification =3D 1 + .InterruptNotification =3D 1, + .InterruptPriority =3D irr }; vcpu->window_registered =3D 1; + vcpu->window_priority =3D irr; reg_names[reg_count] =3D WHvX64RegisterDeliverabilityNotifications; reg_count +=3D 1; } @@ -1737,7 +1711,7 @@ static void whpx_vcpu_post_run(CPUState *cpu) if (vcpu->tpr !=3D tpr) { vcpu->tpr =3D tpr; bql_lock(); - cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->t= pr)); + cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr); bql_unlock(); } =20 --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1775276505; cv=none; d=zohomail.com; s=zohoarc; b=eXPIuh7u83sTQAxnqTMArXeqilZAZ+m1r1F+4fbYV8rO5mCNQkV/zHJlkFq7YYTwimt0AaedQ2Gd6eNJ3jkaOHINoKWyctpbL1NW7IjlsWzqITa0ejbbwTQbxpvUUOmJuWuLP/OCOgG+bHLaroCY/M2kl9nhj/C7GvmgCwQM9Jw= ARC-Message-Signature: i=1; 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t=1775276435; x=1777868435; bh=+hn/b907vnbE0dvYvh4HHSsKO/zS5B54ItsSB46awcE=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=F7C+hvoSOQ7nyEK9WalGYQDhXBBVkrL8XcjRS/zFdwlgiLzLqTW2vUZQZNAZm96hNSPLWb1ZPvM1a2i0NJlFoWM9ZMER5Nbujii1d6sMVlu/cwbTrmlV6i/3cbk22/zc7HjX454SkEEoL1pJRmfNaEgTmzmqFVxil84fucQ0sc8A5M+h3ESn/752Gf/O/9ZaIecoGqHWR166zCeW7ZoCAXIoZpJySvSzlWGYwU1bgJXwvO+UXt4Gsi/ivOHP4tgcl0BJQwPlVn8tJuTmcJ0G+HC8xqC/cb2eksdR2bpjUFxtS02AXwZrdF6LNDG4S1o1OB4t0Fojyr/MVZBugQonng== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Wei Liu , Roman Bolshakov , Pedro Barbuda , Mohamed Mediouni , Phil Dennis-Jordan , Paolo Bonzini , Zhao Liu Subject: [PATCH v6 09/11] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off Date: Sat, 4 Apr 2026 06:20:13 +0200 Message-ID: <20260404042015.86580-10-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260404042015.86580-1-mohamed@unpredictable.fr> References: <20260404042015.86580-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA0MDAzNCBTYWx0ZWRfX02eIjIs0fE6D xM5Pc7voNyL5u/dLKmo+ZSGAltf9EWGQUJxQ4fhR+UbG/YO+TyQyILx4m8Qo9pr/NJoUePH1w39 SxzOd9fCg5C3iBIK7L2w+3Uw7P1oIa7D7NrYUMwwusJuyU/AtbiHC36K6s5KSyzwd1zzj7hdgwg q9Z4OTXrAMcqwsqUTJs1/gIU7f57B97U9jJbps/MMXb9Fo/Vd9e3kb29fWf8FocLqb2v4WarPBK Wkpvzd0o4yKjZTYIoFd3NMwohb59dEz/dsJgQpnsYi4M/03k8+2gLyPV6y81DVXHKWTd9DsR5Va FHdQ95zHi6m6JANryi0nx1NQzCp3DdWuzzajZwo1mppawnnuPoSS7q5p5ulJEE= X-Proofpoint-ORIG-GUID: l7WeCXRaIsYgVuj_Bxd4oaVVP5mxde-X X-Authority-Info-Out: v=2.4 cv=aqW/yCZV c=1 sm=1 tr=0 ts=69d09191 cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117 a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=4IdwVP5-j8YZXVcKM5MA:9 X-Proofpoint-GUID: l7WeCXRaIsYgVuj_Bxd4oaVVP5mxde-X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_07,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=0 clxscore=1030 mlxlogscore=866 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2604040034 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.12; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276507962154100 Content-Type: text/plain; charset="utf-8" When kernel-irqchip=3Don, manage TPR as part of the APIC state instead enti= rely. This fixes some failure to set state errors. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 97284b954b..a3e91ca533 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -93,7 +93,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] =3D { WHvX64RegisterCr2, WHvX64RegisterCr3, WHvX64RegisterCr4, - WHvX64RegisterCr8, =20 /* X64 Debug Registers */ /* @@ -457,8 +456,11 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel = level) vcxt.values[idx++].Reg64 =3D env->cr[3]; assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr4); vcxt.values[idx++].Reg64 =3D env->cr[4]; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr8); - vcxt.values[idx++].Reg64 =3D vcpu->tpr; + /* For kernel-irqchip=3Don, TPR is managed as part of APIC state */ + if (!whpx_irqchip_in_kernel()) { + WHV_REGISTER_VALUE cr8 =3D {.Reg64 =3D vcpu->tpr}; + whpx_set_reg(cpu, WHvX64RegisterCr8, cr8); + } =20 /* 8 Debug Registers - Skipped */ =20 @@ -714,11 +716,14 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel= level) env->cr[3] =3D vcxt.values[idx++].Reg64; assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr4); env->cr[4] =3D vcxt.values[idx++].Reg64; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr8); - tpr =3D vcxt.values[idx++].Reg64; - if (tpr !=3D vcpu->tpr) { - vcpu->tpr =3D tpr; - cpu_set_apic_tpr(x86_cpu->apic_state, tpr); + + /* For kernel-irqchip=3Don, TPR is managed as part of APIC state */ + if (!whpx_irqchip_in_kernel()) { + tpr =3D vcpu->exit_ctx.VpContext.Cr8; + if (tpr !=3D vcpu->tpr) { + vcpu->tpr =3D tpr; + cpu_set_apic_tpr(x86_cpu->apic_state, tpr); + } } =20 /* 8 Debug Registers - Skipped */ @@ -1660,7 +1665,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 /* Sync the TPR to the CR8 if was modified during the intercept */ tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state); - if (tpr !=3D vcpu->tpr) { + if (!whpx_irqchip_in_kernel() && tpr !=3D vcpu->tpr) { vcpu->tpr =3D tpr; reg_values[reg_count].Reg64 =3D tpr; qatomic_set(&cpu->exit_request, true); @@ -1707,12 +1712,14 @@ static void whpx_vcpu_post_run(CPUState *cpu) =20 env->eflags =3D vcpu->exit_ctx.VpContext.Rflags; =20 - uint64_t tpr =3D vcpu->exit_ctx.VpContext.Cr8; - if (vcpu->tpr !=3D tpr) { - vcpu->tpr =3D tpr; - bql_lock(); - cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr); - bql_unlock(); + if (!whpx_irqchip_in_kernel()) { + uint64_t tpr =3D vcpu->exit_ctx.VpContext.Cr8; + if (vcpu->tpr !=3D tpr) { + vcpu->tpr =3D tpr; + bql_lock(); + cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr); + bql_unlock(); + } } =20 vcpu->interruption_pending =3D --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.53; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276528484154100 Content-Type: text/plain; charset="utf-8" Move WHvCapabilityCodeProcessorPerfmonFeatures queries as that's how we distinguish if on a legacy OS. Now that Windows guests are booting, disable kernel-irqchip=3Don by default for Windows 10 when the PIC is enabled. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 70 +++++++++++++++++++++---------------- 1 file changed, 40 insertions(+), 30 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index a3e91ca533..4810b6387d 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "hw/core/boards.h" #include "hw/intc/ioapic.h" +#include "hw/i386/x86.h" #include "hw/i386/apic_internal.h" #include "qemu/error-report.h" #include "qapi/error.h" @@ -2362,6 +2363,13 @@ int whpx_accel_init(AccelState *as, MachineState *ms) 0x8000000A, 0x80000021, 0x80000022, 0xC0000000, 0xC0000001}; UINT32 cpuidExitList_legacy_os[] =3D {1, 0x40000000, 0x40000001, 0x400= 00010}; =20 + X86MachineState *x86ms =3D X86_MACHINE(ms); + bool pic_enabled =3D false; + + if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { + pic_enabled =3D true; + } + whpx =3D &whpx_global; =20 if (!init_whp_dispatch()) { @@ -2433,6 +2441,35 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 + /* Enable supported performance monitoring capabilities */ + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodeProcessorPerfmonFeatures, &perfmon_features, + sizeof(WHV_PROCESSOR_PERFMON_FEATURES), &whpx_cap_size); + /* + * Relying on this is a crutch to maintain Windows 10 support. + * + * WHvCapabilityCodeProcessorPerfmonFeatures and + * WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks + * are implemented starting from Windows Server 2022 (build 20348). + */ + if (FAILED(hr)) { + warn_report("WHPX: Failed to get performance " + "monitoring features, hr=3D%08lx", hr); + is_modern_os =3D false; + } else { + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeProcessorPerfmonFeatures, + &perfmon_features, + sizeof(WHV_PROCESSOR_PERFMON_FEATURES)); + if (FAILED(hr)) { + error_report("WHPX: Failed to set performance " + "monitoring features, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + } + /* * Error out if WHP doesn't support apic emulation and user is requiri= ng * it. @@ -2445,8 +2482,9 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 - if (whpx->kernel_irqchip_allowed && features.LocalApicEmulation && - whp_dispatch.WHvSetVirtualProcessorInterruptControllerState2) { + if (whpx->kernel_irqchip_allowed && !(whpx_is_legacy_os() && pic_enabl= ed + && !whpx->kernel_irqchip_required) && features.LocalApicEmulation + && whp_dispatch.WHvSetVirtualProcessorInterruptControllerState2) { WHV_X64_LOCAL_APIC_EMULATION_MODE mode =3D WHvX64LocalApicEmulationModeX2Apic; hr =3D whp_dispatch.WHvSetPartitionProperty( @@ -2505,34 +2543,6 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 - /* Enable supported performance monitoring capabilities */ - hr =3D whp_dispatch.WHvGetCapability( - WHvCapabilityCodeProcessorPerfmonFeatures, &perfmon_features, - sizeof(WHV_PROCESSOR_PERFMON_FEATURES), &whpx_cap_size); - /* - * Relying on this is a crutch to maintain Windows 10 support. - * - * WHvCapabilityCodeProcessorPerfmonFeatures and - * WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks - * are implemented starting from Windows Server 2022 (build 20348). - */ - if (FAILED(hr)) { - warn_report("WHPX: Failed to get performance " - "monitoring features, hr=3D%08lx", hr); - is_modern_os =3D false; - } else { - hr =3D whp_dispatch.WHvSetPartitionProperty( - whpx->partition, - WHvPartitionPropertyCodeProcessorPerfmonFeatures, - &perfmon_features, - sizeof(WHV_PROCESSOR_PERFMON_FEATURES)); - if (FAILED(hr)) { - error_report("WHPX: Failed to set performance " - "monitoring features, hr=3D%08lx", hr); - ret =3D -EINVAL; - goto error; - } - } =20 /* Enable synthetic processor features */ WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS synthetic_features; --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1775276527; cv=none; d=zohomail.com; s=zohoarc; b=mPZeb4RdCuELm3B0dpXPWfqduYWD3Gcq6rXkE5LL+sdu/IF5SoeScH3SVHS3hIOD0IXRArJOk64H9YjJYW4MgzMQwBMx+bgShuHm/aSuY9v9qqAdWyNzlj5LA+qWtz2VL8g4mryp3KMZrLhMXMhSQNRau9qMx+V3sLe40hQjz7o= ARC-Message-Signature: i=1; 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t=1775276436; x=1777868436; bh=XF3c7fudpu0e0TEiY2lChefEkznSH2lR6kP+JtXWkz4=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=U/tfDV2eVg4QZOVhxwvPEOKT4EsbDAxLDg5pg91SNf+1G9knwo057DuRM7alN3mfQXNqztJJJn6zpOqWRJHFZ/sDlchNDDqyU1Q0Y41GVI2ucyS/9SPOk2mSLsDA9a4L9mVkmj7nDn1k/jtU5xDfiGA9ZM5gAy/AYqGONcwpyJlVM9o83/spHJbqWF0tZHjbbq5Btquw1l9I684KNv/8naKsoT3XAZn51yDuUqPf99rszGuIr1Duefm37dEjvYO7qoDB0fcvz7qKsABl5lBPnvVvJO7DsgXLNQVu9uAU70PtcaOBJW6MVrbGnmfM3L7w3JAIO77sGmPOvf0xF8QpNA== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: Wei Liu , Roman Bolshakov , Pedro Barbuda , Mohamed Mediouni , Phil Dennis-Jordan , Paolo Bonzini , Zhao Liu Subject: [PATCH v6 11/11] whpx: i386: IO port fast path cleanup Date: Sat, 4 Apr 2026 06:20:15 +0200 Message-ID: <20260404042015.86580-12-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260404042015.86580-1-mohamed@unpredictable.fr> References: <20260404042015.86580-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: CC1raVW39lRktLU8yaf4N8kamy5I5ksM X-Authority-Info-Out: v=2.4 cv=J+2nLQnS c=1 sm=1 tr=0 ts=69d09193 cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117 a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Vrzv6M8N8vcM0KmfSJEA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA0MDAzNCBTYWx0ZWRfX6RIPgARou4Ox DPAETOpkCiSEjcMymtQPQO/UvPMUIe7syU4ZumCLYwrRonJPZPDTU0ZD7SrHk+6ip4r+XlHozcR yS54h7x7NDgPDTr3MIlsgbcGzABSi3TOfOfa/G+XmAWi2wAYjuoaAsKe/VUXySao4FM0yj1NJxW uTX3ZyTKW5lkKAo/b1BjDzRWBmS5e5j1F0KdUW8dBRFPt32lK+tb3i0Z8AE5zTuk9a2FFtAYw42 xKnYUAbqMVwRvWAXrfqP5uGUz+3NXmAlSjKL0t5UFrFr2991mi2e1/GV16Y87LhDmd1S5YVht0S FVOakwXxCBYCGmyG9a/2araGw8UKt6A6jyOneJKPpLzR40eGpIL7moHYpNKr3M= X-Proofpoint-GUID: CC1raVW39lRktLU8yaf4N8kamy5I5ksM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-03_07,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 lowpriorityscore=0 spamscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxscore=0 suspectscore=0 clxscore=1030 mlxlogscore=805 phishscore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2604040034 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.4; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775276530247154100 Content-Type: text/plain; charset="utf-8" vmport calls synchronise_state within an I/O port read. Support that properly. What was there before worked because of a side effect of whpx_get_reg synchronising context if cpu->vcpu_dirty. Remove that whpx_get_reg call in whpx_bump_rip too as it's no longer needed now. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 4810b6387d..ac2671745f 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -861,7 +861,6 @@ static void handle_io(CPUState *env, uint16_t port, voi= d *buffer, static void whpx_bump_rip(CPUState *cpu, WHV_RUN_VP_EXIT_CONTEXT *exit_ctx) { WHV_REGISTER_VALUE reg; - whpx_get_reg(cpu, WHvX64RegisterRip, ®); reg.Reg64 =3D exit_ctx->VpContext.Rip + exit_ctx->VpContext.Instructio= nLength; whpx_set_reg(cpu, WHvX64RegisterRip, reg); } @@ -889,13 +888,23 @@ static int whpx_handle_portio(CPUState *cpu, } else { reg.Reg64 =3D (uint64_t)val; } - whpx_bump_rip(cpu, exit_ctx); - whpx_set_reg(cpu, WHvX64RegisterRax, reg); + /* vmport calls cpu_synchronize_state on an I/O port read */ + if (!cpu->vcpu_dirty) { + whpx_bump_rip(cpu, exit_ctx); + whpx_set_reg(cpu, WHvX64RegisterRax, reg); + } else { + env->eip =3D exit_ctx->VpContext.Rip + exit_ctx->VpContext.Ins= tructionLength; + env->regs[R_EAX] =3D reg.Reg64; + } return 0; } else if (!ctx->AccessInfo.StringOp && ctx->AccessInfo.IsWrite) { RAX(env) =3D ctx->Rax; handle_io(cpu, ctx->PortNumber, &RAX(env), 1, ctx->AccessInfo.Acce= ssSize, 1); - whpx_bump_rip(cpu, exit_ctx); + if (!cpu->vcpu_dirty) { + whpx_bump_rip(cpu, exit_ctx); + } else { + env->eip =3D exit_ctx->VpContext.Rip + exit_ctx->VpContext.Ins= tructionLength; + } return 0; } =20 --=20 2.50.1 (Apple Git-155)