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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.78.123; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775226364405158500 Content-Type: text/plain; charset="utf-8" This was really... quite broken. After fixing this, Windows boots with kernel-irqchip=3Doff. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 51 +++++++++---------------------------- 1 file changed, 12 insertions(+), 39 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 3e006496be..db2e85514c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -371,28 +371,6 @@ static int whpx_set_tsc(CPUState *cpu) return 0; } =20 -/* - * The CR8 register in the CPU is mapped to the TPR register of the APIC, - * however, they use a slightly different encoding. Specifically: - * - * APIC.TPR[bits 7:4] =3D CR8[bits 3:0] - * - * This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64 - * and IA-32 Architectures Software Developer's Manual. - * - * The functions below translate the value of CR8 to TPR and vice versa. - */ - -static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr) -{ - return tpr >> 4; -} - -static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) -{ - return cr8 << 4; -} - void whpx_set_registers(CPUState *cpu, WHPXStateLevel level) { struct whpx_state *whpx =3D &whpx_global; @@ -421,7 +399,7 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel l= evel) v86 =3D (env->eflags & VM_MASK); r86 =3D !(env->cr[0] & CR0_PE_MASK); =20 - vcpu->tpr =3D whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_stat= e)); + vcpu->tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state); vcpu->apic_base =3D cpu_get_apic_base(x86_cpu->apic_state); =20 idx =3D 0; @@ -692,17 +670,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel = level) hr); } =20 - if (whpx_irqchip_in_kernel()) { - /* - * Fetch the TPR value from the emulated APIC. It may get overwrit= ten - * below with the value from CR8 returned by - * WHvGetVirtualProcessorRegisters(). - */ - whpx_apic_get(x86_cpu->apic_state); - vcpu->tpr =3D whpx_apic_tpr_to_cr8( - cpu_get_apic_tpr(x86_cpu->apic_state)); - } - idx =3D 0; =20 /* Indexes for first 16 registers match between HV and QEMU definition= s */ @@ -751,7 +718,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) tpr =3D vcxt.values[idx++].Reg64; if (tpr !=3D vcpu->tpr) { vcpu->tpr =3D tpr; - cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr)); + cpu_set_apic_tpr(x86_cpu->apic_state, tpr); } =20 /* 8 Debug Registers - Skipped */ @@ -1605,6 +1572,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) UINT32 reg_count =3D 0; WHV_REGISTER_VALUE reg_values[3]; WHV_REGISTER_NAME reg_names[3]; + int irr =3D apic_get_highest_priority_irr(x86_cpu->apic_state); =20 memset(&new_int, 0, sizeof(new_int)); memset(reg_values, 0, sizeof(reg_values)); @@ -1643,7 +1611,8 @@ static void whpx_vcpu_pre_run(CPUState *cpu) /* Get pending hard interruption or replay one that was overwritten */ if (!whpx_irqchip_in_kernel()) { if (!vcpu->interruption_pending && - vcpu->interruptable && (env->eflags & IF_MASK)) { + vcpu->interruptable && (env->eflags & IF_MASK) + && (irr =3D=3D -1 || vcpu->tpr < irr)) { assert(!new_int.InterruptionPending); if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); @@ -1690,7 +1659,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } =20 /* Sync the TPR to the CR8 if was modified during the intercept */ - tpr =3D whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state)); + tpr =3D cpu_get_apic_tpr(x86_cpu->apic_state); if (tpr !=3D vcpu->tpr) { vcpu->tpr =3D tpr; reg_values[reg_count].Reg64 =3D tpr; @@ -1702,9 +1671,13 @@ static void whpx_vcpu_pre_run(CPUState *cpu) /* Update the state of the interrupt delivery notification */ if (!vcpu->window_registered && cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { + if (irr =3D=3D -1) { + irr =3D 0; + } reg_values[reg_count].DeliverabilityNotifications =3D (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) { - .InterruptNotification =3D 1 + .InterruptNotification =3D 1, + .InterruptPriority =3D irr }; vcpu->window_registered =3D 1; reg_names[reg_count] =3D WHvX64RegisterDeliverabilityNotifications; @@ -1737,7 +1710,7 @@ static void whpx_vcpu_post_run(CPUState *cpu) if (vcpu->tpr !=3D tpr) { vcpu->tpr =3D tpr; bql_lock(); - cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->t= pr)); + cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr); bql_unlock(); } =20 --=20 2.50.1 (Apple Git-155)