From nobody Sat Apr 11 18:34:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775222147647611.536828689222; Fri, 3 Apr 2026 06:15:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w8eMj-0002qj-Vd; Fri, 03 Apr 2026 09:15:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w8eMi-0002qC-9o for qemu-devel@nongnu.org; Fri, 03 Apr 2026 09:15:12 -0400 Received: from v54.v54282eed.euw1.send.eu.mailgun.net ([185.250.239.4]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1w8eMg-000397-69 for qemu-devel@nongnu.org; Fri, 03 Apr 2026 09:15:12 -0400 Received: from fedora (pub158181109038.dh-hfc.datazug.ch [158.181.109.38]) by 6b35d5fe85243893b0115df7e32ecf0b1954107ecd10c214f43efced52bb359e with SMTP id 69cfbd5ae1e94239b652e484; Fri, 03 Apr 2026 13:15:06 GMT DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=0x65c.net; q=dns/txt; s=email; t=1775222106; x=1775229306; h=Content-Transfer-Encoding: MIME-Version: Message-ID: Date: Subject: Subject: Cc: To: To: From: From: Sender: Sender; bh=TR3ZZO4BI/S5Hcl0BCH8ZcZmu5fK21upHyYovJkP0wc=; b=ZaDCH/a4t+APUA4HL54iMcqZ/qYAu2Lvi4af+Yide9Ng5avR64QQzQ7iMPW5NB0ASuqcxEpRPX5VT9I1tkQMRZ8Tg9aZAXJ5hcq+/GQRlGAO5EEbxtKtN2rWLQ5IMYUON8izzyYTIY/mNKkGY9IJfeeS9Mz23kSWoqQF72fYsQRu+CPXsIzUg3nQE29KEIPwQUZAWFreE0GLI16dX6otUZPEv1Stm8kNmKIcVKP/HrIRzW2BPo3bdkdFFJ2jE5l57WTUUhe7i+wmiijrGWm+7KaFw1SRbDYw+R7QqtUTT5638bNTsYa1TIY5xeEUoqleYy2aSuKePUuf1oRd2llR9g== X-Mailgun-Sid: WyJiNjdhNCIsInFlbXUtZGV2ZWxAbm9uZ251Lm9yZyIsIjU0ZWY0Il0= X-Mailgun-Sending-Ip: 185.250.239.4 From: Alessandro Ratti To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, pbonzini@redhat.com, Alessandro Ratti Subject: [PATCH] target/arm: Move OMAP CP15 register definitions to cpregs-omap.c Date: Fri, 3 Apr 2026 15:14:58 +0200 Message-ID: <20260403131458.446399-1-alessandro@0x65c.net> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.250.239.4; envelope-from=bounce+db73df.54ef4-qemu-devel=nongnu.org@0x65c.net; helo=v54.v54282eed.euw1.send.eu.mailgun.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1775222150266154100 Content-Type: text/plain; charset="utf-8" The OMAP CP15 registers are only relevant to system-mode emulation of OMAP SoCs. Move them out of the monolithic helper.c into a dedicated file, following the pattern of cpregs-pmu.c and cpregs-gcs.c. This reduces the size of helper.c and compiles the OMAP-specific code out of CONFIG_USER_ONLY builds. Suggested-by: Paolo Bonzini Signed-off-by: Alessandro Ratti Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpregs-omap-stub.c | 10 ++++ target/arm/cpregs-omap.c | 88 +++++++++++++++++++++++++++++++++++ target/arm/helper.c | 79 +------------------------------ target/arm/internals.h | 2 + target/arm/meson.build | 2 + 5 files changed, 103 insertions(+), 78 deletions(-) create mode 100644 target/arm/cpregs-omap-stub.c create mode 100644 target/arm/cpregs-omap.c diff --git a/target/arm/cpregs-omap-stub.c b/target/arm/cpregs-omap-stub.c new file mode 100644 index 0000000000..e0fe32632e --- /dev/null +++ b/target/arm/cpregs-omap-stub.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +void define_omap_cp_regs(ARMCPU *cpu) +{ + g_assert_not_reached(); +} diff --git a/target/arm/cpregs-omap.c b/target/arm/cpregs-omap.c new file mode 100644 index 0000000000..5fa6b70150 --- /dev/null +++ b/target/arm/cpregs-omap.c @@ -0,0 +1,88 @@ +/* + * QEMU ARM OMAP CP15 register definitions + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpregs.h" +#include "internals.h" + +static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_ticonfig =3D value & 0xe7; + /* The OS_TYPE bit in this register changes the reported CPUID! */ + env->cp15.c0_cpuid =3D (value & (1 << 5)) ? + ARM_CPUID_TI915T : ARM_CPUID_TI925T; +} + +static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_threadid =3D value & 0xffff; +} + +static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Wait-for-interrupt (deprecated) */ + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); +} + +static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * On OMAP there are registers indicating the max/min index of dcache = lines + * containing a dirty line; cache flush operations have to reset these. + */ + env->cp15.c15_i_max =3D 0x000; + env->cp15.c15_i_min =3D 0xff0; +} + +static const ARMCPRegInfo omap_cp_reginfo[] =3D { + { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_OVERRIDE, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_el[1]), + .resetvalue =3D 0, }, + { .name =3D "", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 0, .opc= 2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + { .name =3D "TICONFIG", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ticonfig), .resetval= ue =3D 0, + .writefn =3D omap_ticonfig_write }, + { .name =3D "IMAX", .cp =3D 15, .crn =3D 15, .crm =3D 2, .opc1 =3D 0, = .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = =3D 0, }, + { .name =3D "IMIN", .cp =3D 15, .crn =3D 15, .crm =3D 3, .opc1 =3D 0, = .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0xff0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_min) }, + { .name =3D "THREADID", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_threadid), .resetval= ue =3D 0, + .writefn =3D omap_threadid_write }, + { .name =3D "TI925T_STATUS", .cp =3D 15, .crn =3D 15, + .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, + .type =3D ARM_CP_NO_RAW, + .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, + /* + * TODO: Peripheral port remap register: + * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller + * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), + * when MMU is off. + */ + { .name =3D "OMAP_CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, + .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, + .type =3D ARM_CP_OVERRIDE | ARM_CP_NO_RAW, + .writefn =3D omap_cachemaint_write }, + { .name =3D "C9", .cp =3D 15, .crn =3D 9, + .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, + .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, +}; + +void define_omap_cp_regs(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, omap_cp_reginfo); +} diff --git a/target/arm/helper.c b/target/arm/helper.c index 7389f2988c..3ac88078aa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2900,83 +2900,6 @@ static const ARMCPRegInfo ttbcr2_reginfo =3D { }, }; =20 -static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_ticonfig =3D value & 0xe7; - /* The OS_TYPE bit in this register changes the reported CPUID! */ - env->cp15.c0_cpuid =3D (value & (1 << 5)) ? - ARM_CPUID_TI915T : ARM_CPUID_TI925T; -} - -static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_threadid =3D value & 0xffff; -} - -static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ -#ifdef CONFIG_USER_ONLY - g_assert_not_reached(); -#else - /* Wait-for-interrupt (deprecated) */ - cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); -#endif -} - -static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * On OMAP there are registers indicating the max/min index of dcache = lines - * containing a dirty line; cache flush operations have to reset these. - */ - env->cp15.c15_i_max =3D 0x000; - env->cp15.c15_i_min =3D 0xff0; -} - -static const ARMCPRegInfo omap_cp_reginfo[] =3D { - { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_OVERRIDE, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_el[1]), - .resetvalue =3D 0, }, - { .name =3D "", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 0, .opc= 2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - { .name =3D "TICONFIG", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ticonfig), .resetval= ue =3D 0, - .writefn =3D omap_ticonfig_write }, - { .name =3D "IMAX", .cp =3D 15, .crn =3D 15, .crm =3D 2, .opc1 =3D 0, = .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = =3D 0, }, - { .name =3D "IMIN", .cp =3D 15, .crn =3D 15, .crm =3D 3, .opc1 =3D 0, = .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0xff0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_min) }, - { .name =3D "THREADID", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_threadid), .resetval= ue =3D 0, - .writefn =3D omap_threadid_write }, - { .name =3D "TI925T_STATUS", .cp =3D 15, .crn =3D 15, - .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, - .type =3D ARM_CP_NO_RAW, - .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, - /* - * TODO: Peripheral port remap register: - * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller - * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), - * when MMU is off. - */ - { .name =3D "OMAP_CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, - .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, - .type =3D ARM_CP_OVERRIDE | ARM_CP_NO_RAW, - .writefn =3D omap_cachemaint_write }, - { .name =3D "C9", .cp =3D 15, .crn =3D 9, - .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, - .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, -}; - static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { /* * RAZ/WI the whole crn=3D15 space, when we don't have a more specific @@ -7043,7 +6966,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_OMAPCP)) { - define_arm_cp_regs(cpu, omap_cp_reginfo); + define_omap_cp_regs(cpu); } if (arm_feature(env, ARM_FEATURE_STRONGARM)) { define_arm_cp_regs(cpu, strongarm_cp_reginfo); diff --git a/target/arm/internals.h b/target/arm/internals.h index 8ec2750847..73fcb84a84 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1796,6 +1796,8 @@ void define_at_insn_regs(ARMCPU *cpu); void define_pm_cpregs(ARMCPU *cpu); /* Add the cpreg definitions for GCS cpregs */ void define_gcs_cpregs(ARMCPU *cpu); +/* Add the cpreg definitions for OMAP CP15 regs */ +void define_omap_cp_regs(ARMCPU *cpu); =20 /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) diff --git a/target/arm/meson.build b/target/arm/meson.build index 6e0e504a40..192ac7c31e 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -33,6 +33,7 @@ arm_user_ss.add(files( 'helper.c', 'vfp_fpscr.c', 'el2-stubs.c', + 'cpregs-omap-stub.c', )) arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('common-semi-target.c')) @@ -48,6 +49,7 @@ arm_common_system_ss.add(files( 'arm-powerctl.c', 'cortex-regs.c', 'cpregs-gcs.c', + 'cpregs-omap.c', 'cpregs-pmu.c', 'cpu-irq.c', 'debug_helper.c', --=20 2.53.0