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a="76140629" X-IronPort-AV: E=Sophos;i="6.23,157,1770624000"; d="scan'208";a="76140629" X-CSE-ConnectionGUID: bwyxdQLBQG6Dxh+UeAMqWQ== X-CSE-MsgGUID: f6DIFUBOSGy6NBYKZtXNMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,157,1770624000"; d="scan'208";a="223884882" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan , Clement Mathieu--Drif Subject: [PATCH v3 06/14] intel_iommu: Export some functions Date: Thu, 2 Apr 2026 23:55:30 -0400 Message-ID: <20260403035541.18355-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260403035541.18355-1-zhenzhong.duan@intel.com> References: <20260403035541.18355-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.19; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.542, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1775188658477154100 Content-Type: text/plain; charset="utf-8" Export some functions for accel code usages. Inline functions and MACROs are moved to internal header files. Then accel code in following patches could access them. Signed-off-by: Zhenzhong Duan Reviewed-by: Clement Mathieu--Drif Reviewed-by: Yi Liu Tested-by: Xudong Hao --- hw/i386/intel_iommu_internal.h | 31 +++++++++++++++++++++++++ hw/i386/intel_iommu.c | 42 ++++++++-------------------------- 2 files changed, 40 insertions(+), 33 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index db4f186a3e..c7e107fe87 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -620,6 +620,12 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL =20 +/* context entry operations */ +#define VTD_CE_GET_PASID_DIR_TABLE(ce) \ + ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) +#define VTD_CE_GET_PRE(ce) \ + ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE) + typedef struct VTDPASIDCacheInfo { uint8_t type; uint16_t did; @@ -746,4 +752,29 @@ static inline bool vtd_pe_pgtt_is_fst(VTDPASIDEntry *p= e) { return (VTD_SM_PASID_ENTRY_PGTT(pe) =3D=3D VTD_SM_PASID_ENTRY_FST); } + +static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) +{ + return pdire->val & 1; +} + +static inline bool vtd_pe_present(VTDPASIDEntry *pe) +{ + return pe->val[0] & VTD_PASID_ENTRY_P; +} + +static inline int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry= *p2) +{ + return memcmp(p1, p2, sizeof(*p1)); +} + +int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasi= d, + VTDPASIDDirEntry *pdire); +int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, + dma_addr_t addr, VTDPASIDEntry *pe); +int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, + uint8_t devfn, VTDContextEntry *ce); +int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, + VTDPASIDEntry *pe, uint32_t pasid); +VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid); #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 635e7ee145..aa67c89e73 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -42,12 +42,6 @@ #include "migration/vmstate.h" #include "trace.h" =20 -/* context entry operations */ -#define VTD_CE_GET_PASID_DIR_TABLE(ce) \ - ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) -#define VTD_CE_GET_PRE(ce) \ - ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE) - /* * Paging mode for first-stage translation (VTD spec Figure 9-6) * 00: 4-level paging, 01: 5-level paging @@ -831,18 +825,12 @@ static inline bool vtd_pe_type_check(IntelIOMMUState = *s, VTDPASIDEntry *pe) } } =20 -static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) -{ - return pdire->val & 1; -} - /** * Caller of this function should check present bit if wants * to use pdir entry for further usage except for fpd bit check. */ -static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, - uint32_t pasid, - VTDPASIDDirEntry *pdire) +int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasi= d, + VTDPASIDDirEntry *pdire) { uint32_t index; dma_addr_t addr, entry_size; @@ -860,15 +848,8 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pa= sid_dir_base, return 0; } =20 -static inline bool vtd_pe_present(VTDPASIDEntry *pe) -{ - return pe->val[0] & VTD_PASID_ENTRY_P; -} - -static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, - uint32_t pasid, - dma_addr_t addr, - VTDPASIDEntry *pe) +int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, + dma_addr_t addr, VTDPASIDEntry *pe) { uint8_t pgtt; uint32_t index; @@ -954,8 +935,8 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, return 0; } =20 -static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, - VTDPASIDEntry *pe, uint32_t pasid) +int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, + VTDPASIDEntry *pe, uint32_t pasid) { dma_addr_t pasid_dir_base; =20 @@ -1526,8 +1507,8 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, V= TDContextEntry *ce) } =20 /* Map a device to its corresponding domain (context-entry) */ -static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, - uint8_t devfn, VTDContextEntry *ce) +int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, + uint8_t devfn, VTDContextEntry *ce) { VTDRootEntry re; int ret_fr; @@ -1909,7 +1890,7 @@ static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(I= ntelIOMMUState *s, vtd_find_as_by_sid_and_pasid, &key); } =20 -static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) +VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) { return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID); } @@ -3133,11 +3114,6 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddre= ssSpace *vtd_as, return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid); } =20 -static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) -{ - return memcmp(p1, p2, sizeof(*p1)); -} - /* Update or invalidate pasid cache based on the pasid entry in guest memo= ry. */ static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value, gpointer user_data) --=20 2.47.3