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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.67.85; envelope-from=mohamed@unpredictable.fr; helo=outbound.pv.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775158352272158500 Content-Type: text/plain; charset="utf-8" Instead of just the command number, include the instruction name to make de= bugging easier. Signed-off-by: Mohamed Mediouni --- target/i386/emulate/x86_emu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c index 55b1a68eb6..c2da1a133f 100644 --- a/target/i386/emulate/x86_emu.c +++ b/target/i386/emulate/x86_emu.c @@ -1399,8 +1399,8 @@ static void init_cmd_handler(void) bool exec_instruction(CPUX86State *env, struct x86_decode *ins) { if (!_cmd_handler[ins->cmd].handler) { - printf("Unimplemented handler (" TARGET_FMT_lx ") for %d (%x %x)\n= ", - env->eip, + printf("Unimplemented handler (" TARGET_FMT_lx ") for %s - %d (%x = %x)\n", + env->eip, decode_cmd_to_string(ins->cmd), ins->cmd, ins->opcode[0], ins->opcode_len > 1 ? ins->opcode[1] : 0); env->eip +=3D ins->len; --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:34:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 02 Apr 2026 19:31:15 +0000 (UTC) Received: from localhost.localdomain (unknown [17.56.9.36]) by p00-icloudmta-asmtp-us-west-1a-20-percent-1 (Postfix) with ESMTPSA id B19AF1800124; Thu, 02 Apr 2026 19:31:12 +0000 (UTC) Dkim-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr; s=sig1; t=1775158277; x=1777750277; bh=NEY/B0hsRoX1RMH5wKACHOnKD7aE0mtEoOch9NbWUDg=; h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme; b=F2BMg7NkPRrlIR5vi04MfngEOLnaqV+RFpuga6LauuQY2i5hd50V83Lb/YH57UOr60wgLO99xaCSNqe7BBb16hBQInuRVJfYn5YZvYtq89/M9v/QBGdpIUTpid0Rgq2GS2OUoix35VpEw29UTpwwFK7k1lU2k1h+X919VYB90qg/HoXlYusbRqONY5DQ21+6JmJwZEsUlfsOIdxf1QQEBEAiS6zyQHZVjGgaoSHXGJOG1zLMCLqeX3XVMqRJeNGJs9ln8CuCpmDUBargszn53sjwtEG31BhhqeCtHMT27W/UkQSDLgkMYYC49Obx5W6yZhSxiPxwEPWyjDthvvGTmQ== mail-alias-created-date: 1752046281608 From: Mohamed Mediouni To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Mohamed Mediouni , Paolo Bonzini , Peter Maydell , Zhao Liu , Roman Bolshakov , Wei Liu , Pedro Barbuda , Phil Dennis-Jordan Subject: [PATCH v2 2/6] whpx: i386: x2apic emulation Date: Thu, 2 Apr 2026 21:31:00 +0200 Message-ID: <20260402193104.56331-3-mohamed@unpredictable.fr> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260402193104.56331-1-mohamed@unpredictable.fr> References: <20260402193104.56331-1-mohamed@unpredictable.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: RgYG4vHqszTxHHBn0PV1uAZsfdAkAk0l X-Proofpoint-ORIG-GUID: RgYG4vHqszTxHHBn0PV1uAZsfdAkAk0l X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAyMDE3NSBTYWx0ZWRfXztC5q96+XBVB QiEKO2+xALQHGQyHrBJzhduPrEqXRSWNhyurA4NWXXHiNDZKSVDn/+Rj3E41Ezd1wKZnTg6v8u8 f0fJgq6BikCPJ8bxfx4BIEOMUi/xPATUMZxuUjD051Tr6PSQpByfaXWzQA+l3r0J89Y/z5Nqh9k D5Suml9LpAy4ThYKfQg/Kj6LKj/Epd/cxaclMUCjgzdHfqt7liY+eRIu7oLGCRG+ftyzUQG42X/ UyWDb4+OPRB8unVKp2KvniTHFN/D2xj57yaxKSUVaYvn8pwQDTCO8oybUuUi7FeXSfUlcUv3K0Y LYiuMMZZ3wx1XYheMZniEYlxDYtP2Y/ECtIZuBaufbomlRayG1PYMENJS4CTCg= X-Authority-Info-Out: v=2.4 cv=ULbQ3Sfy c=1 sm=1 tr=0 ts=69cec404 cx=c_apl:c_pps:t_out a=azHRBMxVc17uSn+fyuI/eg==:117 a=azHRBMxVc17uSn+fyuI/eg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=nj4AhdDZwDx412jv8JQA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-02_03,2026-04-02_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1030 adultscore=0 phishscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 mlxlogscore=688 spamscore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2604020175 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.67.65; envelope-from=mohamed@unpredictable.fr; helo=outbound.pv.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775158322012154100 Content-Type: text/plain; charset="utf-8" Add x2apic emulation to WHPX for the kernel-irqchip=3Doff case. Unfortunately, it looks like there isn't a workaround available for proper behavior of PIC interrupts when kernel-irqchip=3Don for Windows 10. The OS is out of support outside of extended security updates so this will not be addressed. On Windows 11, x2apic will be enabled straight away because Linux enables it even without an IOMMU when using Hyper-V. For Windows 10, you need: -device intel-iommu,intremap=3Don,eim=3Don The performance impact is worthwhile for multicore guests. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 134 +++++++++++++++++++++++++++++++++++- 1 file changed, 133 insertions(+), 1 deletion(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index e56ae2b343..4127440c0c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -1082,6 +1082,8 @@ HRESULT whpx_set_exception_exit_bitmap(UINT64 excepti= ons) /* Register for MSR and CPUID exits */ memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); prop.ExtendedVmExits.X64MsrExit =3D 1; + prop.ExtendedVmExits.X64CpuidExit =3D 1; + if (exceptions !=3D 0) { prop.ExtendedVmExits.ExceptionExit =3D 1; } @@ -1898,6 +1900,18 @@ int whpx_vcpu_run(CPUState *cpu) WHV_REGISTER_NAME reg_names[3]; UINT32 reg_count; bool is_known_msr =3D 0;=20 + uint64_t val; + + if (vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) { + val =3D ((uint32_t)vcpu->exit_ctx.MsrAccess.Rax) | + ((uint64_t)(vcpu->exit_ctx.MsrAccess.Rdx) << 32); + } else { + /* + * Workaround for [-Werror=3Dmaybe-uninitialized] + * with GCC. Not needed with Clang. + */ + val =3D 0; + } =20 reg_names[0] =3D WHvX64RegisterRip; reg_names[1] =3D WHvX64RegisterRax; @@ -1911,7 +1925,47 @@ int whpx_vcpu_run(CPUState *cpu) && !vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite && !whpx_irqchip_in_kernel()) { is_known_msr =3D 1; - reg_values[1].Reg32 =3D (uint32_t)X86_CPU(cpu)->env.apic_b= us_freq; + val =3D X86_CPU(cpu)->env.apic_bus_freq; + } + + if (!whpx_irqchip_in_kernel() && + vcpu->exit_ctx.MsrAccess.MsrNumber =3D=3D MSR_IA32_APICBAS= E) { + is_known_msr =3D 1; + if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) { + /* Read path unreachable on Hyper-V */ + abort(); + } else { + WHV_REGISTER_VALUE reg =3D {.Reg64 =3D val}; + int msr_ret =3D cpu_set_apic_base(X86_CPU(cpu)->apic_s= tate, val); + if (msr_ret < 0) { + x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0= D_GPF, 0); + } + whpx_set_reg(cpu, WHvX64RegisterApicBase, reg); + } + } + + if (!whpx_irqchip_in_kernel() && + vcpu->exit_ctx.MsrAccess.MsrNumber >=3D MSR_APIC_START && + vcpu->exit_ctx.MsrAccess.MsrNumber <=3D MSR_APIC_END) { + int index =3D vcpu->exit_ctx.MsrAccess.MsrNumber - MSR_API= C_START; + int msr_ret; + is_known_msr =3D 1; + if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) { + bql_lock(); + msr_ret =3D apic_msr_read(X86_CPU(cpu)->apic_state, in= dex, &val); + bql_unlock(); + reg_values[1].Reg64 =3D val; + if (msr_ret < 0) { + x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0= D_GPF, 0); + } + } else { + bql_lock(); + msr_ret =3D apic_msr_write(X86_CPU(cpu)->apic_state, i= ndex, val); + bql_unlock(); + if (msr_ret < 0) { + x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0= D_GPF, 0); + } + } } /* * For all unsupported MSR access we: @@ -1921,6 +1975,11 @@ int whpx_vcpu_run(CPUState *cpu) reg_count =3D vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite ? 1 : 3; =20 + if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) { + reg_values[1].Reg32 =3D (uint32_t)val; + reg_values[2].Reg32 =3D (uint32_t)(val >> 32); + } + if (!is_known_msr) { trace_whpx_unsupported_msr_access(vcpu->exit_ctx.MsrAccess= .MsrNumber, vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite); @@ -1939,6 +1998,47 @@ int whpx_vcpu_run(CPUState *cpu) ret =3D 0; break; } + case WHvRunVpExitReasonX64Cpuid: { + WHV_REGISTER_VALUE reg_values[5] =3D {0}; + WHV_REGISTER_NAME reg_names[5]; + UINT32 reg_count =3D 5; + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + + reg_names[0] =3D WHvX64RegisterRip; + reg_names[1] =3D WHvX64RegisterRax; + reg_names[2] =3D WHvX64RegisterRcx; + reg_names[3] =3D WHvX64RegisterRdx; + reg_names[4] =3D WHvX64RegisterRbx; + + reg_values[0].Reg64 =3D + vcpu->exit_ctx.VpContext.Rip + + vcpu->exit_ctx.VpContext.InstructionLength; + + reg_values[1].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRax; + reg_values[2].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRcx; + reg_values[3].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRdx; + reg_values[4].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRbx; + + if (vcpu->exit_ctx.CpuidAccess.Rax =3D=3D 1) { + if (cpu_has_x2apic_feature(env)) { + reg_values[2].Reg64 |=3D CPUID_EXT_X2APIC; + } + } + + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( + whpx->partition, + cpu->cpu_index, + reg_names, reg_count, + reg_values); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set CpuidAccess state " + " registers, hr=3D%08lx", hr); + } + ret =3D 0; + break; + } case WHvRunVpExitReasonException: whpx_get_registers(cpu, WHPX_LEVEL_FULL_STATE); =20 @@ -2136,6 +2236,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) WHV_PROCESSOR_FEATURES_BANKS processor_features; WHV_PROCESSOR_PERFMON_FEATURES perfmon_features; bool is_legacy_os =3D false; + UINT32 cpuidExitList[] =3D {1}; =20 whpx =3D &whpx_global; =20 @@ -2354,6 +2455,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) /* Register for MSR and CPUID exits */ memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); prop.ExtendedVmExits.X64MsrExit =3D 1; + prop.ExtendedVmExits.X64CpuidExit =3D 1; =20 hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, @@ -2366,6 +2468,36 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 + memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); + prop.X64MsrExitBitmap.UnhandledMsrs =3D 1; + if (!whpx_irqchip_in_kernel()) { + prop.X64MsrExitBitmap.ApicBaseMsrWrite =3D 1; + } + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeX64MsrExitBitmap, + &prop, + sizeof(WHV_PARTITION_PROPERTY)); + if (FAILED(hr)) { + error_report("WHPX: Failed to set MSR exit bitmap, hr=3D%08lx", hr= ); + ret =3D -EINVAL; + goto error; + } + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeCpuidExitList, + cpuidExitList, + RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set partition CpuidExitList hr=3D%08= lx", + hr); + ret =3D -EINVAL; + goto error; + } + /* * We do not want to intercept any exceptions from the guest, * until we actually start debugging with gdb. --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:34:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.67.15; envelope-from=mohamed@unpredictable.fr; helo=outbound.pv.icloud.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775158366221154100 Content-Type: text/plain; charset="utf-8" Windows 10 doesn't have the API for this, so using this only for Windows 11. Signed-off-by: Mohamed Mediouni --- include/system/whpx-internal.h | 3 ++ target/i386/cpu.c | 25 ++++++++++++++ target/i386/whpx/whpx-all.c | 63 +++++++++++++++++++++++++++++++++- target/i386/whpx/whpx-i386.h | 4 +++ 4 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 target/i386/whpx/whpx-i386.h diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 8482901f71..480d05fdca 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -89,6 +89,9 @@ void whpx_apic_get(APICCommonState *s); UINT32 StateSize)) \ X(HRESULT, WHvResetPartition, \ (WHV_PARTITION_HANDLE Partition)) \ + X(HRESULT, WHvGetVirtualProcessorCpuidOutput, \ + (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, UINT32 Eax, \ + UINT32 Ecx, WHV_CPUID_OUTPUT* CpuidOutput)) =20 #define WHP_DEFINE_TYPE(return_type, function_name, signature) \ typedef return_type (WINAPI *function_name ## _t) signature; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c6fd1dc00e..0000093fa3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -26,6 +26,8 @@ #include "tcg/helper-tcg.h" #include "exec/translation-block.h" #include "system/hvf.h" +#include "system/whpx.h" +#include "whpx/whpx-i386.h" #include "hvf/hvf-i386.h" #include "kvm/kvm_i386.h" #include "kvm/tdx.h" @@ -8087,6 +8089,17 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w) r =3D hvf_get_supported_cpuid(wi->cpuid.eax, wi->cpuid.ecx, wi->cpuid.reg); + } else if (whpx_enabled()) { + if (wi->type !=3D CPUID_FEATURE_WORD) { + return 0; + } + if (whpx_is_legacy_os()) { + r =3D wi->tcg_features; + } else { + r =3D whpx_get_supported_cpuid(wi->cpuid.eax, + wi->cpuid.ecx, + wi->cpuid.reg); + } } else if (tcg_enabled() || qtest_enabled()) { r =3D wi->tcg_features; } else { @@ -8168,6 +8181,18 @@ static void x86_cpu_get_supported_cpuid(uint32_t fun= c, uint32_t index, *ebx =3D hvf_get_supported_cpuid(func, index, R_EBX); *ecx =3D hvf_get_supported_cpuid(func, index, R_ECX); *edx =3D hvf_get_supported_cpuid(func, index, R_EDX); + } else if (whpx_enabled()) { + if (whpx_is_legacy_os()) { + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + } else { + *eax =3D whpx_get_supported_cpuid(func, index, R_EAX); + *ebx =3D whpx_get_supported_cpuid(func, index, R_EBX); + *ecx =3D whpx_get_supported_cpuid(func, index, R_ECX); + *edx =3D whpx_get_supported_cpuid(func, index, R_EDX); + } } else { *eax =3D 0; *ebx =3D 0; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 4127440c0c..db8855cbea 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -36,6 +36,7 @@ #include "system/whpx-accel-ops.h" #include "system/whpx-all.h" #include "system/whpx-common.h" +#include "whpx-i386.h" =20 #include "emulate/x86_decode.h" #include "emulate/x86_emu.h" @@ -49,6 +50,8 @@ /* for kernel-irqchip=3Doff */ #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 =20 +bool is_legacy_os =3D false; + static const WHV_REGISTER_NAME whpx_register_names[] =3D { =20 /* X64 General purpose registers */ @@ -1062,6 +1065,65 @@ static void whpx_init_emu(void) init_emu(&whpx_x86_emul_ops); } =20 +bool whpx_is_legacy_os(void)=20 +{ + return is_legacy_os; +} + +uint32_t whpx_get_supported_cpuid(uint32_t func, uint32_t idx, int reg) +{ + WHV_CPUID_OUTPUT output; + uint32_t eax, ebx, ecx, edx; + uint32_t cpu_index =3D 0; + bool temp_cpu =3D true; + HRESULT hr; + + hr =3D whp_dispatch.WHvCreateVirtualProcessor( + whpx_global.partition, cpu_index, 0); + + /* This means that the CPU already exists... */ + if (FAILED(hr)) { + temp_cpu =3D false; + } + + hr =3D whp_dispatch.WHvGetVirtualProcessorCpuidOutput(whpx_global.part= ition, + cpu_index, func, idx, &output); + =20 + if (FAILED(hr)) { + abort(); + } + + if (temp_cpu) { + hr =3D whp_dispatch.WHvDeleteVirtualProcessor(whpx_global.partitio= n, cpu_index); + if (FAILED(hr)) { + abort(); + } + } + + eax =3D output.Eax; + ebx =3D output.Ebx; + ecx =3D output.Ecx; + edx =3D output.Edx; + + /* We can emulate X2APIC even for the kernel-irqchip=3Doff case */ + if (func =3D=3D 1) { + ecx |=3D CPUID_EXT_X2APIC; + } + + switch (reg) { + case R_EAX: + return eax; + case R_EBX: + return ebx; + case R_ECX: + return ecx; + case R_EDX: + return edx; + default: + return 0; + } +} + /* * Controls whether we should intercept various exceptions on the guest, * namely breakpoint/single-step events. @@ -2235,7 +2297,6 @@ int whpx_accel_init(AccelState *as, MachineState *ms) WHV_CAPABILITY_FEATURES features =3D {0}; WHV_PROCESSOR_FEATURES_BANKS processor_features; WHV_PROCESSOR_PERFMON_FEATURES perfmon_features; - bool is_legacy_os =3D false; UINT32 cpuidExitList[] =3D {1}; =20 whpx =3D &whpx_global; diff --git a/target/i386/whpx/whpx-i386.h b/target/i386/whpx/whpx-i386.h new file mode 100644 index 0000000000..6db9a75d39 --- /dev/null +++ b/target/i386/whpx/whpx-i386.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +uint32_t whpx_get_supported_cpuid(uint32_t func, uint32_t idx, int reg); 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charset="utf-8" AccessHypercallRegs was present twice so clean that up. Remove TbFlushHypercalls (and its extended Gva range sub-feature) from the user-mode LAPIC case as it behaves oddly there. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index db8855cbea..3cd83b506b 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2483,10 +2483,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) synthetic_features.Bank0.AccessPartitionReferenceTsc =3D 1; synthetic_features.Bank0.AccessHypercallRegs =3D 1; synthetic_features.Bank0.AccessFrequencyRegs =3D 1; - synthetic_features.Bank0.EnableExtendedGvaRangesForFlushVirtualAddress= List =3D 1; synthetic_features.Bank0.AccessVpIndex =3D 1; - synthetic_features.Bank0.AccessHypercallRegs =3D 1; - synthetic_features.Bank0.TbFlushHypercalls =3D 1; =20 if (whpx_irqchip_in_kernel()) { synthetic_features.Bank0.AccessSynicRegs =3D 1; @@ -2494,6 +2491,12 @@ int whpx_accel_init(AccelState *as, MachineState *ms) synthetic_features.Bank0.AccessIntrCtrlRegs =3D 1; synthetic_features.Bank0.SyntheticClusterIpi =3D 1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.64.145; envelope-from=mohamed@unpredictable.fr; helo=outbound.pv.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775158352271158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 3cd83b506b..b8f53ca532 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2275,11 +2275,18 @@ error: return ret; } =20 +static PropValue whpx_default_props[] =3D { + { "x2apic", "on" }, + { NULL, NULL }, +}; + + void whpx_cpu_instance_init(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 host_cpu_instance_init(cpu); + x86_cpu_apply_props(cpu, whpx_default_props); } =20 /* --=20 2.50.1 (Apple Git-155) From nobody Sat Apr 11 18:34:09 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=unpredictable.fr ARC-Seal: i=1; a=rsa-sha256; t=1775158355; cv=none; d=zohomail.com; s=zohoarc; b=AnYLR1raDDZ5RdwaBUou7uh5ehApKpEl3eI4WPVGfXsS1k4PJOLBl5kDvoRmvlEdNlZ/cQr/1Dl7+BAt1emCqKa1dXXaGdcyyR0Q1sIM0vQGjRZ8sYCFHcVc8bRAfHT6vuCrwjcP0JXMaeYGvFMCqXXWjXwrtiKpRXu66HPh7pI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775158355; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.64.144; envelope-from=mohamed@unpredictable.fr; helo=outbound.pv.icloud.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1775158360396154100 Content-Type: text/plain; charset="utf-8" Was removed in 2c08624 but it's still useful for Windows 10 so reintroduce it there. And this time, actually make it work by reporting the hypervisor bit in CPUID. Also pretend to be KVM, with the only capability reported being X2APIC support. Although looks like Linux doesn't use that vmware leaf... Signed-off-by: Mohamed Mediouni --- accel/whpx/whpx-common.c | 2 + include/system/whpx-internal.h | 1 + target/arm/whpx/whpx-all.c | 1 + target/i386/whpx/whpx-all.c | 68 ++++++++++++++++++++++++++++++---- 4 files changed, 64 insertions(+), 8 deletions(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index b813a5d9d2..59be996aef 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -550,6 +550,8 @@ static void whpx_accel_instance_init(Object *obj) =20 whpx->hyperv_enlightenments_allowed =3D true; whpx->hyperv_enlightenments_required =3D false; + /* Value determined at whpx_accel_init */ + whpx->hyperv_enlightenments_enabled =3D false; } =20 static const TypeInfo whpx_accel_type =3D { diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 480d05fdca..576587ec3b 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -45,6 +45,7 @@ struct whpx_state { =20 bool hyperv_enlightenments_allowed; bool hyperv_enlightenments_required; + bool hyperv_enlightenments_enabled; =20 }; =20 diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index bbf0f6be96..4019a513aa 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -968,6 +968,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) * as they're not needed for performance. */ if (whpx->hyperv_enlightenments_required) { + whpx->hyperv_enlightenments_enabled =3D true; hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks, diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index b8f53ca532..b62377cb41 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2077,14 +2077,47 @@ int whpx_vcpu_run(CPUState *cpu) vcpu->exit_ctx.VpContext.Rip + vcpu->exit_ctx.VpContext.InstructionLength; =20 - reg_values[1].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRax; - reg_values[2].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRcx; - reg_values[3].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRdx; - reg_values[4].Reg64 =3D vcpu->exit_ctx.CpuidAccess.DefaultResu= ltRbx; - - if (vcpu->exit_ctx.CpuidAccess.Rax =3D=3D 1) { - if (cpu_has_x2apic_feature(env)) { - reg_values[2].Reg64 |=3D CPUID_EXT_X2APIC; + if (whpx_is_legacy_os()) { + reg_values[1].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Default= ResultRax; + reg_values[2].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Default= ResultRcx; + reg_values[3].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Default= ResultRdx; + reg_values[4].Reg64 =3D vcpu->exit_ctx.CpuidAccess.Default= ResultRbx; + } else { + cpu_x86_cpuid(env, vcpu->exit_ctx.CpuidAccess.Rax, 0,=20 + (UINT32 *)®_values[1].Reg32, + (UINT32 *)®_values[4].Reg32, (UINT32 *)®_values[= 2].Reg32, + (UINT32 *)®_values[3].Reg32); + } + + if (!whpx->hyperv_enlightenments_enabled) { + switch (vcpu->exit_ctx.CpuidAccess.Rax) { + case 1: + if (cpu_has_x2apic_feature(env)) { + reg_values[2].Reg64 |=3D CPUID_EXT_X2APIC; + } + reg_values[2].Reg64 |=3D CPUID_EXT_HYPERVISOR; + break; + case 0x40000000: + /* report KVM */ + if (x86_cpu->vmware_cpuid_freq) { + reg_values[1].Reg64 =3D 0x40000010; + } else { + reg_values[1].Reg64 =3D 0x40000001; + } + reg_values[4].Reg64 =3D 0x4b4d564b; + reg_values[2].Reg64 =3D 0x564b4d56; + reg_values[3].Reg64 =3D 0x4d; + break; + case 0x40000001: + /* report X2APIC */ + reg_values[1].Reg64 =3D reg_values[4].Reg64 =3D reg_va= lues[2].Reg64 =3D 1 << 15; + break; + case 0x40000010: + if (x86_cpu->vmware_cpuid_freq) { + reg_values[1].Reg64 =3D env->tsc_khz; + reg_values[4].Reg64 =3D env->apic_bus_freq / 1000;= /* Hz to KHz */ + } + break; } } =20 @@ -2259,6 +2292,24 @@ int whpx_init_vcpu(CPUState *cpu) env->apic_bus_freq =3D 1000000000; } =20 + /* When Hyper-V enlightenments are not active, fall back to the KVM on= es */ + if (!whpx->hyperv_enlightenments_enabled) { + UINT32 cpuidExitList[] =3D {1, 0x40000000, 0x40000001, 0x40000010= }; + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeCpuidExitList, + cpuidExitList, + RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set partition CpuidExitList hr= =3D%08lx", + hr); + ret =3D -EINVAL; + goto error; + } + } + vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; cpu->accel =3D vcpu; @@ -2507,6 +2558,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) } =20 if (!is_legacy_os && whpx->hyperv_enlightenments_allowed) { + whpx->hyperv_enlightenments_enabled =3D true; hr =3D whp_dispatch.WHvSetPartitionProperty( whpx->partition, WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks, --=20 2.50.1 (Apple Git-155)