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Thu, 02 Apr 2026 08:48:28 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [RFC PATCH] target/arm: always propagate s1ns state on faults Date: Thu, 2 Apr 2026 16:48:21 +0100 Message-ID: <20260402154821.2340594-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1775144968420158500 According to our mmuidx documentation: we fold together most secure and non-secure regimes for A-profile, because there are no banked system registers for aarch64 So we don't hold quite enough information during the table walk to infer we are in secure mode. When we are trying to access a none-secure page we get a stage 1 translation like: (rr) p ptw $1 =3D (S1Translate *) 0x7f07479f93a0 (rr) p *ptw $2 =3D {in_mmu_idx =3D ARMMMUIdx_Stage2, in_ptw_idx =3D ARMMMUIdx_Phys_S,= in_space =3D ARMSS_NonSecure, cur_space =3D ARMSS_NonSecure, in_debug =3D = false, in_at =3D false, in_s1_is_el0 =3D false, in_prot_check =3D 1 '\001', in_nv1 =3D false, o= ut_rw =3D true, out_be =3D false, out_space =3D ARMSS_Secure, out_virt =3D = 1075929104, out_phys =3D 1075929104, out_host =3D 0x7f0750016010} However as we only write HFPAR_EL2.NS when arm_is_secure_below_el3(env) && fi.s1ns we can afford to relax the check in fault_s1ns. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2568 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/ptw.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d5b2ed6c99c..ccdc1ef9916 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -634,9 +634,11 @@ static bool fault_s1ns(ARMSecuritySpace space, ARMMMUI= dx s2_mmu_idx) * For stage 2 faults in Secure EL22, S1NS indicates * whether the faulting IPA is in the Secure or NonSecure * IPA space. For all other kinds of fault, it is false. + * + * At this point we can't actually tell we are in SEL[012] but the + * actual setting of HPFAR_EL2.NS is gated by arm_is_secure_below_el3(= env). */ - return space =3D=3D ARMSS_Secure && regime_is_stage2(s2_mmu_idx) - && s2_mmu_idx =3D=3D ARMMMUIdx_Stage2_S; + return space =3D=3D ARMSS_NonSecure && regime_is_stage2(s2_mmu_idx); } =20 /* Translate a S1 pagetable walk through S2 if needed. */ --=20 2.47.3