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Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 01/10] target/i386/tcg/sysemu: Move target specific SMM code to separate functions Date: Thu, 2 Apr 2026 11:51:23 +0200 Message-ID: <20260402095132.29245-2-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123608960158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth This code movement will make the next patch easier to read. Signed-off-by: Thomas Huth --- target/i386/tcg/system/smm_helper.c | 47 ++++++++++++++++++----------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/s= mm_helper.c index fb028a8272f..3be78cd53d3 100644 --- a/target/i386/tcg/system/smm_helper.c +++ b/target/i386/tcg/system/smm_helper.c @@ -32,26 +32,13 @@ #define SMM_REVISION_ID 0x00020000 #endif =20 -void do_smm_enter(X86CPU *cpu) +static void sm_state_init(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); - target_ulong sm_state; SegmentCache *dt; int i, offset; - - qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); - log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); - - env->msr_smi_count++; - env->hflags |=3D HF_SMM_MASK; - if (env->hflags2 & HF2_NMI_MASK) { - env->hflags2 |=3D HF2_SMM_INSIDE_NMI_MASK; - } else { - env->hflags2 |=3D HF2_NMI_MASK; - } - - sm_state =3D env->smbase + 0x8000; + target_ulong sm_state =3D env->smbase + 0x8000; =20 #ifdef TARGET_X86_64 for (i =3D 0; i < 6; i++) { @@ -156,6 +143,25 @@ void do_smm_enter(X86CPU *cpu) x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); #endif +} + +void do_smm_enter(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); + + env->msr_smi_count++; + env->hflags |=3D HF_SMM_MASK; + if (env->hflags2 & HF2_NMI_MASK) { + env->hflags2 |=3D HF2_SMM_INSIDE_NMI_MASK; + } else { + env->hflags2 |=3D HF2_NMI_MASK; + } + + sm_state_init(cpu); + /* init SMM cpu state */ =20 #ifdef TARGET_X86_64 @@ -191,9 +197,8 @@ void do_smm_enter(X86CPU *cpu) DESC_G_MASK | DESC_A_MASK); } =20 -void helper_rsm(CPUX86State *env) +static void rsm_load_regs(CPUX86State *env) { - X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; @@ -308,6 +313,14 @@ void helper_rsm(CPUX86State *env) env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7ef8); } #endif +} + +void helper_rsm(CPUX86State *env) +{ + X86CPU *cpu =3D env_archcpu(env); + + rsm_load_regs(env); + if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) =3D=3D 0) { env->hflags2 &=3D ~HF2_NMI_MASK; } --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1775123534; cv=none; d=zohomail.com; s=zohoarc; b=MKQqVVD3TbmYTwmxyTP/w/NlonOESorTX5HdaBSR5pIy7as5cqTX6HOE3wKRoJIkG5zHHo0o5LWUwZoUT12cLV7gClDEwnluuAoYsfrxFC/utoeUOsBm9HXtTHOZF2ged5GVaLjaFn9QHGSg4ybVejSb/b4NEJcXO3b+tL1V7iw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775123534; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 2 Apr 2026 09:51:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1775123510; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SdGyZXxwTYuvuSTrhC9NuPS6j2R9Ll8NKs9BQm1mdDs=; b=T2Qz7GlkMRycp47XE91inaz1dXRhSB2x40dDBHth/91FufPGjE6EnOpKOIxv4z3/CDiT+b RhM5e9vGZAdSO91crDLPDFzeRlJ7keznhX1Ysj8FR51A7y+vuXAeahGJdWu2/4QFnU/n6q /ViFRXCw4YGogya4vkXHxc1OgcgS9/k= X-MC-Unique: Jy3nCGZGP4CMkyty9WW0EQ-1 X-Mimecast-MFC-AGG-ID: Jy3nCGZGP4CMkyty9WW0EQ_1775123508 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Pierrick Bouvier , "Michael S. Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 02/10] target/i386/tcg/sysemu: Allow 32-bit SMM code to be used in the 64-bit binary Date: Thu, 2 Apr 2026 11:51:24 +0200 Message-ID: <20260402095132.29245-3-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 27 X-Spam_score: 2.7 X-Spam_bar: ++ X-Spam_report: (2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123537100158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth This is a preparation for the QEMU universal binary where we might want to support both, the x86_64 and the i386 target, in one binary. Instead of using #ifdef TARGET_X86_64 here, check the LM bit to select the 32-bit or 64-bit code during runtime. Signed-off-by: Thomas Huth --- target/i386/tcg/system/smm_helper.c | 65 +++++++++++++++++++---------- 1 file changed, 43 insertions(+), 22 deletions(-) diff --git a/target/i386/tcg/system/smm_helper.c b/target/i386/tcg/system/s= mm_helper.c index 3be78cd53d3..4bbe18a86fb 100644 --- a/target/i386/tcg/system/smm_helper.c +++ b/target/i386/tcg/system/smm_helper.c @@ -23,24 +23,15 @@ #include "exec/log.h" #include "tcg/helper-tcg.h" =20 - -/* SMM support */ - -#ifdef TARGET_X86_64 -#define SMM_REVISION_ID 0x00020064 -#else -#define SMM_REVISION_ID 0x00020000 -#endif - -static void sm_state_init(X86CPU *cpu) +static void sm_state_init_64(X86CPU *cpu) { +#ifdef TARGET_X86_64 CPUX86State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); SegmentCache *dt; int i, offset; target_ulong sm_state =3D env->smbase + 0x8000; =20 -#ifdef TARGET_X86_64 for (i =3D 0; i < 6; i++) { dt =3D &env->segs[i]; offset =3D 0x7e00 + i * 16; @@ -92,9 +83,21 @@ static void sm_state_init(X86CPU *cpu) x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]); =20 - x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); + x86_stl_phys(cs, sm_state + 0x7efc, 0x00020064); /* SMM revision ID= */ x86_stl_phys(cs, sm_state + 0x7f00, env->smbase); #else + g_assert_not_reached(); +#endif +} + +static void sm_state_init_32(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + SegmentCache *dt; + int i, offset; + target_ulong sm_state =3D env->smbase + 0x8000; + x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]); x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]); x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env)); @@ -140,9 +143,8 @@ static void sm_state_init(X86CPU *cpu) } x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]); =20 - x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID); + x86_stl_phys(cs, sm_state + 0x7efc, 0x00020000); /* SMM revision ID = */ x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); -#endif } =20 void do_smm_enter(X86CPU *cpu) @@ -160,13 +162,15 @@ void do_smm_enter(X86CPU *cpu) env->hflags2 |=3D HF2_NMI_MASK; } =20 - sm_state_init(cpu); + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + sm_state_init_64(cpu); + cpu_load_efer(env, 0); + } else { + sm_state_init_32(cpu); + } =20 /* init SMM cpu state */ =20 -#ifdef TARGET_X86_64 - cpu_load_efer(env, 0); -#endif cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); env->eip =3D 0x00008000; @@ -197,15 +201,16 @@ void do_smm_enter(X86CPU *cpu) DESC_G_MASK | DESC_A_MASK); } =20 -static void rsm_load_regs(CPUX86State *env) +static void rsm_load_regs_64(CPUX86State *env) { +#ifdef TARGET_X86_64 CPUState *cs =3D env_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; =20 sm_state =3D env->smbase + 0x8000; -#ifdef TARGET_X86_64 + cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0)); =20 env->gdt.base =3D x86_ldq_phys(cs, sm_state + 0x7e68); @@ -260,6 +265,19 @@ static void rsm_load_regs(CPUX86State *env) env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7f00); } #else + g_assert_not_reached(); +#endif +} + +static void rsm_load_regs_32(CPUX86State *env) +{ + CPUState *cs =3D env_cpu(env); + target_ulong sm_state; + int i, offset; + uint32_t val; + + sm_state =3D env->smbase + 0x8000; + cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8)); cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4), @@ -312,14 +330,17 @@ static void rsm_load_regs(CPUX86State *env) if (val & 0x20000) { env->smbase =3D x86_ldl_phys(cs, sm_state + 0x7ef8); } -#endif } =20 void helper_rsm(CPUX86State *env) { X86CPU *cpu =3D env_archcpu(env); =20 - rsm_load_regs(env); + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + rsm_load_regs_64(env); + } else { + rsm_load_regs_32(env); + } =20 if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) =3D=3D 0) { env->hflags2 &=3D ~HF2_NMI_MASK; --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=dv1YI4XrKEmMX/Zt2Oo13rUJH4BE6rgNyaSFSxxmRGMPiWmiHiZ3s2/X0VrU4W2rypdUYy lfUPm3NCwulFrj4pjCA1TYlulPAYZ5jfOgypX/0NyyFPAmtm+gSRPmvIKymJt0rk0IgTVO q/ClnUfj9sgv5oDQfZcBKJOtz4STjp8= X-MC-Unique: 7nke4crjMUKsWlTaIIdl0Q-1 X-Mimecast-MFC-AGG-ID: 7nke4crjMUKsWlTaIIdl0Q_1775123511 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Pierrick Bouvier , "Michael S. Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 03/10] target-info: Add functions for querying whether the target is i386 or x86_64 Date: Thu, 2 Apr 2026 11:51:25 +0200 Message-ID: <20260402095132.29245-4-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123550777158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth As we already have functions for querying whether the target architecture is one of the various ppc, arm or s390x flavours, add now some functions for x86, too, which will come in handy to decide during runtime whether we are running in 32 or 64-bit mode in the x86 targets. Signed-off-by: Thomas Huth --- include/qemu/target-info.h | 21 +++++++++++++++++++++ target-info.c | 21 +++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 23c997de541..0713ab4bb16 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -99,4 +99,25 @@ bool target_ppc64(void); */ bool target_s390x(void); =20 +/** + * target_base_x86: + * + * Returns whether the target architecture is x86 (32-bit or 64-bit). + */ +bool target_base_x86(void); + +/** + * target_i386: + * + * Returns whether the target architecture is x86 32-bit. + */ +bool target_i386(void); + +/** + * target_x86_64: + * + * Returns whether the target architecture is x86 64-bit. + */ +bool target_x86_64(void); + #endif diff --git a/target-info.c b/target-info.c index 28c458fc7a7..dea73b5fbca 100644 --- a/target-info.c +++ b/target-info.c @@ -93,3 +93,24 @@ bool target_s390x(void) { return target_arch() =3D=3D SYS_EMU_TARGET_S390X; } + +bool target_base_x86(void) +{ + switch (target_arch()) { + case SYS_EMU_TARGET_I386: + case SYS_EMU_TARGET_X86_64: + return true; + default: + return false; + } +} + +bool target_i386(void) +{ + return target_arch() =3D=3D SYS_EMU_TARGET_I386; +} + +bool target_x86_64(void) +{ + return target_arch() =3D=3D SYS_EMU_TARGET_X86_64; +} --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1775123594; cv=none; d=zohomail.com; s=zohoarc; b=h0RvaMEI6roqMyy5QOxD4vD31/LKhkuz+Fa41LkQZed2f1jIAJ07l4oxXuKa8/pylrrIDk5VmI6luBQAPPq910ATDpYhEUPtnOIBSNzCLJ8wRjPXevUfrod5zhlf06e+rZ82S4YA9aHwqISfpdZ9dwFoTiKfd7irac5DwqHWKlk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 2 Apr 2026 09:51:55 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.44.34.44]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 1360C196B088; Thu, 2 Apr 2026 09:51:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1775123520; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qIToqHE3DYdE6OROkXm1aZvJg+93ZnbgMttNmMm5Ihs=; b=LwfkUB5zjDgTVaF4ePdBgggVyo8rTYJALKQHLJXzhEngR+oxGUK0M/y0xBnLA1wZIjG3a9 uPTlQPMZUiEymMGSjqOdV7bvOSl+zfltWr8WWD7mEQ/wDou83U+NeewShCFlMdxUFTRtce UbsPjxJX/gk0NO1huhp9s5ha/0DO9ls= X-MC-Unique: BFZieF7GP8-DbkfgPZqHTQ-1 X-Mimecast-MFC-AGG-ID: BFZieF7GP8-DbkfgPZqHTQ_1775123515 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Pierrick Bouvier , "Michael S. Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 04/10] cpu: Add a way to detect 32-bit mode from argv0 Date: Thu, 2 Apr 2026 11:51:26 +0200 Message-ID: <20260402095132.29245-5-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123597003154100 Content-Type: text/plain; charset="utf-8" From: Thomas Huth In the future, we might want to avoid compiling certain targets separately for 32-bit mode (i.e. -i386, -arm and -ppc) where the 64-bit variant is a superset of the 32-bit variant. But it would be good to provide a way to mimic the 32-bit behavior via the program name in case the users need this compatibility for some scenarios. Thus add a function that checks for the old 32-bit program names and sets a flag accordingly. Signed-off-by: Thomas Huth --- include/qemu/target-info.h | 7 +++++++ system/vl.c | 1 + target-info.c | 20 ++++++++++++++++++-- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 0713ab4bb16..aa9b2e9b0cf 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -9,6 +9,13 @@ #ifndef QEMU_TARGET_INFO_H #define QEMU_TARGET_INFO_H =20 +/** + * target_info_adjust: + * + * Returns: Adjust the target according to the binary name of the executab= le. + */ +void target_info_adjust(const char *argv0); + /** * target_name: * diff --git a/system/vl.c b/system/vl.c index 246623b3196..45c9f5d5c7a 100644 --- a/system/vl.c +++ b/system/vl.c @@ -2884,6 +2884,7 @@ void qemu_init(int argc, char **argv) =20 error_init(argv[0]); qemu_init_exec_dir(argv[0]); + target_info_adjust(argv[0]); =20 os_setup_limits(); =20 diff --git a/target-info.c b/target-info.c index dea73b5fbca..b18fd4e0060 100644 --- a/target-info.c +++ b/target-info.c @@ -12,6 +12,21 @@ #include "qemu/target-info-impl.h" #include "qapi/error.h" =20 +static bool force_32bit; + +void target_info_adjust(const char *argv0) +{ + switch (target_arch()) { + case SYS_EMU_TARGET_X86_64: + if (g_str_has_suffix(argv0, "-i386")) { + force_32bit =3D true; + } + break; + default: + break; + } +} + const char *target_name(void) { return target_info()->target_name; @@ -107,10 +122,11 @@ bool target_base_x86(void) =20 bool target_i386(void) { - return target_arch() =3D=3D SYS_EMU_TARGET_I386; + return target_arch() =3D=3D SYS_EMU_TARGET_I386 || + (target_arch() =3D=3D SYS_EMU_TARGET_X86_64 && force_32bit); } =20 bool target_x86_64(void) { - return target_arch() =3D=3D SYS_EMU_TARGET_X86_64; + return target_arch() =3D=3D SYS_EMU_TARGET_X86_64 && !force_32bit; } --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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b=S520Cr0OnOoBzHdgnhm6fcuBO7sEoz3twcKwQbLABo0kUy9ulftG0RfBX9pdeEbAZTxoik JabrrSPn4TD1TKzxJNTKmXDBSr9CmSJU1NGqBdGC9tl3QmTcuRkGXScNGPYzMRKLbD6uHZ 7BzSCvvCmmjCdHS4Ea9z9kWdXBdSHr4= X-MC-Unique: vir7AfNrO3OJaPqoP7-ShQ-1 X-Mimecast-MFC-AGG-ID: vir7AfNrO3OJaPqoP7-ShQ_1775123519 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Pierrick Bouvier , "Michael S. Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 05/10] target/i386/cpu: Allow to limit the 64-bit binary to 32-bit mode only Date: Thu, 2 Apr 2026 11:51:27 +0200 Message-ID: <20260402095132.29245-6-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 27 X-Spam_score: 2.7 X-Spam_bar: ++ X-Spam_report: (2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123625061158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth qemu-system-x86_64 is pretty much a proper superset of qemu-system-i386, so in the long run, it does not make too much sense that we continuously build two binaries here, we should deprecate the latter rather sooner than later. However, some people still might want to start QEMU in a mode that limits the environment to 32-bit. Thus allow qemu-system-x86_64 to run in 32-bit mode if the binary name ends in "-i386". Signed-off-by: Thomas Huth --- target/i386/cpu.h | 15 +++------------ target/i386/cpu.c | 20 ++++++++++---------- target/i386/gdbstub.c | 2 +- 3 files changed, 14 insertions(+), 23 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0b539155c40..9cb357aa797 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -36,13 +36,8 @@ =20 #define XEN_NR_VIRQS 24 =20 -#ifdef TARGET_X86_64 -#define I386_ELF_MACHINE EM_X86_64 -#define ELF_MACHINE_UNAME "x86_64" -#else -#define I386_ELF_MACHINE EM_386 -#define ELF_MACHINE_UNAME "i686" -#endif +#define I386_ELF_MACHINE (target_x86_64() ? EM_X86_64 : EM_386) +#define ELF_MACHINE_UNAME (target_x86_64() ? "x86_64" : "i686") =20 enum { R_EAX =3D 0, @@ -277,11 +272,7 @@ typedef enum X86Seg { #define CR4_PKS_MASK (1U << 24) #define CR4_LAM_SUP_MASK (1U << 28) =20 -#ifdef TARGET_X86_64 -#define CR4_FRED_MASK (1ULL << 32) -#else -#define CR4_FRED_MASK 0 -#endif +#define CR4_FRED_MASK (target_x86_64() ? (1ULL << 32) : 0) =20 #define CR4_RESERVED_MASK \ (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c6fd1dc00eb..e30d47831d6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8094,18 +8094,18 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU = *cpu, FeatureWord w) } =20 switch (w) { -#ifndef TARGET_X86_64 case FEAT_8000_0001_EDX: /* * 32-bit TCG can emulate 64-bit compatibility mode. If there is = no * way for userspace to get out of its 32-bit jail, we can leave * the LM bit set. */ - unavail =3D tcg_enabled() - ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES - : CPUID_EXT2_LM; + if (target_i386()) { + unavail =3D tcg_enabled() + ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES + : CPUID_EXT2_LM; + } break; -#endif =20 case FEAT_8000_0007_EBX: if (cpu && !IS_AMD_CPU(&cpu->env)) { @@ -8351,11 +8351,11 @@ static void x86_cpu_load_model(X86CPU *cpu, const X= 86CPUModel *model) =20 static const gchar *x86_gdb_arch_name(CPUState *cs) { -#ifdef TARGET_X86_64 - return "i386:x86-64"; -#else - return "i386"; -#endif + if (target_x86_64()) { + return "i386:x86-64"; + } else { + return "i386"; + } } =20 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index 5c5fa727216..951c443e6d2 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -498,7 +498,7 @@ void x86_cpu_gdb_init(CPUState *cs) #ifdef TARGET_X86_64 CPUX86State *env =3D &X86_CPU(cs)->env; =20 - if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APXF) { + if (target_x86_64() && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AP= XF)) { gdb_register_coprocessor(cs, i386_cpu_gdb_get_egprs, i386_cpu_gdb_set_egprs, gdb_find_static_feature("i386-64bit-apx.x= ml")); --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1775123584; cv=none; d=zohomail.com; s=zohoarc; b=dh4o//QonqI/7JdVF/Ob+hy7o/Mo5DkG40pXjMoqhQVOtrCUHXUwMXGoF1Dn91PFIKSeD0jtizqKanzVvLeWg5HHsZgjEbog12dZmwFH4+IUXSyIjRzPrKlqQU4Ri6h8l6T3hRar562qpyNUAw+YPGxRON1Sb4Fm5whEF6eqCZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775123584; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dt8BivEK1e7GnYfJ7w9mJBRBOXLtkOE3S+CxgwChgzo=; b=Es7JMYkMPX1nP9zdVZ+rgRbwzOMR10Vca6TZm9PsTkBc+Uo0kXIfLEHprBFxgwbwsFxeXj3A+gFI23TbJpjio5unBcFSMA+78Uz+Rh81olPLVgN+wbT57XfXzrpCoDkVr5pIxxEU1Bey9/ZYEnHq+b/LH3xzAUdAA65VUUZ35B0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775123584102439.3304718207586; Thu, 2 Apr 2026 02:53:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w8Eif-00071B-4w; Thu, 02 Apr 2026 05:52:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w8Eid-0006yq-IB for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:52:07 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w8Eic-0008S0-6C for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:52:07 -0400 Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-570-8sF4b54nNTqA0AxrS3CC9A-1; Thu, 02 Apr 2026 05:52:04 -0400 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 21B8C195606B; Thu, 2 Apr 2026 09:52:03 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.44.34.44]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 5A1BA196B088; Thu, 2 Apr 2026 09:52:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1775123525; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dt8BivEK1e7GnYfJ7w9mJBRBOXLtkOE3S+CxgwChgzo=; b=YCURX5fhXJQcgiJL8rvNGMp0vtl9VX08+m1B+mEc//Vyxdg3h0x8rD0L2+Ssjx88Uvey5A tRNngCJSeYyX7kwcSOyHLicISuRC+g2R7iUjtMON3dMNLeXaxwtWk6aSiFJAJdSjyzArrq P32Mw6jmfTYydOURc5HfdBxXbUutA8Q= X-MC-Unique: 8sF4b54nNTqA0AxrS3CC9A-1 X-Mimecast-MFC-AGG-ID: 8sF4b54nNTqA0AxrS3CC9A_1775123523 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Pierrick Bouvier , "Michael S. Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 06/10] target/i386: Select a 32-bit/64-bit default CPU during runtime Date: Thu, 2 Apr 2026 11:51:28 +0200 Message-ID: <20260402095132.29245-7-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 27 X-Spam_score: 2.7 X-Spam_bar: ++ X-Spam_report: (2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123584840158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth For supporting both, the i386 and the x86_64 target in one binary, TARGET_DEFAULT_CPU_TYPE needs to be adjusted during runtime. Signed-off-by: Thomas Huth --- target/i386/cpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9cb357aa797..9d71d1dcca7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2777,7 +2777,9 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define CPU_RESOLVING_TYPE TYPE_X86_CPU =20 #ifdef TARGET_X86_64 -#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") +#define TARGET_DEFAULT_CPU_TYPE \ + (target_i386() ? X86_CPU_TYPE_NAME("qemu32") \ + : X86_CPU_TYPE_NAME("qemu64")) #else #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") #endif --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1775123548; cv=none; d=zohomail.com; s=zohoarc; b=c/l6yEeL+25BYm3KJrNYH3HPthxHVOlIVatchG9ldKCUk9exU710HehPJSwg6qcGXKoH3Xg/a9UBiC13ySd82sOS6WxgpvYY6Rt4HKsXYCk9qyVh+Wfwr6PnXxNH/rocEyd2l55FxxKc4NR+gfwg9+f42DPi3UCt5HnjHExQYSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775123548; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pyTPQJzVYC5in5/dSMWzlphXYjyzR9HnC+1W6LLvFtY=; b=jmDSltOsyvqaTdxRxpOTYuRQPLYhnZbf6HoZKRdReDCbGytE8hJXWhCshwrS+/KoS5e0qUx5QgRy/pONI7Cd7FSLiaq5G0uXOMJiEyKsV3Q2+oXQE11QUxqCayDWhgsjiaOHMjtBeMbisdAFoHCJCHGN3r46eLFlup76i9l+cog= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775123548119488.3334181677079; Thu, 2 Apr 2026 02:52:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w8Eio-00077c-PY; Thu, 02 Apr 2026 05:52:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w8Eik-00076Q-N4 for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:52:14 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w8Eij-0008So-5q for qemu-devel@nongnu.org; Thu, 02 Apr 2026 05:52:14 -0400 Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-421-7i9MxwZBPai4bpNIaxBBiw-1; Thu, 02 Apr 2026 05:52:09 -0400 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id E4FD21956063; Thu, 2 Apr 2026 09:52:07 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.44.34.44]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id AB16C196B088; Thu, 2 Apr 2026 09:52:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1775123532; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pyTPQJzVYC5in5/dSMWzlphXYjyzR9HnC+1W6LLvFtY=; b=ZHJG/iOhB21yb6RmD8tL7wgilgLLoa7B4orLxhQhTCaxBYPx2inVEzuwYTlInEN78fdwPh upn2oWp1PoUcJufj7OYj6DRJ0Sb1ZOkkOoDSClt1HefhVzcsnuXIUqJZa0KwxoFz3+5T6s fQHZG7V09nuN6lgubmTqGLAeRXKhec8= X-MC-Unique: 7i9MxwZBPai4bpNIaxBBiw-1 X-Mimecast-MFC-AGG-ID: 7i9MxwZBPai4bpNIaxBBiw_1775123528 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Pierrick Bouvier , "Michael S. Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 07/10] target/i386: Adjust the suffix of the CPU devices to 32-bit/64-bit mode Date: Thu, 2 Apr 2026 11:51:29 +0200 Message-ID: <20260402095132.29245-8-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 27 X-Spam_score: 2.7 X-Spam_bar: ++ X-Spam_report: (2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123550595154100 Content-Type: text/plain; charset="utf-8" From: Thomas Huth qemu-system-i386 uses the suffix "-i386-cpu" for the CPU devices, while qemu-system-x86_64 uses the suffix "-x86_64-cpu" instead. For supporting both targets in one binary, we have to adjust the suffix during runtime. Signed-off-by: Thomas Huth --- target/i386/cpu.h | 3 ++- target/i386/cpu.c | 29 ++++++++++++++++++++++++----- target/i386/host-cpu.c | 6 +++++- 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9d71d1dcca7..38309773ea8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2775,10 +2775,11 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t = new_dr7); uint64_t cpu_get_tsc(CPUX86State *env); =20 #define CPU_RESOLVING_TYPE TYPE_X86_CPU +#define I386_CPU_TYPE_SUFFIX "-i386-cpu" =20 #ifdef TARGET_X86_64 #define TARGET_DEFAULT_CPU_TYPE \ - (target_i386() ? X86_CPU_TYPE_NAME("qemu32") \ + (target_i386() ? "qemu32" I386_CPU_TYPE_SUFFIX \ : X86_CPU_TYPE_NAME("qemu64")) #else #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e30d47831d6..98e03cb9a88 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2276,7 +2276,11 @@ void host_cpuid(uint32_t function, uint32_t count, */ static char *x86_cpu_type_name(const char *model_name) { - return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); + if (target_i386()) { + return g_strdup_printf("%s" I386_CPU_TYPE_SUFFIX, model_name); + } else { + return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); + } } =20 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) @@ -2288,7 +2292,16 @@ static ObjectClass *x86_cpu_class_by_name(const char= *cpu_model) static char *x86_cpu_class_get_model_name(X86CPUClass *cc) { const char *class_name =3D object_class_get_name(OBJECT_CLASS(cc)); - assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); + const char *type_suffix; + + if (target_i386()) { + type_suffix =3D I386_CPU_TYPE_SUFFIX; + } else { + type_suffix =3D X86_CPU_TYPE_SUFFIX; + } + + assert(g_str_has_suffix(class_name, type_suffix)); + return cpu_model_from_type(class_name); } =20 @@ -7266,7 +7279,7 @@ static void max_x86_cpu_initfn(Object *obj) } } =20 -static const TypeInfo max_x86_cpu_type_info =3D { +static TypeInfo max_x86_cpu_type_info =3D { .name =3D X86_CPU_TYPE_NAME("max"), .parent =3D TYPE_X86_CPU, .instance_init =3D max_x86_cpu_initfn, @@ -7884,7 +7897,8 @@ static gint x86_cpu_list_compare(gconstpointer a, gco= nstpointer b, gpointer d) =20 static GSList *get_sorted_cpu_model_list(void) { - GSList *list =3D object_class_get_list(TYPE_X86_CPU, false); + GSList *list =3D object_class_get_list(target_i386() ? + "i386-cpu" : TYPE_X86_CPU, false); list =3D g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); return list; } @@ -10818,7 +10832,7 @@ static void x86_cpu_base_class_init(ObjectClass *oc= , const void *data) xcc->ordering =3D 8; } =20 -static const TypeInfo x86_base_cpu_type_info =3D { +static TypeInfo x86_base_cpu_type_info =3D { .name =3D X86_CPU_TYPE_NAME("base"), .parent =3D TYPE_X86_CPU, .class_init =3D x86_cpu_base_class_init, @@ -10832,6 +10846,11 @@ static void x86_cpu_register_types(void) for (i =3D 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { x86_register_cpudef_types(&builtin_x86_defs[i]); } + + if (target_i386()) { + x86_base_cpu_type_info.name =3D "base" I386_CPU_TYPE_SUFFIX; + max_x86_cpu_type_info.name =3D "max" I386_CPU_TYPE_SUFFIX; + } type_register_static(&max_x86_cpu_type_info); type_register_static(&x86_base_cpu_type_info); } diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c index d5e2bb5e187..a6b8bb484b3 100644 --- a/target/i386/host-cpu.c +++ b/target/i386/host-cpu.c @@ -179,7 +179,7 @@ static void host_cpu_class_init(ObjectClass *oc, const = void *data) g_strdup_printf("processor with all supported host features "); } =20 -static const TypeInfo host_cpu_type_info =3D { +static TypeInfo host_cpu_type_info =3D { .name =3D X86_CPU_TYPE_NAME("host"), .parent =3D X86_CPU_TYPE_NAME("max"), .class_init =3D host_cpu_class_init, @@ -187,6 +187,10 @@ static const TypeInfo host_cpu_type_info =3D { =20 static void host_cpu_type_init(void) { + if (target_i386()) { + host_cpu_type_info.name =3D "host" I386_CPU_TYPE_SUFFIX; + host_cpu_type_info.parent =3D "max" I386_CPU_TYPE_SUFFIX; + } type_register_static(&host_cpu_type_info); } =20 --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1775123568; cv=none; d=zohomail.com; s=zohoarc; b=oGBUBrOLvWLmYBSDNTtWwb3BJ0Ig9q7ryKDPyG+da3L6jQaed16pzmvKG1cHXnAF3WxECo9xgbnmeI9Loe1bHPnljyjh25JAyfkoW5qK9tKfzA+QEbe23FQvu8rx5Of/mnhH52HHtNYHbvFhVRK9sQAsEjXlLqrmFb7Pizm0F6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775123568; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 2 Apr 2026 09:52:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1775123536; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sPFlzk9ZLlZHPOcJhaP/VkTFHtoZ9xuGlVYtWm9rC1k=; b=MNK30biTDm96fwJ578FEh6uuymQ3y0mKKphVd/ne+oEx/YzOR5l1W/7UkR1yc58hXB32wD TpzKdwJX5FLY/aJz1iqVdZJmKJlg4AJl4IpGF/H5ouhC9nYhr0JCasBWz9/5Sho1AOPgAf b1itlgAt1IE8Z5jtC7TO/K7H/hq1/FM= X-MC-Unique: 1vhEy7nAPBuHaAth0OIBwQ-1 X-Mimecast-MFC-AGG-ID: 1vhEy7nAPBuHaAth0OIBwQ_1775123531 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Pierrick Bouvier , "Michael S. Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 08/10] hw/i386/isapc: Adjust the check for valid CPUs in the isapc machine Date: Thu, 2 Apr 2026 11:51:30 +0200 Message-ID: <20260402095132.29245-9-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 27 X-Spam_score: 2.7 X-Spam_bar: ++ X-Spam_report: (2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_SBL_CSS=3.335, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123568936158500 Content-Type: text/plain; charset="utf-8" From: Thomas Huth Now that we can run in both, x86_64 and i386 mode with one binary, we must not hard-code the suffix of the CPU names here anymore. Signed-off-by: Thomas Huth --- target/i386/cpu.h | 1 + hw/i386/isapc.c | 18 ++++++++++-------- target/i386/cpu.c | 2 +- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 38309773ea8..78f2dadc2e3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2722,6 +2722,7 @@ void mark_unavailable_features(X86CPU *cpu, FeatureWo= rd w, uint64_t mask, const char *verbose_prefix); void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, const char *verbose_prefix); +char *x86_cpu_type_name(const char *model_name); =20 static inline bool x86_has_cpuid_0x1f(X86CPU *cpu) { diff --git a/hw/i386/isapc.c b/hw/i386/isapc.c index 1ba9ae22cc3..c772b7f533a 100644 --- a/hw/i386/isapc.c +++ b/hw/i386/isapc.c @@ -43,13 +43,13 @@ static void pc_init_isa(MachineState *machine) =20 bool valid_cpu_type =3D false; static const char * const valid_cpu_types[] =3D { - X86_CPU_TYPE_NAME("486"), - X86_CPU_TYPE_NAME("athlon"), - X86_CPU_TYPE_NAME("kvm32"), - X86_CPU_TYPE_NAME("pentium"), - X86_CPU_TYPE_NAME("pentium2"), - X86_CPU_TYPE_NAME("pentium3"), - X86_CPU_TYPE_NAME("qemu32"), + "486", + "athlon", + "kvm32", + "pentium", + "pentium2", + "pentium3", + "qemu32", }; =20 /* @@ -59,8 +59,10 @@ static void pc_init_isa(MachineState *machine) * a warning if anyone tries to use a deprecated CPU. */ for (i =3D 0; i < ARRAY_SIZE(valid_cpu_types); i++) { - if (!strcmp(machine->cpu_type, valid_cpu_types[i])) { + g_autofree char *valid_cpu =3D x86_cpu_type_name(valid_cpu_types[i= ]); + if (!strcmp(machine->cpu_type, valid_cpu)) { valid_cpu_type =3D true; + break; } } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 98e03cb9a88..a8ff1b29f33 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2274,7 +2274,7 @@ void host_cpuid(uint32_t function, uint32_t count, /* Return type name for a given CPU model name * Caller is responsible for freeing the returned string. */ -static char *x86_cpu_type_name(const char *model_name) +char *x86_cpu_type_name(const char *model_name) { if (target_i386()) { return g_strdup_printf("%s" I386_CPU_TYPE_SUFFIX, model_name); --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1775123540; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1gBbz0lXmLXZQfWTPJ1x/oz786AusvxHAXLc6WW8Klk=; b=cU+j3yFzsVA5KzeyJqg7qlV/Rb9wd8AD6OWhfOd4ZBa4JSQ75sGjCS1+o7gZ8NgltvcA+q 1hz7lukx1lXXk343cDPe2+03IU+kBYBZSF1WB5M6xuaBLosPx/Eoi8knwwarafQI/yN5FF TABXk1IXX2yBFIUnGtDhRJZa+2nn7sk= X-MC-Unique: 4uqSidACPHiJXw1hTNwhTg-1 X-Mimecast-MFC-AGG-ID: 4uqSidACPHiJXw1hTNwhTg_1775123536 From: Thomas Huth To: Paolo Bonzini , qemu-devel@nongnu.org Cc: Pierrick Bouvier , "Michael S. Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 09/10] target/i386: Support migrating from i386 to x86_64 target Date: Thu, 2 Apr 2026 11:51:31 +0200 Message-ID: <20260402095132.29245-10-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123641721154100 Content-Type: text/plain; charset="utf-8" From: Thomas Huth For migrating from qemu-system-i386 to qemu-system-x86_64, we have to support the CPU vmstate of the 32-bit target. Signed-off-by: Thomas Huth --- target/i386/cpu.h | 47 +++++++-- target/i386/cpu.c | 8 +- target/i386/machine.c | 222 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 270 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 78f2dadc2e3..88fcf44fdc0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1632,6 +1632,13 @@ typedef struct SegmentCache { uint32_t flags; } SegmentCache; =20 +typedef struct SegmentCache32 { + uint32_t selector; + uint32_t base; + uint32_t limit; + uint32_t flags; +} SegmentCache32; + typedef union MMXReg { uint8_t _b_MMXReg[64 / 8]; uint16_t _w_MMXReg[64 / 16]; @@ -1974,10 +1981,16 @@ typedef struct CPUCaches { typedef struct CPUArchState { /* standard registers */ target_ulong regs[CPU_NB_EREGS]; - target_ulong eip; - target_ulong eflags; /* eflags register. During CPU emulation, CC - flags and DF are set to zero because they are - stored elsewhere */ + union { + target_ulong eip; + uint32_t eip32; + }; + union { + target_ulong eflags; /* eflags register. During CPU emulation, CC + flags and DF are set to zero because they = are + stored elsewhere */ + uint32_t eflags32; + }; =20 /* emulator internal eflags handling */ target_ulong cc_dst; @@ -2042,8 +2055,14 @@ typedef struct CPUArchState { =20 /* sysenter registers */ uint32_t sysenter_cs; - target_ulong sysenter_esp; - target_ulong sysenter_eip; + union { + target_ulong sysenter_esp; + uint32_t sysenter_esp32; + }; + union { + target_ulong sysenter_eip; + uint32_t sysenter_eip32; + }; uint64_t star; =20 uint64_t vm_hsave; @@ -2294,6 +2313,21 @@ typedef struct CPUArchState { uint16_t fptag_vmstate; uint16_t fpregs_format_vmstate; =20 +#ifdef TARGET_X86_64 + /* + * These fields are only used for migrating from qemu-system-i386 + * to qemu-system-x86_64 + */ + uint32_t regs32[CPU_NB_REGS32]; + SegmentCache32 segs32[6]; /* selector values */ + SegmentCache32 ldt32; + SegmentCache32 tr32; + SegmentCache32 gdt32; /* only base and limit are used */ + SegmentCache32 idt32; /* only base and limit are used */ + uint32_t cr32[5]; + uint32_t dr32[8]; +#endif + uint64_t xss; uint32_t umwait; =20 @@ -2546,6 +2580,7 @@ struct X86CPUClass { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_x86_cpu; +extern const VMStateDescription vmstate_i386_cpu; #endif =20 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a8ff1b29f33..a087a45dbfe 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10701,7 +10701,7 @@ static const Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" =20 -static const struct SysemuCPUOps i386_sysemu_ops =3D { +static struct SysemuCPUOps i386_sysemu_ops =3D { .has_work =3D x86_cpu_has_work, .get_memory_mapping =3D x86_cpu_get_memory_mapping, .get_paging_enabled =3D x86_cpu_get_paging_enabled, @@ -10746,8 +10746,14 @@ static void x86_cpu_common_class_init(ObjectClass = *oc, const void *data) =20 #ifndef CONFIG_USER_ONLY cc->max_as =3D X86ASIdx_MAX; +#ifdef TARGET_X86_64 + if (target_i386()) { + i386_sysemu_ops.legacy_vmsd =3D &vmstate_i386_cpu; + } +#endif cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ + #ifdef CONFIG_TCG cc->tcg_ops =3D &x86_tcg_ops; #endif /* CONFIG_TCG */ diff --git a/target/i386/machine.c b/target/i386/machine.c index 48a2a4b3190..bb6019d3419 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -310,6 +310,44 @@ static int cpu_pre_save(void *opaque) return 0; } =20 + +#ifdef TARGET_X86_64 +static void copy_segcache(SegmentCache32 *sc32, SegmentCache *sc64) +{ + sc64->selector =3D sc32->selector; + sc64->base =3D sc32->base; + sc64->limit =3D sc32->limit; + sc64->flags =3D sc32->flags; +} +#endif + +static void cpu_post_load_fixup32(CPUX86State *env) +{ +#ifdef TARGET_X86_64 + int i; + + for (i =3D 0; i < CPU_NB_REGS32; i++) { + env->regs[i] =3D env->regs32[i]; + } + + for (i =3D 0; i < ARRAY_SIZE(env->segs); i++) { + copy_segcache(&env->segs32[i], &env->segs[i]); + } + + copy_segcache(&env->ldt32, &env->ldt); + copy_segcache(&env->tr32, &env->tr); + copy_segcache(&env->gdt32, &env->gdt); + copy_segcache(&env->idt32, &env->idt); + + for (i =3D 0; i < ARRAY_SIZE(env->cr); i++) { + env->cr[i] =3D env->cr32[i]; + } + for (i =3D 0; i < ARRAY_SIZE(env->dr); i++) { + env->dr[i] =3D env->dr32[i]; + } +#endif +} + static int cpu_post_load(void *opaque, int version_id) { X86CPU *cpu =3D opaque; @@ -317,6 +355,10 @@ static int cpu_post_load(void *opaque, int version_id) CPUX86State *env =3D &cpu->env; int i; =20 + if (target_i386()) { + cpu_post_load_fixup32(env); + } + if (env->tsc_khz && env->user_tsc_khz && env->tsc_khz !=3D env->user_tsc_khz) { error_report("Mismatch between user-specified TSC frequency and " @@ -1920,3 +1962,183 @@ const VMStateDescription vmstate_x86_cpu =3D { NULL } }; + +/* ***************** 32-bit target hacks below **************** */ + +#ifdef TARGET_X86_64 + +static const VMStateDescription vmstate_segment32 =3D { + .name =3D "segment", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(selector, SegmentCache32), + VMSTATE_UINT32(base, SegmentCache32), + VMSTATE_UINT32(limit, SegmentCache32), + VMSTATE_UINT32(flags, SegmentCache32), + VMSTATE_END_OF_LIST() + } +}; + +#define VMSTATE_SEGMENT32(_field, _state) { \ + .name =3D (stringify(_field)), \ + .size =3D sizeof(SegmentCache32), \ + .vmsd =3D &vmstate_segment32, \ + .flags =3D VMS_STRUCT, \ + .offset =3D offsetof(_state, _field) \ + + type_check(SegmentCache32, typeof_field(_state, _field)) \ +} + +#define VMSTATE_SEGMENT32_ARRAY(_field, _state, _n) \ + VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment32, Segment= Cache32) + +#define VMSTATE_XMM32_REGS(_field, _state, _start) \ + VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS32, 0, \ + vmstate_xmm_reg, ZMMReg) + +#define VMSTATE_YMMH32_REGS_VARS(_field, _state, _start, _v) \ + VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS32, _v, \ + vmstate_ymmh_reg, ZMMReg) + +const VMStateDescription vmstate_i386_cpu =3D { + .name =3D "cpu", + .version_id =3D 12, + .minimum_version_id =3D 11, + .pre_save =3D cpu_pre_save, + .post_load =3D cpu_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_SUB_ARRAY(env.regs32, X86CPU, 0, CPU_NB_REGS32), + VMSTATE_UINT32(env.eip32, X86CPU), + VMSTATE_UINT32(env.eflags32, X86CPU), + VMSTATE_UINT32(env.hflags, X86CPU), + /* FPU */ + VMSTATE_UINT16(env.fpuc, X86CPU), + VMSTATE_UINT16(env.fpus_vmstate, X86CPU), + VMSTATE_UINT16(env.fptag_vmstate, X86CPU), + VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU), + + VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPRe= g), + + VMSTATE_SEGMENT32_ARRAY(env.segs32, X86CPU, 6), + VMSTATE_SEGMENT32(env.ldt32, X86CPU), + VMSTATE_SEGMENT32(env.tr32, X86CPU), + VMSTATE_SEGMENT32(env.gdt32, X86CPU), + VMSTATE_SEGMENT32(env.idt32, X86CPU), + + VMSTATE_UINT32(env.sysenter_cs, X86CPU), + VMSTATE_UINT32(env.sysenter_esp32, X86CPU), + VMSTATE_UINT32(env.sysenter_eip32, X86CPU), + + VMSTATE_UINT32(env.cr32[0], X86CPU), + VMSTATE_UINT32(env.cr32[2], X86CPU), + VMSTATE_UINT32(env.cr32[3], X86CPU), + VMSTATE_UINT32(env.cr32[4], X86CPU), + VMSTATE_UINT32_ARRAY(env.dr32, X86CPU, 8), + /* MMU */ + VMSTATE_INT32(env.a20_mask, X86CPU), + /* XMM */ + VMSTATE_UINT32(env.mxcsr, X86CPU), + VMSTATE_XMM32_REGS(env.xmm_regs, X86CPU, 0), + + VMSTATE_UINT32(env.smbase, X86CPU), + + VMSTATE_UINT64(env.pat, X86CPU), + VMSTATE_UINT32(env.hflags2, X86CPU), + + VMSTATE_UINT64(env.vm_hsave, X86CPU), + VMSTATE_UINT64(env.vm_vmcb, X86CPU), + VMSTATE_UINT64(env.tsc_offset, X86CPU), + VMSTATE_UINT64(env.intercept, X86CPU), + VMSTATE_UINT16(env.intercept_cr_read, X86CPU), + VMSTATE_UINT16(env.intercept_cr_write, X86CPU), + VMSTATE_UINT16(env.intercept_dr_read, X86CPU), + VMSTATE_UINT16(env.intercept_dr_write, X86CPU), + VMSTATE_UINT32(env.intercept_exceptions, X86CPU), + VMSTATE_UINT8(env.v_tpr, X86CPU), + /* MTRRs */ + VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11), + VMSTATE_UINT64(env.mtrr_deftype, X86CPU), + VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8), + /* KVM-related states */ + VMSTATE_INT32(env.interrupt_injected, X86CPU), + VMSTATE_UINT32(env.mp_state, X86CPU), + VMSTATE_UINT64(env.tsc, X86CPU), + VMSTATE_INT32(env.exception_nr, X86CPU), + VMSTATE_UINT8(env.soft_interrupt, X86CPU), + VMSTATE_UINT8(env.nmi_injected, X86CPU), + VMSTATE_UINT8(env.nmi_pending, X86CPU), + VMSTATE_UINT8(env.has_error_code, X86CPU), + VMSTATE_UINT32(env.sipi_vector, X86CPU), + /* MCE */ + VMSTATE_UINT64(env.mcg_cap, X86CPU), + VMSTATE_UINT64(env.mcg_status, X86CPU), + VMSTATE_UINT64(env.mcg_ctl, X86CPU), + VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4), + /* rdtscp */ + VMSTATE_UINT64(env.tsc_aux, X86CPU), + /* KVM pvclock msr */ + VMSTATE_UINT64(env.system_time_msr, X86CPU), + VMSTATE_UINT64(env.wall_clock_msr, X86CPU), + /* XSAVE related fields */ + VMSTATE_UINT64_V(env.xcr0, X86CPU, 12), + VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12), + VMSTATE_YMMH32_REGS_VARS(env.xmm_regs, X86CPU, 0, 12), + VMSTATE_END_OF_LIST() + /* The above list is not sorted /wrt version numbers, watch out! */ + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_exception_info, + &vmstate_error_code, + &vmstate_async_pf_msr, + &vmstate_async_pf_int_msr, + &vmstate_pv_eoi_msr, + &vmstate_steal_time_msr, + &vmstate_poll_control_msr, + &vmstate_fpop_ip_dp, + &vmstate_msr_tsc_adjust, + &vmstate_msr_tscdeadline, + &vmstate_msr_ia32_misc_enable, + &vmstate_msr_ia32_feature_control, + &vmstate_msr_architectural_pmu, + &vmstate_mpx, + &vmstate_msr_hyperv_hypercall, + &vmstate_msr_hyperv_vapic, + &vmstate_msr_hyperv_time, + &vmstate_msr_hyperv_crash, + &vmstate_msr_hyperv_runtime, + &vmstate_msr_hyperv_synic, + &vmstate_msr_hyperv_stimer, + &vmstate_msr_hyperv_reenlightenment, + &vmstate_avx512, + &vmstate_xss, + &vmstate_umwait, + &vmstate_tsc_khz, + &vmstate_msr_smi_count, + &vmstate_pkru, + &vmstate_pkrs, + &vmstate_spec_ctrl, + &amd_tsc_scale_msr_ctrl, + &vmstate_mcg_ext_ctl, + &vmstate_msr_intel_pt, + &vmstate_msr_virt_ssbd, + &vmstate_svm_npt, + &vmstate_svm_guest, +#ifdef CONFIG_KVM + &vmstate_nested_state, + &vmstate_xen_vcpu, +#endif + &vmstate_msr_tsx_ctrl, + &vmstate_msr_intel_sgx, + &vmstate_pdptrs, + &vmstate_msr_xfd, + &vmstate_msr_hwcr, + &vmstate_arch_lbr, + &vmstate_triple_fault, + &vmstate_pl0_ssp, + &vmstate_cet, + + NULL + } +}; + +#endif /* TARGET_X86_64 */ --=20 2.53.0 From nobody Sat Apr 11 18:38:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1775123601; cv=none; d=zohomail.com; s=zohoarc; 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Tsirkin" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zhao Liu , Thomas Huth Subject: [PATCH 10/10] docs/about/deprecated: Deprecate the qemu-system-i386 binary Date: Thu, 2 Apr 2026 11:51:32 +0200 Message-ID: <20260402095132.29245-11-thuth@redhat.com> In-Reply-To: <20260402095132.29245-1-thuth@redhat.com> References: <20260402095132.29245-1-thuth@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.54, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1775123602945158500 From: Thomas Huth Aside from not supporting KVM on 32-bit hosts, the qemu-system-x86_64 binary is a proper superset of the qemu-system-i386 binary. And with the 32-bit x86 host support being removed now, it is possible to deprecate the qemu-system-i386 binary now, too. With regards to 32-bit KVM support in the x86 Linux kernel, the developers confirmed that they do not need a recent qemu-system-i386 binary here: https://lore.kernel.org/kvm/Y%2ffkTs5ajFy0hP1U@google.com/ Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Thomas Huth --- docs/about/deprecated.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index a6d6a713265..2de51337d75 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -301,6 +301,25 @@ machine must ensure that they're setting the ``spike``= machine in the command line (``-M spike``). =20 =20 +System emulator binaries +------------------------ + +``qemu-system-i386`` binary (since 11.1) +'''''''''''''''''''''''''''''''''''''''' + +The ``qemu-system-i386`` binary was mainly useful for running with KVM +on 32-bit x86 hosts, but most Linux distributions already removed their +support for 32-bit x86 kernels, so hardly anybody still needs this. The +``qemu-system-x86_64`` binary is a proper superset and can be used to +run 32-bit guests by selecting a 32-bit CPU model, including KVM support +on x86_64 hosts. Thus users are recommended to reconfigure their systems +to use the ``qemu-system-x86_64`` binary instead. If a 32-bit CPU guest +environment should be enforced, you can switch off the "long mode" CPU +flag with ``-cpu max,lm=3Doff``, or rename/symlink ``qemu-system-x86_64`` +to ``qemu-system-i386`` -- QEMU will then run with the 64-bit extensions +disabled. + + Backend options --------------- =20 --=20 2.53.0