From nobody Tue Apr 7 21:48:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1775137568; cv=none; d=zohomail.com; s=zohoarc; b=lu1wgUxzpIRG7j/I86wZW5L/ea44gTGIcSIKJiz5VUc6PCvkUnjmiFSSyI/DDiYnRHHq11czKNViIdFZn4XQZ40LE5cmKZIr5F7NfBsUffNQ9J3rYEtHl0JmyUQI+swj1jcsIfmNY72KldpQwkBS62guBq36aYFDh1U9dLk/iMg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775137568; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HJT/I+bbATbzpZa7IFBQev2FeK1wmUQopVue49jowBM=; b=iZC9RetY34F4T7cW+H/Usy4jJia2PnyUlH6PFK0S5Lg46wtql032pz3m1WroqaI7lt+0cbH/32t1gkonoUcD4HP5BeIYmj9q4LcKVmrSNqD3F5VPVye4Bir4zUrTMO3H6RPdQjCGmPi4cmBcRnWVdvNXnzVD8nHYD0kEsCBHHdE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775137568116584.2624399659313; Thu, 2 Apr 2026 06:46:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w8ILI-0008P4-Sn; Thu, 02 Apr 2026 09:44:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w8IKw-0004lE-8H; Thu, 02 Apr 2026 09:43:55 -0400 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w8HXl-0008QM-JN; Thu, 02 Apr 2026 08:53:09 -0400 Received: from localhost (unknown [131.107.147.136]) by linux.microsoft.com (Postfix) with ESMTPSA id 5803620B7135; Thu, 2 Apr 2026 05:52:59 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 5803620B7135 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1775134379; bh=HJT/I+bbATbzpZa7IFBQev2FeK1wmUQopVue49jowBM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SCHwIjL692COZw/8pbjnMyFLcDEBqUgjJxhYYbB2tMutNb0ass7XBrDxmTE9R2Rq+ S9la6TDwxEvlbT8HBds/MXENFavkTnF37TXsPiuXFDRSNP8TWFwlup3XfyjMdcKeuQ +apmEAUZ82TEGl37mFZ0vmoXhNKhqyrp8XU4315s= From: Aastha Rawat Date: Thu, 02 Apr 2026 12:52:29 +0000 Subject: [PATCH v2 02/14] accel/mshv: extract common CPU register helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260402-mshv_accel_arm64_supp-v2-2-754895c15e9e@linux.microsoft.com> References: <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com> In-Reply-To: <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com> To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Paolo Bonzini , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Anirudh Rayabharam , Aastha Rawat , Magnus Kulke , qemu-arm@nongnu.org, Alexander Graf , Pedro Barbuda , Mohamed Mediouni X-Mailer: b4 0.15.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1775137570871154100 Move arch-independent MSHV CPU register handling functions into accel/mshv/mshv-cpu-common.c. Update x86 MSHV backends to use these shared helpers. Prefix get_generic_regs() with mshv_ for proper namespacing since it is now public. Signed-off-by: Aastha Rawat --- accel/mshv/meson.build | 3 +- accel/mshv/mshv-cpu-common.c | 151 +++++++++++++++++++++++++++++++++++++++= ++++ include/system/mshv_int.h | 3 + target/i386/mshv/mshv-cpu.c | 130 +------------------------------------ 4 files changed, 159 insertions(+), 128 deletions(-) diff --git a/accel/mshv/meson.build b/accel/mshv/meson.build index e433187cde..ebe32921b3 100644 --- a/accel/mshv/meson.build +++ b/accel/mshv/meson.build @@ -1,5 +1,6 @@ system_ss.add(when: 'CONFIG_MSHV', if_true: files( 'irq.c', 'mem.c', - 'mshv-all.c' + 'mshv-all.c', + 'mshv-cpu-common.c' )) diff --git a/accel/mshv/mshv-cpu-common.c b/accel/mshv/mshv-cpu-common.c new file mode 100644 index 0000000000..b104720161 --- /dev/null +++ b/accel/mshv/mshv-cpu-common.c @@ -0,0 +1,151 @@ +/* + * QEMU MSHV common CPU register helpers + * + * Copyright Microsoft, Corp. 2026 + * + * Authors: Ziqiao Zhou + * Magnus Kulke + * Jinank Jain + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/memalign.h" + +#include "system/mshv.h" +#include "system/mshv_int.h" + +#include "hw/core/cpu.h" +#include "linux/mshv.h" + +#include + +int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *as= socs, + size_t n_regs) +{ + int cpu_fd =3D mshv_vcpufd(cpu); + int vp_index =3D cpu->cpu_index; + size_t in_sz, assocs_sz; + hv_input_set_vp_registers *in =3D cpu->accel->hvcall_args.input_page; + struct mshv_root_hvcall args =3D {0}; + int ret; + + /* find out the size of the struct w/ a flexible array at the tail */ + assocs_sz =3D n_regs * sizeof(hv_register_assoc); + in_sz =3D sizeof(hv_input_set_vp_registers) + assocs_sz; + + /* fill the input struct */ + memset(in, 0, sizeof(hv_input_set_vp_registers)); + in->vp_index =3D vp_index; + memcpy(in->elements, assocs, assocs_sz); + + /* create the hvcall envelope */ + args.code =3D HVCALL_SET_VP_REGISTERS; + args.in_sz =3D in_sz; + args.in_ptr =3D (uint64_t) in; + args.reps =3D (uint16_t) n_regs; + + /* perform the call */ + ret =3D mshv_hvcall(cpu_fd, &args); + if (ret < 0) { + error_report("Failed to set registers"); + return -1; + } + + /* assert we set all registers */ + if (args.reps !=3D n_regs) { + error_report("Failed to set registers: expected %zu elements" + ", got %u", n_regs, args.reps); + return -1; + } + + return 0; +} + +int mshv_get_generic_regs(CPUState *cpu, hv_register_assoc *assocs, + size_t n_regs) +{ + int cpu_fd =3D mshv_vcpufd(cpu); + int vp_index =3D cpu->cpu_index; + hv_input_get_vp_registers *in =3D cpu->accel->hvcall_args.input_page; + hv_register_value *values =3D cpu->accel->hvcall_args.output_page; + size_t in_sz, names_sz, values_sz; + int i, ret; + struct mshv_root_hvcall args =3D {0}; + + /* find out the size of the struct w/ a flexible array at the tail */ + names_sz =3D n_regs * sizeof(hv_register_name); + in_sz =3D sizeof(hv_input_get_vp_registers) + names_sz; + + /* fill the input struct */ + memset(in, 0, sizeof(hv_input_get_vp_registers)); + in->vp_index =3D vp_index; + for (i =3D 0; i < n_regs; i++) { + in->names[i] =3D assocs[i].name; + } + + /* determine size of value output buffer */ + values_sz =3D n_regs * sizeof(union hv_register_value); + + /* create the hvcall envelope */ + args.code =3D HVCALL_GET_VP_REGISTERS; + args.in_sz =3D in_sz; + args.in_ptr =3D (uint64_t) in; + args.out_sz =3D values_sz; + args.out_ptr =3D (uint64_t) values; + args.reps =3D (uint16_t) n_regs; + + /* perform the call */ + ret =3D mshv_hvcall(cpu_fd, &args); + if (ret < 0) { + error_report("Failed to retrieve registers"); + return -1; + } + + /* assert we got all registers */ + if (args.reps !=3D n_regs) { + error_report("Failed to retrieve registers: expected %zu elements" + ", got %u", n_regs, args.reps); + return -1; + } + + /* copy values into assoc */ + for (i =3D 0; i < n_regs; i++) { + assocs[i].value =3D values[i]; + } + + return 0; +} + +int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd) +{ + int ret; + struct mshv_create_vp vp_arg =3D { + .vp_index =3D vp_index, + }; + + ret =3D ioctl(vm_fd, MSHV_CREATE_VP, &vp_arg); + if (ret < 0) { + error_report("failed to create mshv vcpu: %s", strerror(errno)); + return -1; + } + + *cpu_fd =3D ret; + + return 0; +} + +void mshv_remove_vcpu(int vm_fd, int cpu_fd) +{ + close(cpu_fd); +} + +void mshv_setup_hvcall_args(AccelCPUState *state) +{ + void *mem =3D qemu_memalign(HV_HYP_PAGE_SIZE, 2 * HV_HYP_PAGE_SIZE); + + state->hvcall_args.base =3D mem; + state->hvcall_args.input_page =3D mem; + state->hvcall_args.output_page =3D (uint8_t *)mem + HV_HYP_PAGE_SIZE; +} diff --git a/include/system/mshv_int.h b/include/system/mshv_int.h index 35386c422f..ff3ab957b5 100644 --- a/include/system/mshv_int.h +++ b/include/system/mshv_int.h @@ -89,12 +89,15 @@ int mshv_load_regs(CPUState *cpu); int mshv_store_regs(CPUState *cpu); int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *as= socs, size_t n_regs); +int mshv_get_generic_regs(CPUState *cpu, hv_register_assoc *assocs, + size_t n_regs); int mshv_arch_put_registers(const CPUState *cpu); void mshv_arch_init_vcpu(CPUState *cpu); void mshv_arch_destroy_vcpu(CPUState *cpu); void mshv_arch_amend_proc_features( union hv_partition_synthetic_processor_features *features); int mshv_arch_post_init_vm(int vm_fd); +void mshv_setup_hvcall_args(AccelCPUState *state); =20 typedef struct mshv_root_hvcall mshv_root_hvcall; int mshv_hvcall(int fd, const mshv_root_hvcall *args); diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 2bc978deb2..9a80dc34d0 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -148,103 +148,6 @@ static int translate_gva(const CPUState *cpu, uint64_= t gva, uint64_t *gpa, return 0; } =20 -int mshv_set_generic_regs(const CPUState *cpu, const hv_register_assoc *as= socs, - size_t n_regs) -{ - int cpu_fd =3D mshv_vcpufd(cpu); - int vp_index =3D cpu->cpu_index; - size_t in_sz, assocs_sz; - hv_input_set_vp_registers *in =3D cpu->accel->hvcall_args.input_page; - struct mshv_root_hvcall args =3D {0}; - int ret; - - /* find out the size of the struct w/ a flexible array at the tail */ - assocs_sz =3D n_regs * sizeof(hv_register_assoc); - in_sz =3D sizeof(hv_input_set_vp_registers) + assocs_sz; - - /* fill the input struct */ - memset(in, 0, sizeof(hv_input_set_vp_registers)); - in->vp_index =3D vp_index; - memcpy(in->elements, assocs, assocs_sz); - - /* create the hvcall envelope */ - args.code =3D HVCALL_SET_VP_REGISTERS; - args.in_sz =3D in_sz; - args.in_ptr =3D (uint64_t) in; - args.reps =3D (uint16_t) n_regs; - - /* perform the call */ - ret =3D mshv_hvcall(cpu_fd, &args); - if (ret < 0) { - error_report("Failed to set registers"); - return -1; - } - - /* assert we set all registers */ - if (args.reps !=3D n_regs) { - error_report("Failed to set registers: expected %zu elements" - ", got %u", n_regs, args.reps); - return -1; - } - - return 0; -} - -static int get_generic_regs(CPUState *cpu, hv_register_assoc *assocs, - size_t n_regs) -{ - int cpu_fd =3D mshv_vcpufd(cpu); - int vp_index =3D cpu->cpu_index; - hv_input_get_vp_registers *in =3D cpu->accel->hvcall_args.input_page; - hv_register_value *values =3D cpu->accel->hvcall_args.output_page; - size_t in_sz, names_sz, values_sz; - int i, ret; - struct mshv_root_hvcall args =3D {0}; - - /* find out the size of the struct w/ a flexible array at the tail */ - names_sz =3D n_regs * sizeof(hv_register_name); - in_sz =3D sizeof(hv_input_get_vp_registers) + names_sz; - - /* fill the input struct */ - memset(in, 0, sizeof(hv_input_get_vp_registers)); - in->vp_index =3D vp_index; - for (i =3D 0; i < n_regs; i++) { - in->names[i] =3D assocs[i].name; - } - - /* determine size of value output buffer */ - values_sz =3D n_regs * sizeof(union hv_register_value); - - /* create the hvcall envelope */ - args.code =3D HVCALL_GET_VP_REGISTERS; - args.in_sz =3D in_sz; - args.in_ptr =3D (uint64_t) in; - args.out_sz =3D values_sz; - args.out_ptr =3D (uint64_t) values; - args.reps =3D (uint16_t) n_regs; - - /* perform the call */ - ret =3D mshv_hvcall(cpu_fd, &args); - if (ret < 0) { - error_report("Failed to retrieve registers"); - return -1; - } - - /* assert we got all registers */ - if (args.reps !=3D n_regs) { - error_report("Failed to retrieve registers: expected %zu elements" - ", got %u", n_regs, args.reps); - return -1; - } - - /* copy values into assoc */ - for (i =3D 0; i < n_regs; i++) { - assocs[i].value =3D values[i]; - } - - return 0; -} - static int set_standard_regs(const CPUState *cpu) { X86CPU *x86cpu =3D X86_CPU(cpu); @@ -334,7 +237,7 @@ int mshv_get_standard_regs(CPUState *cpu) for (size_t i =3D 0; i < n_regs; i++) { assocs[i].name =3D STANDARD_REGISTER_NAMES[i]; } - ret =3D get_generic_regs(cpu, assocs, n_regs); + ret =3D mshv_get_generic_regs(cpu, assocs, n_regs); if (ret < 0) { error_report("failed to get standard registers"); return -1; @@ -412,7 +315,7 @@ int mshv_get_special_regs(CPUState *cpu) for (size_t i =3D 0; i < n_regs; i++) { assocs[i].name =3D SPECIAL_REGISTER_NAMES[i]; } - ret =3D get_generic_regs(cpu, assocs, n_regs); + ret =3D mshv_get_generic_regs(cpu, assocs, n_regs); if (ret < 0) { error_report("failed to get special registers"); return -errno; @@ -1525,29 +1428,6 @@ int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_messa= ge *msg, MshvVmExit *exit) return 0; } =20 -void mshv_remove_vcpu(int vm_fd, int cpu_fd) -{ - close(cpu_fd); -} - - -int mshv_create_vcpu(int vm_fd, uint8_t vp_index, int *cpu_fd) -{ - int ret; - struct mshv_create_vp vp_arg =3D { - .vp_index =3D vp_index, - }; - ret =3D ioctl(vm_fd, MSHV_CREATE_VP, &vp_arg); - if (ret < 0) { - error_report("failed to create mshv vcpu: %s", strerror(errno)); - return -1; - } - - *cpu_fd =3D ret; - - return 0; -} - static void read_segment_descriptor(CPUState *cpu, struct x86_segment_descriptor *desc, enum X86Seg seg_idx) @@ -1580,8 +1460,6 @@ void mshv_arch_init_vcpu(CPUState *cpu) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; AccelCPUState *state =3D cpu->accel; - size_t page =3D HV_HYP_PAGE_SIZE; - void *mem =3D qemu_memalign(page, 2 * page); =20 /* sanity check, to make sure we don't overflow the page */ QEMU_BUILD_BUG_ON((MAX_REGISTER_COUNT @@ -1589,9 +1467,7 @@ void mshv_arch_init_vcpu(CPUState *cpu) + sizeof(hv_input_get_vp_registers) > HV_HYP_PAGE_SIZE)); =20 - state->hvcall_args.base =3D mem; - state->hvcall_args.input_page =3D mem; - state->hvcall_args.output_page =3D (uint8_t *)mem + page; + mshv_setup_hvcall_args(state); =20 env->emu_mmio_buf =3D g_new(char, 4096); } --=20 2.45.4