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Wed, 01 Apr 2026 12:21:22 -0700 (PDT) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, jim.macarthur@linaro.org, Richard Henderson , philmd@linaro.org, Paolo Bonzini , Pierrick Bouvier Subject: [PATCH v6 12/12] target/arm/tcg/translate.c: replace target_ulong with uint32_t Date: Wed, 1 Apr 2026 12:20:57 -0700 Message-ID: <20260401192057.1182724-13-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260401192057.1182724-1-pierrick.bouvier@linaro.org> References: <20260401192057.1182724-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1775071410844154100 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier --- target/arm/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 4546bbeeeff..204f9657993 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -6450,7 +6450,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cpu) * fields here. */ uint32_t condexec_bits; - target_ulong pc_arg =3D dc->base.pc_next; + uint32_t pc_arg =3D dc->base.pc_next; =20 if (tb_cflags(dcbase->tb) & CF_PCREL) { pc_arg &=3D ~TARGET_PAGE_MASK; @@ -6612,7 +6612,7 @@ static void thumb_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) bool is_16bit; /* TCG op to rewind to if this turns out to be an invalid ECI state */ TCGOp *insn_eci_rewind =3D NULL; - target_ulong insn_eci_pc_save =3D -1; + uint32_t insn_eci_pc_save =3D -1; =20 /* Misaligned thumb PC is architecturally impossible. */ assert((dc->base.pc_next & 1) =3D=3D 0); --=20 2.47.3