From nobody Wed Apr 1 22:11:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1775057450; cv=none; d=zohomail.com; s=zohoarc; b=SgTVHzqpWX/ONHmv2/NpFFpl/o3qKuNob6YguiTA9oUDOQfG6bBxFyRWA6Ia55yGfz3xGAddSYs94yXO7wU+8mwEnKbN6LkC0J7Z/rPOoiiNrIbyNxDqhNwVMUg/wa4ToEJhBTCesDpF/XMqlZJppsku3eZgUgJKcaswr08Mzt8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775057450; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qxvGCeGyglPN4k1rILccHF+Z6VL6Mnxy7g+mcm6uGOg=; b=IS+n7jlsWh+qQ9wtba6mxMhfysyHlKwuIUlCJBPFd1QYrbl6aE64Paw8e8glT70+12Sk0bqkCA+3GIdUVnYRDi60Zr2T7kUmRdAJBhewMoNWWkKLn0KbAF1Nut1oSArm7IJaE9W+G89s/yzpk/At1+xPpjigq4vK6hBgUPbiu6I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775057450957865.7651914528616; Wed, 1 Apr 2026 08:30:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w7xUn-000164-7x; Wed, 01 Apr 2026 11:28:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w7xUm-00015G-8y for qemu-devel@nongnu.org; Wed, 01 Apr 2026 11:28:40 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w7xUj-00088E-0P for qemu-devel@nongnu.org; Wed, 01 Apr 2026 11:28:40 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 631F2eD41579389 for ; Wed, 1 Apr 2026 15:28:25 GMT Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d8mr2vbph-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 01 Apr 2026 15:28:20 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2c3b8880ca9so5709031eec.1 for ; Wed, 01 Apr 2026 08:28:18 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df3b84sm38491eec.5.2026.04.01.08.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 08:28:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= qxvGCeGyglPN4k1rILccHF+Z6VL6Mnxy7g+mcm6uGOg=; b=cigXxUs9EAstNuRC Y11cATkX+kivC3iLRMwGZq7NRHnAB7RSqund5I9gAAufo49UZERLQBlqjAjNLYJG ts6TDr2OiCOLtnYd2nCiZNVx+SDk3rbqp2+YOMoqLQLKWLMIrZBI6LmqwPBeFcdg NhABwaHdaULFfTMchKUUirG8EDOoBqhii8QDhK9uiSCXgpIbzJ4kc1JvpSP/lyki dmp2GDBBb5MdKzDhP3wSvdAZfri6jfVwfSeOs+PmmaxiYnkyWPYcSOjsvpWPyR1S OgJlGFnWJ8VuFE88pSfkRPXkUUSCxASI9072QcSdrPqYkA7bZblB9mRAycBQFCNQ DHlSmg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1775057297; x=1775662097; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qxvGCeGyglPN4k1rILccHF+Z6VL6Mnxy7g+mcm6uGOg=; b=cwBHoA3kQd1/kXIvbkIN0YkUA+MhYhRZI1zrig61hBX97KVunjODum5Zw0Zi1CYGbf giTgl8JjiQV9UyYQ1blHkYvnYPWolNynIYAVfcKyjTv+bH27cOHCSXXcN2NHwnZncHGQ 4Ea33tXGcGa86IngzTov5UaEwFDqgrjnN6u/uUb9vd2aReaQniZrk4J0cV8lriSD0G8q duAD2BgB6goSKThlKqjFqsTcxguq0+1Bto7Cf7QPOTf5xEpW1szbcix+ZPDjL+XzPdWx knLxpk7THZW910cbiBbYlXV/MzAPRuhppVuPg9NpCyjUdFFlacgAK5fD+8Dp/lq8CPR9 4Dtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775057297; x=1775662097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=qxvGCeGyglPN4k1rILccHF+Z6VL6Mnxy7g+mcm6uGOg=; b=bslGOpKJHi5+KxtU5pjTtCAnpOJqHCm3bF4RKFYBhwLYPGsU8WTQLA/3mYFSqbXkDH xPE56eOdGU33TZA0uNfcPNUfUHD97L46qXt2ogccoY1F5nkMRjd91WHNxabTFZ0sgtvR 4eh/uCRTycmEBe+HD8dXL1CZgP58k7X+aCT5FIiP9g3l05ldgEI7nSV5WfByWeIIH4E9 STssEOj/cNhySUHfgEBmUgGRqEJ9ZZE1jy5AA3croL3LUCLYhDFJBasnZuFz4wVBm0B4 638ZhSteuc93cAf7JXzqKEWUuMu2zEgmky9s6RsCq3jCZjuCSamNUH++tMcGI43YvuQ+ CtFw== X-Gm-Message-State: AOJu0YwRWgDIe4p7YiRzZylpIrc5NHa95nFhkMEHUtbE+V6AtZp107dS MjvmnXgC2vdxYCaXBSNDQCGuFrp+ROHat+7MyIPLX5N7GqCOuHpbnXj8KirE67m3vp/3AeFYKd2 MWaR0HlM6knOYydt2BT3tg4HaFx7R9hyuRD8z13FUCL1Zw1wmspcLtFNB/wsOQiqPwQ== X-Gm-Gg: ATEYQzyQKstdI4Kd9ErMByraibFZi0d1ZzLQu0wk1vcx/hasutWlWBSWquQQTxTccfn zL4PlhRgHY5uNTlu6QZmnfbzT+Rax2aKO0RA7BtWXBHmltrRRZ3+8m5FjYSLBOXO37rkuBOpqvS 7Evg4cU01Zy7cBI7n9x55hzrpdXUJPALUIyU4KE8dl3hR+ZHAoHxye8dtYFXBJHIVEH54Vj4uZY 4+l2tYiOFUWvJx9mu+1IKl0j0X/2Mpxm/0g+/hQ0ln1k4yyijhg1P/DA30ZG0WQihkJWHXOrgiv 4rGuPb7aCnXVcei42Hw9dI9Z2ClcoP5RlnUJVLvjV5aktxyIJM970L0A74DAm9GMO53yzbrj/vB xPQM5AGG9kK2JMnoyB6t6jD0AoGcv17302roVZvSZQJK8IGDQXbSNNfL1nMKjy3eRJX2o4g== X-Received: by 2002:a05:7300:d51b:b0:2c8:7172:3b96 with SMTP id 5a478bee46e88-2c9325b017emr2219200eec.18.1775057296553; Wed, 01 Apr 2026 08:28:16 -0700 (PDT) X-Received: by 2002:a05:7300:d51b:b0:2c8:7172:3b96 with SMTP id 5a478bee46e88-2c9325b017emr2219173eec.18.1775057295889; Wed, 01 Apr 2026 08:28:15 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com, marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng Subject: [PATCH v6 34/37] hw/hexagon: Introduce hexagon TLB device Date: Wed, 1 Apr 2026 08:26:54 -0700 Message-Id: <20260401152657.314902-35-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260401152657.314902-1-brian.cain@oss.qualcomm.com> References: <20260401152657.314902-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=B+O0EetM c=1 sm=1 tr=0 ts=69cd3994 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=_ljVuOvC_GqhvFfVm74A:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: f6OxWdo39XfAGDzD8Uh1YxcJdtOugLdr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDE0NCBTYWx0ZWRfXwNHKDOgwJ0G3 WeLjIKsKst3/s7NYRUW47aEvk7iNLoOr4aimOUjRhsXo50Bi8BQG2lM0We01sCwnAccunkmKVnJ 3cNStCvBqrZ/tJsBTUyMw/WLj2ZMr/VD5FggHJvcBiJdBVTRoaMoRpyqUlxBkPh3CrjzfPXRnJh siwCtECoJ9x75a9YgGLq0ykFgTqLi4mFmRc/j+Ao2tnej35EeuIU4XIVEuB1thq9KeoK1q+x0r1 r00eyhvP5kTl2ej3y/6XfdNelM+5o8Rrc2WvdhGFaCP2+06OIijuNvbDHQ5BOtXJyH53+j6A7f7 F0BKoLOwqgxIekJPGIqXUbKPeC/XTVztNtlc215to1tWlgVunmbBKe3XQ0Ccn1dWQrq3h4rGBDR 9yhdOGS4oXDMWRnHxD1JR7igug3mvoBw26wy36EkmiwWpQzAHeBkxJphpAOfP3GJZDGJYA7Yx+k Esn75JnZbXacRHUjbMg== X-Proofpoint-GUID: f6OxWdo39XfAGDzD8Uh1YxcJdtOugLdr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_04,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010144 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775057451371158500 Add the hexagon TLB QOM device model. Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon_tlb.h | 46 +++ target/hexagon/cpu.h | 7 + hw/hexagon/hexagon_tlb.c | 466 +++++++++++++++++++++++++++++++ target/hexagon/cpu.c | 3 + 4 files changed, 522 insertions(+) create mode 100644 include/hw/hexagon/hexagon_tlb.h create mode 100644 hw/hexagon/hexagon_tlb.c diff --git a/include/hw/hexagon/hexagon_tlb.h b/include/hw/hexagon/hexagon_= tlb.h new file mode 100644 index 00000000000..90d9ed84043 --- /dev/null +++ b/include/hw/hexagon/hexagon_tlb.h @@ -0,0 +1,46 @@ +/* + * Hexagon TLB QOM Device + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_HEXAGON_TLB_H +#define HW_HEXAGON_TLB_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "exec/hwaddr.h" +#include "exec/mmu-access-type.h" +#include "monitor/monitor.h" +#define TYPE_HEXAGON_TLB "hexagon-tlb" +OBJECT_DECLARE_SIMPLE_TYPE(HexagonTLBState, HEXAGON_TLB) + +struct HexagonTLBState { + SysBusDevice parent_obj; + + uint32_t num_entries; + uint64_t *entries; +}; + +uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index); +void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t valu= e); + +bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, MMUAccessType access_type, + hwaddr *PA, int *prot, uint64_t *size, + int32_t *excp, int *cause_code, int mmu_idx); + +uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, int *cause_code); + +int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry, + uint64_t index); + +void hexagon_tlb_dump(Monitor *mon, HexagonTLBState *tlb); + +bool hexagon_tlb_dump_entry(Monitor *mon, uint64_t entry); + +uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb); + +#endif /* HW_HEXAGON_TLB_H */ diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index d3361936d04..15dd99d2155 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -27,6 +27,9 @@ #define SREG_WRITES_MAX 2 #endif =20 +typedef struct HexagonTLBState HexagonTLBState; +typedef struct HexagonGlobalRegState HexagonGlobalRegState; + #include "cpu-qom.h" #include "exec/cpu-common.h" #include "exec/cpu-defs.h" @@ -46,6 +49,7 @@ #define REG_WRITES_MAX 32 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 +#define MAX_TLB_ENTRIES 1024 =20 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU #ifndef CONFIG_USER_ONLY @@ -175,6 +179,9 @@ struct ArchCPU { bool lldb_compat; target_ulong lldb_stack_adjust; bool short_circuit; +#ifndef CONFIG_USER_ONLY + HexagonTLBState *tlb; +#endif }; =20 #include "cpu_bits.h" diff --git a/hw/hexagon/hexagon_tlb.c b/hw/hexagon/hexagon_tlb.c new file mode 100644 index 00000000000..d218e97446c --- /dev/null +++ b/hw/hexagon/hexagon_tlb.c @@ -0,0 +1,466 @@ +/* + * Hexagon TLB QOM Device + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/hexagon/hexagon_tlb.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/resettable.h" +#include "migration/vmstate.h" +#include "monitor/monitor.h" +#include "qapi/error.h" +#include "exec/target_page.h" +#include "target/hexagon/cpu.h" +#include "target/hexagon/cpu_bits.h" + +/* PTE (TLB entry) field extraction */ +#define GET_PTE_PPD(entry) extract64((entry), 0, 24) +#define GET_PTE_C(entry) extract64((entry), 24, 4) +#define GET_PTE_U(entry) extract64((entry), 28, 1) +#define GET_PTE_R(entry) extract64((entry), 29, 1) +#define GET_PTE_W(entry) extract64((entry), 30, 1) +#define GET_PTE_X(entry) extract64((entry), 31, 1) +#define GET_PTE_VPN(entry) extract64((entry), 32, 20) +#define GET_PTE_ASID(entry) extract64((entry), 52, 7) +#define GET_PTE_ATR0(entry) extract64((entry), 59, 1) +#define GET_PTE_ATR1(entry) extract64((entry), 60, 1) +#define GET_PTE_PA35(entry) extract64((entry), 61, 1) +#define GET_PTE_G(entry) extract64((entry), 62, 1) +#define GET_PTE_V(entry) extract64((entry), 63, 1) + +/* PPD (physical page descriptor) */ +static inline uint64_t GET_PPD(uint64_t entry) +{ + return GET_PTE_PPD(entry) | (GET_PTE_PA35(entry) << 24); +} + +#define NO_ASID (1 << 8) + +typedef enum { + PGSIZE_4K, + PGSIZE_16K, + PGSIZE_64K, + PGSIZE_256K, + PGSIZE_1M, + PGSIZE_4M, + PGSIZE_16M, + PGSIZE_64M, + PGSIZE_256M, + PGSIZE_1G, +} tlb_pgsize_t; + +#define NUM_PGSIZE_TYPES (PGSIZE_1G + 1) + +static const char *pgsize_str[NUM_PGSIZE_TYPES] =3D { + "4K", + "16K", + "64K", + "256K", + "1M", + "4M", + "16M", + "64M", + "256M", + "1G", +}; + +#define INVALID_MASK 0xffffffffLL + +static const uint64_t encmask_2_mask[] =3D { + 0x0fffLL, /* 4k, 0000 */ + 0x3fffLL, /* 16k, 0001 */ + 0xffffLL, /* 64k, 0010 */ + 0x3ffffLL, /* 256k, 0011 */ + 0xfffffLL, /* 1m, 0100 */ + 0x3fffffLL, /* 4m, 0101 */ + 0xffffffLL, /* 16m, 0110 */ + 0x3ffffffLL, /* 64m, 0111 */ + 0xfffffffLL, /* 256m, 1000 */ + 0x3fffffffLL, /* 1g, 1001 */ + INVALID_MASK, /* RSVD, 1010 */ +}; + +static inline tlb_pgsize_t hex_tlb_pgsize_type(uint64_t entry) +{ + if (entry =3D=3D 0) { + qemu_log_mask(CPU_LOG_MMU, "%s: Supplied TLB entry was 0!\n", + __func__); + return 0; + } + tlb_pgsize_t size =3D ctz64(entry); + g_assert(size < NUM_PGSIZE_TYPES); + return size; +} + +static inline uint64_t hex_tlb_page_size_bytes(uint64_t entry) +{ + return 1ull << (qemu_target_page_bits() + 2 * hex_tlb_pgsize_type(entr= y)); +} + +static inline uint64_t hex_tlb_phys_page_num(uint64_t entry) +{ + uint32_t ppd =3D GET_PPD(entry); + return ppd >> 1; +} + +static inline uint64_t hex_tlb_phys_addr(uint64_t entry) +{ + uint64_t pagemask =3D encmask_2_mask[hex_tlb_pgsize_type(entry)]; + uint64_t pagenum =3D hex_tlb_phys_page_num(entry); + uint64_t PA =3D (pagenum << qemu_target_page_bits()) & (~pagemask); + return PA; +} + +static inline uint64_t hex_tlb_virt_addr(uint64_t entry) +{ + return (uint64_t)GET_PTE_VPN(entry) << qemu_target_page_bits(); +} + +bool hexagon_tlb_dump_entry(Monitor *mon, uint64_t entry) +{ + if (GET_PTE_V(entry)) { + uint64_t PA =3D hex_tlb_phys_addr(entry); + uint64_t VA =3D hex_tlb_virt_addr(entry); + monitor_printf(mon, "0x%016" PRIx64 ": ", entry); + monitor_printf(mon, "V:%" PRId64 " G:%" PRId64 + " A1:%" PRId64 " A0:%" PRId64, + GET_PTE_V(entry), + GET_PTE_G(entry), + GET_PTE_ATR1(entry), + GET_PTE_ATR0(entry)); + monitor_printf(mon, " ASID:0x%02" PRIx64 " VA:0x%08" PRIx64, + GET_PTE_ASID(entry), VA); + monitor_printf(mon, + " X:%" PRId64 " W:%" PRId64 " R:%" PRId64 + " U:%" PRId64 " C:%" PRId64, + GET_PTE_X(entry), + GET_PTE_W(entry), + GET_PTE_R(entry), + GET_PTE_U(entry), + GET_PTE_C(entry)); + monitor_printf(mon, " PA:0x%09" PRIx64 " SZ:%s (0x%" PRIx64 ")", + PA, pgsize_str[hex_tlb_pgsize_type(entry)], + hex_tlb_page_size_bytes(entry)); + monitor_printf(mon, "\n"); + return true; + } + + /* Not valid */ + return false; +} + +static inline bool hex_tlb_entry_match_noperm(uint64_t entry, uint32_t asi= d, + uint64_t VA) +{ + if (GET_PTE_V(entry)) { + if (GET_PTE_G(entry)) { + /* Global entry - ignore ASID */ + } else if (asid !=3D NO_ASID) { + uint32_t tlb_asid =3D GET_PTE_ASID(entry); + if (tlb_asid !=3D asid) { + return false; + } + } + + uint64_t page_size =3D hex_tlb_page_size_bytes(entry); + uint64_t page_start =3D + ROUND_DOWN(hex_tlb_virt_addr(entry), page_size); + if (page_start <=3D VA && VA < page_start + page_size) { + return true; + } + } + return false; +} + +static inline void hex_tlb_entry_get_perm(uint64_t entry, + MMUAccessType access_type, + int mmu_idx, int *prot, + int32_t *excp, int *cause_code) +{ + bool perm_x =3D GET_PTE_X(entry); + bool perm_w =3D GET_PTE_W(entry); + bool perm_r =3D GET_PTE_R(entry); + bool perm_u =3D GET_PTE_U(entry); + bool user_idx =3D mmu_idx =3D=3D MMU_USER_IDX; + + if (mmu_idx =3D=3D MMU_KERNEL_IDX) { + *prot =3D PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return; + } + + *prot =3D PAGE_VALID; + switch (access_type) { + case MMU_INST_FETCH: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_FETCH_NO_UPAGE; + } else if (!perm_x) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_FETCH_NO_XPAGE; + } + break; + case MMU_DATA_LOAD: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_UREAD; + } else if (!perm_r) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_READ; + } + break; + case MMU_DATA_STORE: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_UWRITE; + } else if (!perm_w) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_WRITE; + } + break; + } + + if (!user_idx || perm_u) { + if (perm_x) { + *prot |=3D PAGE_EXEC; + } + if (perm_r) { + *prot |=3D PAGE_READ; + } + if (perm_w) { + *prot |=3D PAGE_WRITE; + } + } +} + +static inline bool hex_tlb_entry_match(uint64_t entry, uint8_t asid, + uint32_t VA, + MMUAccessType access_type, hwaddr *= PA, + int *prot, uint64_t *size, + int32_t *excp, int *cause_code, + int mmu_idx) +{ + if (hex_tlb_entry_match_noperm(entry, asid, VA)) { + hex_tlb_entry_get_perm(entry, access_type, mmu_idx, prot, excp, + cause_code); + *PA =3D hex_tlb_phys_addr(entry); + *size =3D hex_tlb_page_size_bytes(entry); + return true; + } + return false; +} + +static bool hex_tlb_is_match(uint64_t entry1, uint64_t entry2, + bool consider_gbit) +{ + bool valid1 =3D GET_PTE_V(entry1); + bool valid2 =3D GET_PTE_V(entry2); + uint64_t size1 =3D hex_tlb_page_size_bytes(entry1); + uint64_t vaddr1 =3D ROUND_DOWN(hex_tlb_virt_addr(entry1), size1); + uint64_t size2 =3D hex_tlb_page_size_bytes(entry2); + uint64_t vaddr2 =3D ROUND_DOWN(hex_tlb_virt_addr(entry2), size2); + int asid1 =3D GET_PTE_ASID(entry1); + int asid2 =3D GET_PTE_ASID(entry2); + bool gbit1 =3D GET_PTE_G(entry1); + bool gbit2 =3D GET_PTE_G(entry2); + + if (!valid1 || !valid2) { + return false; + } + + if (((vaddr1 <=3D vaddr2) && (vaddr2 < (vaddr1 + size1))) || + ((vaddr2 <=3D vaddr1) && (vaddr1 < (vaddr2 + size2)))) { + if (asid1 =3D=3D asid2) { + return true; + } + if ((consider_gbit && gbit1) || gbit2) { + return true; + } + } + return false; +} + +/* Public API */ + +uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index) +{ + g_assert(index < tlb->num_entries); + return tlb->entries[index]; +} + +void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t valu= e) +{ + g_assert(index < tlb->num_entries); + tlb->entries[index] =3D value; +} + +bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, MMUAccessType access_type, + hwaddr *PA, int *prot, uint64_t *size, + int32_t *excp, int *cause_code, int mmu_idx) +{ + *PA =3D 0; + *prot =3D 0; + *size =3D 0; + *excp =3D 0; + *cause_code =3D 0; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + if (hex_tlb_entry_match(tlb->entries[i], asid, VA, access_type, + PA, prot, size, excp, cause_code, mmu_idx)= ) { + return true; + } + } + return false; +} + +uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, int *cause_code) +{ + uint32_t not_found =3D 0x80000000; + uint32_t idx =3D not_found; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + uint64_t entry =3D tlb->entries[i]; + if (hex_tlb_entry_match_noperm(entry, asid, VA)) { + if (idx !=3D not_found) { + *cause_code =3D HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH; + break; + } + idx =3D i; + } + } + + if (idx =3D=3D not_found) { + qemu_log_mask(CPU_LOG_MMU, + "%s: 0x%" PRIx32 ", 0x%08" PRIx32 " =3D> NOT FOUND\n= ", + __func__, asid, VA); + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s: 0x%" PRIx32 ", 0x%08" PRIx32 " =3D> %d\n", + __func__, asid, VA, idx); + } + + return idx; +} + +/* + * Return codes: + * 0 or positive index of match + * -1 multiple matches + * -2 no match + */ +int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry, + uint64_t index) +{ + int matches =3D 0; + int last_match =3D 0; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + if (hex_tlb_is_match(entry, tlb->entries[i], false)) { + matches++; + last_match =3D i; + } + } + + if (matches =3D=3D 1) { + return last_match; + } + if (matches =3D=3D 0) { + return -2; + } + return -1; +} + +void hexagon_tlb_dump(Monitor *mon, HexagonTLBState *tlb) +{ + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + hexagon_tlb_dump_entry(mon, tlb->entries[i]); + } +} + +uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb) +{ + return tlb->num_entries; +} + +/* QOM lifecycle */ + +static void hexagon_tlb_init(Object *obj) +{ +} + +static void hexagon_tlb_realize(DeviceState *dev, Error **errp) +{ + HexagonTLBState *s =3D HEXAGON_TLB(dev); + + if (s->num_entries =3D=3D 0 || s->num_entries > MAX_TLB_ENTRIES) { + error_setg(errp, "Invalid TLB num-entries: %" PRIu32, + s->num_entries); + return; + } + s->entries =3D g_new0(uint64_t, s->num_entries); +} + +static void hexagon_tlb_unrealize(DeviceState *dev) +{ + HexagonTLBState *s =3D HEXAGON_TLB(dev); + g_free(s->entries); + s->entries =3D NULL; +} + +static void hexagon_tlb_reset_hold(Object *obj, ResetType type) +{ + HexagonTLBState *s =3D HEXAGON_TLB(obj); + if (s->entries) { + memset(s->entries, 0, sizeof(uint64_t) * s->num_entries); + } +} + +static const VMStateDescription vmstate_hexagon_tlb =3D { + .name =3D "hexagon-tlb", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(num_entries, HexagonTLBState), + VMSTATE_VARRAY_UINT32_ALLOC(entries, HexagonTLBState, num_entries, + 0, vmstate_info_uint64, uint64_t), + VMSTATE_END_OF_LIST() + }, +}; + +static const Property hexagon_tlb_properties[] =3D { + DEFINE_PROP_UINT32("num-entries", HexagonTLBState, num_entries, + MAX_TLB_ENTRIES), +}; + +static void hexagon_tlb_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->realize =3D hexagon_tlb_realize; + dc->unrealize =3D hexagon_tlb_unrealize; + rc->phases.hold =3D hexagon_tlb_reset_hold; + dc->vmsd =3D &vmstate_hexagon_tlb; + dc->user_creatable =3D false; + device_class_set_props(dc, hexagon_tlb_properties); +} + +static const TypeInfo hexagon_tlb_info =3D { + .name =3D TYPE_HEXAGON_TLB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HexagonTLBState), + .instance_init =3D hexagon_tlb_init, + .class_init =3D hexagon_tlb_class_init, +}; + +static void hexagon_tlb_register_types(void) +{ + type_register_static(&hexagon_tlb_info); +} + +type_init(hexagon_tlb_register_types) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ab5bfb0ed0e..4da1b01fcd1 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -23,6 +23,7 @@ #include "qapi/error.h" #include "hw/core/qdev-properties.h" #include "fpu/softfloat-helpers.h" +#include "hw/hexagon/hexagon_tlb.h" #include "tcg/tcg.h" #include "exec/gdbstub.h" #include "accel/tcg/cpu-ops.h" @@ -50,6 +51,8 @@ static ObjectClass *hexagon_cpu_class_by_name(const char = *cpu_model) } =20 static const Property hexagon_cpu_properties[] =3D { +#if !defined(CONFIG_USER_ONLY) +#endif DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false), DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjus= t, 0, qdev_prop_uint32, target_ulong), --=20 2.34.1