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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775057465346158500 Add cycle counting infrastructure for system emulation: - PCYCLE_ENABLED TB flag to gate cycle counting - gen_pcycle_counters() to emit cycle count increments - Real implementations replacing pcycle stubs in cpu_helper.c - hex_cycle_count TCG global for t_cycle_count - pcycle_enabled context field in DisasContext All pcycle code is guarded by #ifndef CONFIG_USER_ONLY. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/translate.h | 3 +++ target/hexagon/cpu.c | 4 ++++ target/hexagon/cpu_helper.c | 14 +++++++++++--- target/hexagon/translate.c | 26 ++++++++++++++++++++++++++ 5 files changed, 45 insertions(+), 3 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 56f89209795..d3b7b346841 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -161,6 +161,7 @@ struct ArchCPU { #include "cpu_bits.h" =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) +FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 7e528379db6..eaf48a865c2 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -84,6 +84,9 @@ typedef struct DisasContext { TCGv new_pred_value[NUM_PREGS]; TCGv branch_taken; TCGv dczero_addr; + bool pcycle_enabled; + bool pkt_ends_tb; + uint32_t num_cycles; } DisasContext; =20 bool is_gather_store_insn(DisasContext *ctx); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 79ee4264c70..45ac9a3d24e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -275,6 +275,10 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState= *cs) hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } =20 +#ifndef CONFIG_USER_ONLY + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1); +#endif + return (TCGTBCPUState){ .pc =3D pc, .flags =3D hex_flags }; } =20 diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index a2b486f4bb5..bb991a671e8 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -33,17 +33,25 @@ uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_e= nv, int index) =20 uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env) { - g_assert_not_reached(); + uint64_t total =3D 0; + CPUState *cs; + + g_assert(bql_locked()); + CPU_FOREACH(cs) { + CPUHexagonState *thread_env =3D cpu_env(cs); + total +=3D thread_env->t_cycle_count; + } + return total; } =20 uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env) { - g_assert_not_reached(); + return (uint32_t)(hexagon_get_sys_pcycle_count(env) >> 32); } =20 uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env) { - g_assert_not_reached(); + return (uint32_t)(hexagon_get_sys_pcycle_count(env)); } =20 void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 01445fdcbac..91dff442c80 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -61,6 +61,9 @@ TCGv_i64 hex_store_val64[STORES_MAX]; TCGv hex_llsc_addr; TCGv hex_llsc_val; TCGv_i64 hex_llsc_val_i64; +#ifndef CONFIG_USER_ONLY +TCGv_i64 hex_cycle_count; +#endif TCGv hex_vstore_addr[VSTORES_MAX]; TCGv hex_vstore_size[VSTORES_MAX]; TCGv hex_vstore_pending[VSTORES_MAX]; @@ -128,6 +131,15 @@ static void gen_exception_raw(int excp) gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); } =20 +#ifndef CONFIG_USER_ONLY +static void gen_pcycle_counters(DisasContext *ctx) +{ + if (ctx->pcycle_enabled) { + tcg_gen_addi_i64(hex_cycle_count, hex_cycle_count, ctx->num_cycles= ); + } +} +#endif + static void gen_exec_counters(DisasContext *ctx) { tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], @@ -136,6 +148,9 @@ static void gen_exec_counters(DisasContext *ctx) hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT], hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); +#ifndef CONFIG_USER_ONLY + gen_pcycle_counters(ctx); +#endif } =20 static bool use_goto_tb(DisasContext *ctx, target_ulong dest) @@ -821,6 +836,8 @@ static void gen_commit_hvx(DisasContext *ctx) } } =20 +#define PCYCLES_PER_PACKET 1 + static void update_exec_counters(DisasContext *ctx) { Packet *pkt =3D ctx->pkt; @@ -842,6 +859,7 @@ static void update_exec_counters(DisasContext *ctx) ctx->num_packets++; ctx->num_insns +=3D num_real_insns; ctx->num_hvx_insns +=3D num_hvx_insns; + ctx->num_cycles +=3D PCYCLES_PER_PACKET; } =20 static void gen_commit_packet(DisasContext *ctx) @@ -994,6 +1012,10 @@ static void hexagon_tr_init_disas_context(DisasContex= tBase *dcbase, ctx->branch_cond =3D TCG_COND_NEVER; ctx->is_tight_loop =3D FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); ctx->short_circuit =3D hex_cpu->short_circuit; +#ifndef CONFIG_USER_ONLY + ctx->num_cycles =3D 0; + ctx->pcycle_enabled =3D FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED= ); +#endif } =20 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -1136,6 +1158,10 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, llsc_val), "llsc_val"); hex_llsc_val_i64 =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); +#ifndef CONFIG_USER_ONLY + hex_cycle_count =3D tcg_global_mem_new_i64(tcg_env, + offsetof(CPUHexagonState, t_cycle_count), "t_cycle_count"); +#endif for (i =3D 0; i < STORES_MAX; i++) { snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); hex_store_addr[i] =3D tcg_global_mem_new(tcg_env, --=20 2.34.1