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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1775057616900154100 From: Brian Cain Co-authored-by: Sid Manning Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.c | 1 - target/hexagon/cpu_helper.c | 354 ++++++++++++++++++++++++++++++++++++ target/hexagon/op_helper.c | 33 +++- 3 files changed, 384 insertions(+), 4 deletions(-) create mode 100644 target/hexagon/cpu_helper.c diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c79b19d059e..79ee4264c70 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -339,7 +339,6 @@ static void hexagon_cpu_realize(DeviceState *dev, Error= **errp) =20 qemu_init_vcpu(cs); cpu_reset(cs); - mcc->parent_realize(dev, errp); } =20 diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c new file mode 100644 index 00000000000..a2b486f4bb5 --- /dev/null +++ b/target/hexagon/cpu_helper.c @@ -0,0 +1,354 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_helper.h" +#include "system/cpus.h" +#include "hw/core/boards.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/hexagon_globalreg.h" +#include "hex_interrupts.h" +#include "hex_mmu.h" +#include "system/runstate.h" +#include "exec/cpu-interrupt.h" +#include "exec/target_page.h" +#include "accel/tcg/cpu-ldst.h" +#include "exec/cputlb.h" +#include "qemu/log.h" +#include "tcg/tcg-op.h" +#include "internal.h" +#include "macros.h" +#include "sys_macros.h" +#include "arch.h" + + +uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index) +{ + g_assert_not_reached(); +} + +uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env) +{ + g_assert_not_reached(); +} + +uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env) +{ + g_assert_not_reached(); +} + +uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env) +{ + g_assert_not_reached(); +} + +void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val) +{ + g_assert_not_reached(); +} + +void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t val) +{ + g_assert_not_reached(); +} + +void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t val) +{ + g_assert_not_reached(); +} + +static void hexagon_resume_thread(CPUHexagonState *env) +{ + CPUState *cs =3D env_cpu(env); + clear_wait_mode(env); + /* + * The wait instruction keeps the PC pointing to itself + * so that it has an opportunity to check for interrupts. + * + * When we come out of wait mode, adjust the PC to the + * next executable instruction. + */ + env->gpr[HEX_REG_PC] =3D env->wait_next_pc; + cs =3D env_cpu(env); + ASSERT_DIRECT_TO_GUEST_UNSET(env, cs->exception_index); + cs->halted =3D false; + cs->exception_index =3D HEX_EVENT_NONE; + qemu_cpu_kick(cs); +} + +void hexagon_resume_threads(CPUHexagonState *current_env, uint32_t mask) +{ + CPUState *cs; + CPUHexagonState *env; + + g_assert(bql_locked()); + CPU_FOREACH(cs) { + env =3D cpu_env(cs); + g_assert(env->threadId < THREADS_MAX); + if ((mask & (0x1 << env->threadId))) { + if (get_exe_mode(env) =3D=3D HEX_EXE_MODE_WAIT) { + hexagon_resume_thread(env); + } + } + } +} + +void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old) +{ + bool old_EX, old_UM, old_GM, old_IE; + bool new_EX, new_UM, new_GM, new_IE; + uint8_t old_asid, new_asid; + + g_assert(bql_locked()); + + old_EX =3D GET_SSR_FIELD(SSR_EX, old); + old_UM =3D GET_SSR_FIELD(SSR_UM, old); + old_GM =3D GET_SSR_FIELD(SSR_GM, old); + old_IE =3D GET_SSR_FIELD(SSR_IE, old); + new_EX =3D GET_SSR_FIELD(SSR_EX, new); + new_UM =3D GET_SSR_FIELD(SSR_UM, new); + new_GM =3D GET_SSR_FIELD(SSR_GM, new); + new_IE =3D GET_SSR_FIELD(SSR_IE, new); + + if ((old_EX !=3D new_EX) || + (old_UM !=3D new_UM) || + (old_GM !=3D new_GM)) { + hex_mmu_mode_change(env); + } + + old_asid =3D GET_SSR_FIELD(SSR_ASID, old); + new_asid =3D GET_SSR_FIELD(SSR_ASID, new); + if (new_asid !=3D old_asid) { + CPUState *cs =3D env_cpu(env); + tlb_flush(cs); + } + + /* See if the interrupts have been enabled or we have exited EX mode */ + if ((new_IE && !old_IE) || + (!new_EX && old_EX)) { + hex_interrupt_update(env); + } +} + +void clear_wait_mode(CPUHexagonState *env) +{ + HexagonCPU *cpu; + uint32_t modectl, thread_wait_mask; + + g_assert(bql_locked()); + + cpu =3D env_archcpu(env); + if (cpu->globalregs) { + modectl =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL, + env->threadId); + thread_wait_mask =3D GET_FIELD(MODECTL_W, modectl); + thread_wait_mask &=3D ~(0x1 << env->threadId); + SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_W, thread_wait_mas= k); + } +} + +void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause) +{ + uint32_t old, new; + + g_assert(bql_locked()); + + old =3D env->t_sreg[HEX_SREG_SSR]; + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_EX, 1); + SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_CAUSE, cause); + new =3D env->t_sreg[HEX_SREG_SSR]; + + hexagon_modify_ssr(env, new, old); +} + + +int get_exe_mode(CPUHexagonState *env) +{ + HexagonCPU *cpu; + uint32_t modectl, thread_enabled_mask, thread_wait_mask; + uint32_t isdbst, debugmode; + bool E_bit, W_bit, D_bit; + + g_assert(bql_locked()); + + cpu =3D env_archcpu(env); + modectl =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL, + env->threadId) : 0; + thread_enabled_mask =3D GET_FIELD(MODECTL_E, modectl); + E_bit =3D thread_enabled_mask & (0x1 << env->threadId); + thread_wait_mask =3D GET_FIELD(MODECTL_W, modectl); + W_bit =3D thread_wait_mask & (0x1 << env->threadId); + isdbst =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_ISDBST, + env->threadId) : 0; + debugmode =3D GET_FIELD(ISDBST_DEBUGMODE, isdbst); + D_bit =3D debugmode & (0x1 << env->threadId); + + if (!D_bit && !W_bit && !E_bit) { + return HEX_EXE_MODE_OFF; + } + if (!D_bit && !W_bit && E_bit) { + return HEX_EXE_MODE_RUN; + } + if (!D_bit && W_bit && E_bit) { + return HEX_EXE_MODE_WAIT; + } + if (D_bit && !W_bit && E_bit) { + return HEX_EXE_MODE_DEBUG; + } + g_assert_not_reached(); +} + +static uint32_t set_enable_mask(CPUHexagonState *env) +{ + HexagonCPU *cpu; + uint32_t modectl, thread_enabled_mask; + + g_assert(bql_locked()); + + cpu =3D env_archcpu(env); + if (!cpu->globalregs) { + return 0; + } + modectl =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL, + env->threadId); + thread_enabled_mask =3D GET_FIELD(MODECTL_E, modectl); + thread_enabled_mask |=3D 0x1 << env->threadId; + SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_E, thread_enabled_mask= ); + return thread_enabled_mask; +} + +static uint32_t clear_enable_mask(CPUHexagonState *env) +{ + HexagonCPU *cpu; + uint32_t modectl, thread_enabled_mask; + + g_assert(bql_locked()); + + cpu =3D env_archcpu(env); + if (!cpu->globalregs) { + return 0; + } + modectl =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL, + env->threadId); + thread_enabled_mask =3D GET_FIELD(MODECTL_E, modectl); + thread_enabled_mask &=3D ~(0x1 << env->threadId); + SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_E, thread_enabled_mask= ); + return thread_enabled_mask; +} +static void do_start_thread(CPUState *cs, run_on_cpu_data tbd) +{ + CPUHexagonState *env; + + BQL_LOCK_GUARD(); + + env =3D cpu_env(cs); + + hexagon_cpu_soft_reset(env); + + set_enable_mask(env); + + cs->halted =3D 0; + cs->exception_index =3D HEX_EVENT_NONE; + cpu_resume(cs); +} + +void hexagon_start_threads(CPUHexagonState *current_env, uint32_t mask) +{ + CPUState *cs; + CPU_FOREACH(cs) { + CPUHexagonState *env =3D cpu_env(cs); + if (!(mask & (0x1 << env->threadId))) { + continue; + } + + if (current_env->threadId !=3D env->threadId) { + async_safe_run_on_cpu(cs, do_start_thread, RUN_ON_CPU_NULL); + } + } +} + +/* + * When we have all threads stopped, the return + * value to the shell is register 2 from thread 0. + */ +static uint32_t get_thread0_r2(void) +{ + CPUState *cs; + CPU_FOREACH(cs) { + CPUHexagonState *thread =3D cpu_env(cs); + if (thread->threadId =3D=3D 0) { + return thread->gpr[2]; + } + } + g_assert_not_reached(); +} + +void hexagon_stop_thread(CPUHexagonState *env) +{ + uint32_t thread_enabled_mask; + CPUState *cs; + + BQL_LOCK_GUARD(); + + thread_enabled_mask =3D clear_enable_mask(env); + cs =3D env_cpu(env); + cpu_interrupt(cs, CPU_INTERRUPT_HALT); + if (!thread_enabled_mask) { + /* All threads are stopped, request shutdown */ + qemu_system_shutdown_request_with_code( + SHUTDOWN_CAUSE_GUEST_SHUTDOWN, get_thread0_r2()); + } +} + +static int sys_in_monitor_mode_ssr(uint32_t ssr) +{ + if ((GET_SSR_FIELD(SSR_EX, ssr) !=3D 0) || + ((GET_SSR_FIELD(SSR_EX, ssr) =3D=3D 0) && + (GET_SSR_FIELD(SSR_UM, ssr) =3D=3D 0))) { + return 1; + } + return 0; +} + +static int sys_in_guest_mode_ssr(uint32_t ssr) +{ + if ((GET_SSR_FIELD(SSR_EX, ssr) =3D=3D 0) && + (GET_SSR_FIELD(SSR_UM, ssr) !=3D 0) && + (GET_SSR_FIELD(SSR_GM, ssr) !=3D 0)) { + return 1; + } + return 0; +} + +static int sys_in_user_mode_ssr(uint32_t ssr) +{ + if ((GET_SSR_FIELD(SSR_EX, ssr) =3D=3D 0) && + (GET_SSR_FIELD(SSR_UM, ssr) !=3D 0) && + (GET_SSR_FIELD(SSR_GM, ssr) =3D=3D 0)) { + return 1; + } + return 0; +} + +int get_cpu_mode(CPUHexagonState *env) +{ + uint32_t ssr =3D env->t_sreg[HEX_SREG_SSR]; + + if (sys_in_monitor_mode_ssr(ssr)) { + return HEX_CPU_MODE_MONITOR; + } else if (sys_in_guest_mode_ssr(ssr)) { + return HEX_CPU_MODE_GUEST; + } else if (sys_in_user_mode_ssr(ssr)) { + return HEX_CPU_MODE_USER; + } + return HEX_CPU_MODE_MONITOR; +} diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 87da1fe430c..947988d2456 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -19,6 +19,7 @@ #include "qemu/log.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" @@ -1451,17 +1452,43 @@ void HELPER(setimask)(CPUHexagonState *env, uint32_= t tid, uint32_t imask) =20 void HELPER(sreg_write_masked)(CPUHexagonState *env, uint32_t reg, uint32_= t val) { - g_assert_not_reached(); + BQL_LOCK_GUARD(); + if (reg < HEX_SREG_GLB_START) { + env->t_sreg[reg] =3D val; + } else { + HexagonCPU *cpu =3D env_archcpu(env); + if (cpu->globalregs) { + hexagon_globalreg_write_masked(cpu->globalregs, reg, val); + } + } +} + +static inline QEMU_ALWAYS_INLINE uint32_t sreg_read(CPUHexagonState *env, + uint32_t reg) +{ + HexagonCPU *cpu; + + g_assert(bql_locked()); + if (reg < HEX_SREG_GLB_START) { + return env->t_sreg[reg]; + } + cpu =3D env_archcpu(env); + return cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, reg, env->threadId) : 0; } =20 uint32_t HELPER(sreg_read)(CPUHexagonState *env, uint32_t reg) { - g_assert_not_reached(); + BQL_LOCK_GUARD(); + return sreg_read(env, reg); } =20 uint64_t HELPER(sreg_read_pair)(CPUHexagonState *env, uint32_t reg) { - g_assert_not_reached(); + BQL_LOCK_GUARD(); + + return deposit64((uint64_t) sreg_read(env, reg), 32, 32, + sreg_read(env, reg + 1)); } =20 uint32_t HELPER(greg_read)(CPUHexagonState *env, uint32_t reg) --=20 2.34.1